Struct k210_pac::uart1::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub rbr_dll_thr: RBR_DLL_THR,
    pub dlh_ier: DLH_IER,
    pub fcr_iir: FCR_IIR,
    pub lcr: LCR,
    pub mcr: MCR,
    pub lsr: LSR,
    pub msr: MSR,
    pub scr: SCR,
    pub lpdll: LPDLL,
    pub lpdlh: LPDLH,
    pub srbr_sthr: [SRBR_STHR; 16],
    pub far: FAR,
    pub tfr: TFR,
    pub rfw: RFW,
    pub usr: USR,
    pub tfl: TFL,
    pub rfl: RFL,
    pub srr: SRR,
    pub srts: SRTS,
    pub sbcr: SBCR,
    pub sdmam: SDMAM,
    pub sfe: SFE,
    pub srt: SRT,
    pub stet: STET,
    pub htx: HTX,
    pub dmasa: DMASA,
    pub tcr: TCR,
    pub de_en: DE_EN,
    pub re_en: RE_EN,
    pub det: DET,
    pub tat: TAT,
    pub dlf: DLF,
    pub rar: RAR,
    pub tar: TAR,
    pub lcr_ext: LCR_EXT,
    pub cpr: CPR,
    pub ucv: UCV,
    pub ctr: CTR,
    // some fields omitted
}

Register block

Fields

rbr_dll_thr: RBR_DLL_THR

0x00 - Receive Buffer Register / Divisor Latch (Low) / Transmit Holding Register (depending on context and R/W)

dlh_ier: DLH_IER

0x04 - Divisor Latch (High) / Interrupt Enable Register

fcr_iir: FCR_IIR

0x08 - FIFO Control Register / Interrupt Identification Register

lcr: LCR

0x0c - Line Control Register

mcr: MCR

0x10 - Modem Control Register

lsr: LSR

0x14 - Line Status Register

msr: MSR

0x18 - Modem Status Register

scr: SCR

0x1c - Scratchpad Register

lpdll: LPDLL

0x20 - Low Power Divisor Latch (Low) Register

lpdlh: LPDLH

0x24 - Low Power Divisor Latch (High) Register

srbr_sthr: [SRBR_STHR; 16]

0x30 - Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W)

far: FAR

0x70 - FIFO Access Register

tfr: TFR

0x74 - Transmit FIFO Read Register

rfw: RFW

0x78 - Receive FIFO Write Register

usr: USR

0x7c - UART Status Register

tfl: TFL

0x80 - Transmit FIFO Level

rfl: RFL

0x84 - Receive FIFO Level

srr: SRR

0x88 - Software Reset Register

srts: SRTS

0x8c - Shadow Request to Send Register

sbcr: SBCR

0x90 - Shadow Break Control Register

sdmam: SDMAM

0x94 - Shadow DMA Mode

sfe: SFE

0x98 - Shadow FIFO Enable

srt: SRT

0x9c - Shadow RCVR Trigger Register

stet: STET

0xa0 - Shadow TX Empty Trigger Register

htx: HTX

0xa4 - Halt TX Regster

dmasa: DMASA

0xa8 - DMA Software Acknowledge Register

tcr: TCR

0xac - Transfer Control Register

de_en: DE_EN

0xb0 - DE Enable Register

re_en: RE_EN

0xb4 - RE Enable Register

det: DET

0xb8 - DE Assertion Time Register

tat: TAT

0xbc - Turn-Around Time Register

dlf: DLF

0xc0 - Divisor Latch (Fractional) Register

rar: RAR

0xc4 - Receive-Mode Address Register

tar: TAR

0xc8 - Transmit-Mode Address Register

lcr_ext: LCR_EXT

0xcc - Line Control Register (Extended)

cpr: CPR

0xf4 - Component Parameter Register

ucv: UCV

0xf8 - UART Component Version

ctr: CTR

0xfc - Component Type Register