[][src]Type Definition imxrt1062_usbphy1::ctrl_tog::R

type R = R<u32, CTRL_TOG>;

Reader of register CTRL_TOG

Methods

impl R[src]

pub fn enotg_id_chg_irq(&self) -> ENOTG_ID_CHG_IRQ_R[src]

Bit 0 - Enable OTG_ID_CHG_IRQ.

pub fn enhostdiscondetect(&self) -> ENHOSTDISCONDETECT_R[src]

Bit 1 - For host mode, enables high-speed disconnect detector

pub fn enirqhostdiscon(&self) -> ENIRQHOSTDISCON_R[src]

Bit 2 - Enables interrupt for detection of disconnection to Device when in high-speed host mode

pub fn hostdiscondetect_irq(&self) -> HOSTDISCONDETECT_IRQ_R[src]

Bit 3 - Indicates that the device has disconnected in high-speed mode

pub fn endevplugindetect(&self) -> ENDEVPLUGINDETECT_R[src]

Bit 4 - For device mode, enables 200-KOhm pullups for detecting connectivity to the host.

pub fn devplugin_polarity(&self) -> DEVPLUGIN_POLARITY_R[src]

Bit 5 - For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in

pub fn otg_id_chg_irq(&self) -> OTG_ID_CHG_IRQ_R[src]

Bit 6 - OTG ID change interrupt. Indicates the value of ID pin changed.

pub fn enotgiddetect(&self) -> ENOTGIDDETECT_R[src]

Bit 7 - Enables circuit to detect resistance of MiniAB ID pin.

pub fn resumeirqsticky(&self) -> RESUMEIRQSTICKY_R[src]

Bit 8 - Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it

pub fn enirqresumedetect(&self) -> ENIRQRESUMEDETECT_R[src]

Bit 9 - Enables interrupt for detection of a non-J state on the USB line

pub fn resume_irq(&self) -> RESUME_IRQ_R[src]

Bit 10 - Indicates that the host is sending a wake-up after suspend

pub fn enirqdevplugin(&self) -> ENIRQDEVPLUGIN_R[src]

Bit 11 - Enables interrupt for the detection of connectivity to the USB line.

pub fn devplugin_irq(&self) -> DEVPLUGIN_IRQ_R[src]

Bit 12 - Indicates that the device is connected

pub fn data_on_lradc(&self) -> DATA_ON_LRADC_R[src]

Bit 13 - Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.

pub fn enutmilevel2(&self) -> ENUTMILEVEL2_R[src]

Bit 14 - Enables UTMI+ Level2. This should be enabled if needs to support LS device

pub fn enutmilevel3(&self) -> ENUTMILEVEL3_R[src]

Bit 15 - Enables UTMI+ Level3

pub fn enirqwakeup(&self) -> ENIRQWAKEUP_R[src]

Bit 16 - Enables interrupt for the wakeup events.

pub fn wakeup_irq(&self) -> WAKEUP_IRQ_R[src]

Bit 17 - Indicates that there is a wakeup event

pub fn enauto_pwron_pll(&self) -> ENAUTO_PWRON_PLL_R[src]

Bit 18 - Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended

pub fn enautoclr_clkgate(&self) -> ENAUTOCLR_CLKGATE_R[src]

Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

pub fn enautoclr_phy_pwd(&self) -> ENAUTOCLR_PHY_PWD_R[src]

Bit 20 - Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended

pub fn endpdmchg_wkup(&self) -> ENDPDMCHG_WKUP_R[src]

Bit 21 - Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended

pub fn enidchg_wkup(&self) -> ENIDCHG_WKUP_R[src]

Bit 22 - Enables the feature to wakeup USB if ID is toggled when USB is suspended.

pub fn envbuschg_wkup(&self) -> ENVBUSCHG_WKUP_R[src]

Bit 23 - Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.

pub fn fsdll_rst_en(&self) -> FSDLL_RST_EN_R[src]

Bit 24 - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.

pub fn rsvd1(&self) -> RSVD1_R[src]

Bits 25:26 - Reserved.

pub fn otg_id_value(&self) -> OTG_ID_VALUE_R[src]

Bit 27 - Almost same as OTGID_STATUS in USBPHYx_STATUS Register

pub fn host_force_ls_se0(&self) -> HOST_FORCE_LS_SE0_R[src]

Bit 28 - Forces the next FS packet that is transmitted to have a EOP with LS timing

pub fn utmi_suspendm(&self) -> UTMI_SUSPENDM_R[src]

Bit 29 - Used by the PHY to indicate a powered-down state

pub fn clkgate(&self) -> CLKGATE_R[src]

Bit 30 - Gate UTMI Clocks

pub fn sftrst(&self) -> SFTRST_R[src]

Bit 31 - Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers