Struct imxrt1062_usbphy1::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _PWD>>

pub fn txpwdfs(&mut self) -> TXPWDFS_W

Bit 10 - 0 = Normal operation

pub fn txpwdibias(&mut self) -> TXPWDIBIAS_W

Bit 11 - 0 = Normal operation

pub fn txpwdv2i(&mut self) -> TXPWDV2I_W

Bit 12 - 0 = Normal operation

pub fn rxpwdenv(&mut self) -> RXPWDENV_W

Bit 17 - 0 = Normal operation

pub fn rxpwd1pt1(&mut self) -> RXPWD1PT1_W

Bit 18 - 0 = Normal operation

pub fn rxpwddiff(&mut self) -> RXPWDDIFF_W

Bit 19 - 0 = Normal operation

pub fn rxpwdrx(&mut self) -> RXPWDRX_W

Bit 20 - 0 = Normal operation

impl W<u32, Reg<u32, _PWD_SET>>

pub fn txpwdfs(&mut self) -> TXPWDFS_W

Bit 10 - 0 = Normal operation

pub fn txpwdibias(&mut self) -> TXPWDIBIAS_W

Bit 11 - 0 = Normal operation

pub fn txpwdv2i(&mut self) -> TXPWDV2I_W

Bit 12 - 0 = Normal operation

pub fn rxpwdenv(&mut self) -> RXPWDENV_W

Bit 17 - 0 = Normal operation

pub fn rxpwd1pt1(&mut self) -> RXPWD1PT1_W

Bit 18 - 0 = Normal operation

pub fn rxpwddiff(&mut self) -> RXPWDDIFF_W

Bit 19 - 0 = Normal operation

pub fn rxpwdrx(&mut self) -> RXPWDRX_W

Bit 20 - 0 = Normal operation

impl W<u32, Reg<u32, _PWD_CLR>>

pub fn txpwdfs(&mut self) -> TXPWDFS_W

Bit 10 - 0 = Normal operation

pub fn txpwdibias(&mut self) -> TXPWDIBIAS_W

Bit 11 - 0 = Normal operation

pub fn txpwdv2i(&mut self) -> TXPWDV2I_W

Bit 12 - 0 = Normal operation

pub fn rxpwdenv(&mut self) -> RXPWDENV_W

Bit 17 - 0 = Normal operation

pub fn rxpwd1pt1(&mut self) -> RXPWD1PT1_W

Bit 18 - 0 = Normal operation

pub fn rxpwddiff(&mut self) -> RXPWDDIFF_W

Bit 19 - 0 = Normal operation

pub fn rxpwdrx(&mut self) -> RXPWDRX_W

Bit 20 - 0 = Normal operation

impl W<u32, Reg<u32, _PWD_TOG>>

pub fn txpwdfs(&mut self) -> TXPWDFS_W

Bit 10 - 0 = Normal operation

pub fn txpwdibias(&mut self) -> TXPWDIBIAS_W

Bit 11 - 0 = Normal operation

pub fn txpwdv2i(&mut self) -> TXPWDV2I_W

Bit 12 - 0 = Normal operation

pub fn rxpwdenv(&mut self) -> RXPWDENV_W

Bit 17 - 0 = Normal operation

pub fn rxpwd1pt1(&mut self) -> RXPWD1PT1_W

Bit 18 - 0 = Normal operation

pub fn rxpwddiff(&mut self) -> RXPWDDIFF_W

Bit 19 - 0 = Normal operation

pub fn rxpwdrx(&mut self) -> RXPWDRX_W

Bit 20 - 0 = Normal operation

impl W<u32, Reg<u32, _TX>>

pub fn d_cal(&mut self) -> D_CAL_W

Bits 0:3 - Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%

pub fn rsvd0(&mut self) -> RSVD0_W

Bits 4:7 - Reserved. Note: This bit should remain clear.

pub fn txcal45dn(&mut self) -> TXCAL45DN_W

Bits 8:11 - Decode to select a 45-Ohm resistance to the USB_DN output pin

pub fn rsvd1(&mut self) -> RSVD1_W

Bits 12:15 - Reserved. Note: This bit should remain clear.

pub fn txcal45dp(&mut self) -> TXCAL45DP_W

Bits 16:19 - Decode to select a 45-Ohm resistance to the USB_DP output pin

pub fn usbphy_tx_edgectrl(&mut self) -> USBPHY_TX_EDGECTRL_W

Bits 26:28 - Controls the edge-rate of the current sensing transistors used in HS transmit

impl W<u32, Reg<u32, _TX_SET>>

pub fn d_cal(&mut self) -> D_CAL_W

Bits 0:3 - Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%

pub fn rsvd0(&mut self) -> RSVD0_W

Bits 4:7 - Reserved. Note: This bit should remain clear.

pub fn txcal45dn(&mut self) -> TXCAL45DN_W

Bits 8:11 - Decode to select a 45-Ohm resistance to the USB_DN output pin

pub fn rsvd1(&mut self) -> RSVD1_W

Bits 12:15 - Reserved. Note: This bit should remain clear.

pub fn txcal45dp(&mut self) -> TXCAL45DP_W

Bits 16:19 - Decode to select a 45-Ohm resistance to the USB_DP output pin

pub fn usbphy_tx_edgectrl(&mut self) -> USBPHY_TX_EDGECTRL_W

Bits 26:28 - Controls the edge-rate of the current sensing transistors used in HS transmit

impl W<u32, Reg<u32, _TX_CLR>>

pub fn d_cal(&mut self) -> D_CAL_W

Bits 0:3 - Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%

pub fn rsvd0(&mut self) -> RSVD0_W

Bits 4:7 - Reserved. Note: This bit should remain clear.

pub fn txcal45dn(&mut self) -> TXCAL45DN_W

Bits 8:11 - Decode to select a 45-Ohm resistance to the USB_DN output pin

pub fn rsvd1(&mut self) -> RSVD1_W

Bits 12:15 - Reserved. Note: This bit should remain clear.

pub fn txcal45dp(&mut self) -> TXCAL45DP_W

Bits 16:19 - Decode to select a 45-Ohm resistance to the USB_DP output pin

pub fn usbphy_tx_edgectrl(&mut self) -> USBPHY_TX_EDGECTRL_W

Bits 26:28 - Controls the edge-rate of the current sensing transistors used in HS transmit

impl W<u32, Reg<u32, _TX_TOG>>

pub fn d_cal(&mut self) -> D_CAL_W

Bits 0:3 - Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%

pub fn rsvd0(&mut self) -> RSVD0_W

Bits 4:7 - Reserved. Note: This bit should remain clear.

pub fn txcal45dn(&mut self) -> TXCAL45DN_W

Bits 8:11 - Decode to select a 45-Ohm resistance to the USB_DN output pin

pub fn rsvd1(&mut self) -> RSVD1_W

Bits 12:15 - Reserved. Note: This bit should remain clear.

pub fn txcal45dp(&mut self) -> TXCAL45DP_W

Bits 16:19 - Decode to select a 45-Ohm resistance to the USB_DP output pin

pub fn usbphy_tx_edgectrl(&mut self) -> USBPHY_TX_EDGECTRL_W

Bits 26:28 - Controls the edge-rate of the current sensing transistors used in HS transmit

impl W<u32, Reg<u32, _RX>>

pub fn envadj(&mut self) -> ENVADJ_W

Bits 0:2 - The ENVADJ field adjusts the trip point for the envelope detector

pub fn disconadj(&mut self) -> DISCONADJ_W

Bits 4:6 - The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0

pub fn rxdbypass(&mut self) -> RXDBYPASS_W

Bit 22 - 0 = Normal operation

impl W<u32, Reg<u32, _RX_SET>>

pub fn envadj(&mut self) -> ENVADJ_W

Bits 0:2 - The ENVADJ field adjusts the trip point for the envelope detector

pub fn disconadj(&mut self) -> DISCONADJ_W

Bits 4:6 - The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0

pub fn rxdbypass(&mut self) -> RXDBYPASS_W

Bit 22 - 0 = Normal operation

impl W<u32, Reg<u32, _RX_CLR>>

pub fn envadj(&mut self) -> ENVADJ_W

Bits 0:2 - The ENVADJ field adjusts the trip point for the envelope detector

pub fn disconadj(&mut self) -> DISCONADJ_W

Bits 4:6 - The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0

pub fn rxdbypass(&mut self) -> RXDBYPASS_W

Bit 22 - 0 = Normal operation

impl W<u32, Reg<u32, _RX_TOG>>

pub fn envadj(&mut self) -> ENVADJ_W

Bits 0:2 - The ENVADJ field adjusts the trip point for the envelope detector

pub fn disconadj(&mut self) -> DISCONADJ_W

Bits 4:6 - The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0

pub fn rxdbypass(&mut self) -> RXDBYPASS_W

Bit 22 - 0 = Normal operation

impl W<u32, Reg<u32, _CTRL>>

pub fn enotg_id_chg_irq(&mut self) -> ENOTG_ID_CHG_IRQ_W

Bit 0 - Enable OTG_ID_CHG_IRQ.

pub fn enhostdiscondetect(&mut self) -> ENHOSTDISCONDETECT_W

Bit 1 - For host mode, enables high-speed disconnect detector

pub fn enirqhostdiscon(&mut self) -> ENIRQHOSTDISCON_W

Bit 2 - Enables interrupt for detection of disconnection to Device when in high-speed host mode

pub fn hostdiscondetect_irq(&mut self) -> HOSTDISCONDETECT_IRQ_W

Bit 3 - Indicates that the device has disconnected in high-speed mode

pub fn endevplugindetect(&mut self) -> ENDEVPLUGINDETECT_W

Bit 4 - For device mode, enables 200-KOhm pullups for detecting connectivity to the host.

pub fn devplugin_polarity(&mut self) -> DEVPLUGIN_POLARITY_W

Bit 5 - For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in

pub fn otg_id_chg_irq(&mut self) -> OTG_ID_CHG_IRQ_W

Bit 6 - OTG ID change interrupt. Indicates the value of ID pin changed.

pub fn enotgiddetect(&mut self) -> ENOTGIDDETECT_W

Bit 7 - Enables circuit to detect resistance of MiniAB ID pin.

pub fn resumeirqsticky(&mut self) -> RESUMEIRQSTICKY_W

Bit 8 - Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it

pub fn enirqresumedetect(&mut self) -> ENIRQRESUMEDETECT_W

Bit 9 - Enables interrupt for detection of a non-J state on the USB line

pub fn resume_irq(&mut self) -> RESUME_IRQ_W

Bit 10 - Indicates that the host is sending a wake-up after suspend

pub fn enirqdevplugin(&mut self) -> ENIRQDEVPLUGIN_W

Bit 11 - Enables interrupt for the detection of connectivity to the USB line.

pub fn devplugin_irq(&mut self) -> DEVPLUGIN_IRQ_W

Bit 12 - Indicates that the device is connected

pub fn data_on_lradc(&mut self) -> DATA_ON_LRADC_W

Bit 13 - Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.

pub fn enutmilevel2(&mut self) -> ENUTMILEVEL2_W

Bit 14 - Enables UTMI+ Level2. This should be enabled if needs to support LS device

pub fn enutmilevel3(&mut self) -> ENUTMILEVEL3_W

Bit 15 - Enables UTMI+ Level3

pub fn enirqwakeup(&mut self) -> ENIRQWAKEUP_W

Bit 16 - Enables interrupt for the wakeup events.

pub fn wakeup_irq(&mut self) -> WAKEUP_IRQ_W

Bit 17 - Indicates that there is a wakeup event

pub fn enauto_pwron_pll(&mut self) -> ENAUTO_PWRON_PLL_W

Bit 18 - Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended

pub fn enautoclr_clkgate(&mut self) -> ENAUTOCLR_CLKGATE_W

Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

pub fn enautoclr_phy_pwd(&mut self) -> ENAUTOCLR_PHY_PWD_W

Bit 20 - Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended

pub fn endpdmchg_wkup(&mut self) -> ENDPDMCHG_WKUP_W

Bit 21 - Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended

pub fn enidchg_wkup(&mut self) -> ENIDCHG_WKUP_W

Bit 22 - Enables the feature to wakeup USB if ID is toggled when USB is suspended.

pub fn envbuschg_wkup(&mut self) -> ENVBUSCHG_WKUP_W

Bit 23 - Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.

pub fn fsdll_rst_en(&mut self) -> FSDLL_RST_EN_W

Bit 24 - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.

pub fn host_force_ls_se0(&mut self) -> HOST_FORCE_LS_SE0_W

Bit 28 - Forces the next FS packet that is transmitted to have a EOP with LS timing

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - Gate UTMI Clocks

pub fn sftrst(&mut self) -> SFTRST_W

Bit 31 - Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers

impl W<u32, Reg<u32, _CTRL_SET>>

pub fn enotg_id_chg_irq(&mut self) -> ENOTG_ID_CHG_IRQ_W

Bit 0 - Enable OTG_ID_CHG_IRQ.

pub fn enhostdiscondetect(&mut self) -> ENHOSTDISCONDETECT_W

Bit 1 - For host mode, enables high-speed disconnect detector

pub fn enirqhostdiscon(&mut self) -> ENIRQHOSTDISCON_W

Bit 2 - Enables interrupt for detection of disconnection to Device when in high-speed host mode

pub fn hostdiscondetect_irq(&mut self) -> HOSTDISCONDETECT_IRQ_W

Bit 3 - Indicates that the device has disconnected in high-speed mode

pub fn endevplugindetect(&mut self) -> ENDEVPLUGINDETECT_W

Bit 4 - For device mode, enables 200-KOhm pullups for detecting connectivity to the host.

pub fn devplugin_polarity(&mut self) -> DEVPLUGIN_POLARITY_W

Bit 5 - For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in

pub fn otg_id_chg_irq(&mut self) -> OTG_ID_CHG_IRQ_W

Bit 6 - OTG ID change interrupt. Indicates the value of ID pin changed.

pub fn enotgiddetect(&mut self) -> ENOTGIDDETECT_W

Bit 7 - Enables circuit to detect resistance of MiniAB ID pin.

pub fn resumeirqsticky(&mut self) -> RESUMEIRQSTICKY_W

Bit 8 - Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it

pub fn enirqresumedetect(&mut self) -> ENIRQRESUMEDETECT_W

Bit 9 - Enables interrupt for detection of a non-J state on the USB line

pub fn resume_irq(&mut self) -> RESUME_IRQ_W

Bit 10 - Indicates that the host is sending a wake-up after suspend

pub fn enirqdevplugin(&mut self) -> ENIRQDEVPLUGIN_W

Bit 11 - Enables interrupt for the detection of connectivity to the USB line.

pub fn devplugin_irq(&mut self) -> DEVPLUGIN_IRQ_W

Bit 12 - Indicates that the device is connected

pub fn data_on_lradc(&mut self) -> DATA_ON_LRADC_W

Bit 13 - Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.

pub fn enutmilevel2(&mut self) -> ENUTMILEVEL2_W

Bit 14 - Enables UTMI+ Level2. This should be enabled if needs to support LS device

pub fn enutmilevel3(&mut self) -> ENUTMILEVEL3_W

Bit 15 - Enables UTMI+ Level3

pub fn enirqwakeup(&mut self) -> ENIRQWAKEUP_W

Bit 16 - Enables interrupt for the wakeup events.

pub fn wakeup_irq(&mut self) -> WAKEUP_IRQ_W

Bit 17 - Indicates that there is a wakeup event

pub fn enauto_pwron_pll(&mut self) -> ENAUTO_PWRON_PLL_W

Bit 18 - Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended

pub fn enautoclr_clkgate(&mut self) -> ENAUTOCLR_CLKGATE_W

Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

pub fn enautoclr_phy_pwd(&mut self) -> ENAUTOCLR_PHY_PWD_W

Bit 20 - Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended

pub fn endpdmchg_wkup(&mut self) -> ENDPDMCHG_WKUP_W

Bit 21 - Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended

pub fn enidchg_wkup(&mut self) -> ENIDCHG_WKUP_W

Bit 22 - Enables the feature to wakeup USB if ID is toggled when USB is suspended.

pub fn envbuschg_wkup(&mut self) -> ENVBUSCHG_WKUP_W

Bit 23 - Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.

pub fn fsdll_rst_en(&mut self) -> FSDLL_RST_EN_W

Bit 24 - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.

pub fn host_force_ls_se0(&mut self) -> HOST_FORCE_LS_SE0_W

Bit 28 - Forces the next FS packet that is transmitted to have a EOP with LS timing

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - Gate UTMI Clocks

pub fn sftrst(&mut self) -> SFTRST_W

Bit 31 - Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers

impl W<u32, Reg<u32, _CTRL_CLR>>

pub fn enotg_id_chg_irq(&mut self) -> ENOTG_ID_CHG_IRQ_W

Bit 0 - Enable OTG_ID_CHG_IRQ.

pub fn enhostdiscondetect(&mut self) -> ENHOSTDISCONDETECT_W

Bit 1 - For host mode, enables high-speed disconnect detector

pub fn enirqhostdiscon(&mut self) -> ENIRQHOSTDISCON_W

Bit 2 - Enables interrupt for detection of disconnection to Device when in high-speed host mode

pub fn hostdiscondetect_irq(&mut self) -> HOSTDISCONDETECT_IRQ_W

Bit 3 - Indicates that the device has disconnected in high-speed mode

pub fn endevplugindetect(&mut self) -> ENDEVPLUGINDETECT_W

Bit 4 - For device mode, enables 200-KOhm pullups for detecting connectivity to the host.

pub fn devplugin_polarity(&mut self) -> DEVPLUGIN_POLARITY_W

Bit 5 - For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in

pub fn otg_id_chg_irq(&mut self) -> OTG_ID_CHG_IRQ_W

Bit 6 - OTG ID change interrupt. Indicates the value of ID pin changed.

pub fn enotgiddetect(&mut self) -> ENOTGIDDETECT_W

Bit 7 - Enables circuit to detect resistance of MiniAB ID pin.

pub fn resumeirqsticky(&mut self) -> RESUMEIRQSTICKY_W

Bit 8 - Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it

pub fn enirqresumedetect(&mut self) -> ENIRQRESUMEDETECT_W

Bit 9 - Enables interrupt for detection of a non-J state on the USB line

pub fn resume_irq(&mut self) -> RESUME_IRQ_W

Bit 10 - Indicates that the host is sending a wake-up after suspend

pub fn enirqdevplugin(&mut self) -> ENIRQDEVPLUGIN_W

Bit 11 - Enables interrupt for the detection of connectivity to the USB line.

pub fn devplugin_irq(&mut self) -> DEVPLUGIN_IRQ_W

Bit 12 - Indicates that the device is connected

pub fn data_on_lradc(&mut self) -> DATA_ON_LRADC_W

Bit 13 - Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.

pub fn enutmilevel2(&mut self) -> ENUTMILEVEL2_W

Bit 14 - Enables UTMI+ Level2. This should be enabled if needs to support LS device

pub fn enutmilevel3(&mut self) -> ENUTMILEVEL3_W

Bit 15 - Enables UTMI+ Level3

pub fn enirqwakeup(&mut self) -> ENIRQWAKEUP_W

Bit 16 - Enables interrupt for the wakeup events.

pub fn wakeup_irq(&mut self) -> WAKEUP_IRQ_W

Bit 17 - Indicates that there is a wakeup event

pub fn enauto_pwron_pll(&mut self) -> ENAUTO_PWRON_PLL_W

Bit 18 - Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended

pub fn enautoclr_clkgate(&mut self) -> ENAUTOCLR_CLKGATE_W

Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

pub fn enautoclr_phy_pwd(&mut self) -> ENAUTOCLR_PHY_PWD_W

Bit 20 - Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended

pub fn endpdmchg_wkup(&mut self) -> ENDPDMCHG_WKUP_W

Bit 21 - Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended

pub fn enidchg_wkup(&mut self) -> ENIDCHG_WKUP_W

Bit 22 - Enables the feature to wakeup USB if ID is toggled when USB is suspended.

pub fn envbuschg_wkup(&mut self) -> ENVBUSCHG_WKUP_W

Bit 23 - Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.

pub fn fsdll_rst_en(&mut self) -> FSDLL_RST_EN_W

Bit 24 - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.

pub fn host_force_ls_se0(&mut self) -> HOST_FORCE_LS_SE0_W

Bit 28 - Forces the next FS packet that is transmitted to have a EOP with LS timing

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - Gate UTMI Clocks

pub fn sftrst(&mut self) -> SFTRST_W

Bit 31 - Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers

impl W<u32, Reg<u32, _CTRL_TOG>>

pub fn enotg_id_chg_irq(&mut self) -> ENOTG_ID_CHG_IRQ_W

Bit 0 - Enable OTG_ID_CHG_IRQ.

pub fn enhostdiscondetect(&mut self) -> ENHOSTDISCONDETECT_W

Bit 1 - For host mode, enables high-speed disconnect detector

pub fn enirqhostdiscon(&mut self) -> ENIRQHOSTDISCON_W

Bit 2 - Enables interrupt for detection of disconnection to Device when in high-speed host mode

pub fn hostdiscondetect_irq(&mut self) -> HOSTDISCONDETECT_IRQ_W

Bit 3 - Indicates that the device has disconnected in high-speed mode

pub fn endevplugindetect(&mut self) -> ENDEVPLUGINDETECT_W

Bit 4 - For device mode, enables 200-KOhm pullups for detecting connectivity to the host.

pub fn devplugin_polarity(&mut self) -> DEVPLUGIN_POLARITY_W

Bit 5 - For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in

pub fn otg_id_chg_irq(&mut self) -> OTG_ID_CHG_IRQ_W

Bit 6 - OTG ID change interrupt. Indicates the value of ID pin changed.

pub fn enotgiddetect(&mut self) -> ENOTGIDDETECT_W

Bit 7 - Enables circuit to detect resistance of MiniAB ID pin.

pub fn resumeirqsticky(&mut self) -> RESUMEIRQSTICKY_W

Bit 8 - Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it

pub fn enirqresumedetect(&mut self) -> ENIRQRESUMEDETECT_W

Bit 9 - Enables interrupt for detection of a non-J state on the USB line

pub fn resume_irq(&mut self) -> RESUME_IRQ_W

Bit 10 - Indicates that the host is sending a wake-up after suspend

pub fn enirqdevplugin(&mut self) -> ENIRQDEVPLUGIN_W

Bit 11 - Enables interrupt for the detection of connectivity to the USB line.

pub fn devplugin_irq(&mut self) -> DEVPLUGIN_IRQ_W

Bit 12 - Indicates that the device is connected

pub fn data_on_lradc(&mut self) -> DATA_ON_LRADC_W

Bit 13 - Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.

pub fn enutmilevel2(&mut self) -> ENUTMILEVEL2_W

Bit 14 - Enables UTMI+ Level2. This should be enabled if needs to support LS device

pub fn enutmilevel3(&mut self) -> ENUTMILEVEL3_W

Bit 15 - Enables UTMI+ Level3

pub fn enirqwakeup(&mut self) -> ENIRQWAKEUP_W

Bit 16 - Enables interrupt for the wakeup events.

pub fn wakeup_irq(&mut self) -> WAKEUP_IRQ_W

Bit 17 - Indicates that there is a wakeup event

pub fn enauto_pwron_pll(&mut self) -> ENAUTO_PWRON_PLL_W

Bit 18 - Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended

pub fn enautoclr_clkgate(&mut self) -> ENAUTOCLR_CLKGATE_W

Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

pub fn enautoclr_phy_pwd(&mut self) -> ENAUTOCLR_PHY_PWD_W

Bit 20 - Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended

pub fn endpdmchg_wkup(&mut self) -> ENDPDMCHG_WKUP_W

Bit 21 - Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended

pub fn enidchg_wkup(&mut self) -> ENIDCHG_WKUP_W

Bit 22 - Enables the feature to wakeup USB if ID is toggled when USB is suspended.

pub fn envbuschg_wkup(&mut self) -> ENVBUSCHG_WKUP_W

Bit 23 - Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.

pub fn fsdll_rst_en(&mut self) -> FSDLL_RST_EN_W

Bit 24 - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.

pub fn host_force_ls_se0(&mut self) -> HOST_FORCE_LS_SE0_W

Bit 28 - Forces the next FS packet that is transmitted to have a EOP with LS timing

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - Gate UTMI Clocks

pub fn sftrst(&mut self) -> SFTRST_W

Bit 31 - Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers

impl W<u32, Reg<u32, _STATUS>>

pub fn otgid_status(&mut self) -> OTGID_STATUS_W

Bit 8 - Indicates the results of ID pin on MiniAB plug

impl W<u32, Reg<u32, _DEBUG>>

pub fn otgidpiolock(&mut self) -> OTGIDPIOLOCK_W

Bit 0 - Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value

pub fn debug_interface_hold(&mut self) -> DEBUG_INTERFACE_HOLD_W

Bit 1 - Use holding registers to assist in timing for external UTMI interface.

pub fn hstpulldown(&mut self) -> HSTPULLDOWN_W

Bits 2:3 - Set bit 3 to 1 to pull down 15-KOhm on USB_DP line

pub fn enhstpulldown(&mut self) -> ENHSTPULLDOWN_W

Bits 4:5 - Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown

pub fn tx2rxcount(&mut self) -> TX2RXCOUNT_W

Bits 8:11 - Delay in between the end of transmit to the beginning of receive

pub fn entx2rxcount(&mut self) -> ENTX2RXCOUNT_W

Bit 12 - Set this bit to allow a countdown to transition in between TX and RX.

pub fn squelchresetcount(&mut self) -> SQUELCHRESETCOUNT_W

Bits 16:20 - Delay in between the detection of squelch to the reset of high-speed RX.

pub fn ensquelchreset(&mut self) -> ENSQUELCHRESET_W

Bit 24 - Set bit to allow squelch to reset high-speed receive.

pub fn squelchresetlength(&mut self) -> SQUELCHRESETLENGTH_W

Bits 25:28 - Duration of RESET in terms of the number of 480-MHz cycles.

pub fn host_resume_debug(&mut self) -> HOST_RESUME_DEBUG_W

Bit 29 - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - Gate Test Clocks

impl W<u32, Reg<u32, _DEBUG_SET>>

pub fn otgidpiolock(&mut self) -> OTGIDPIOLOCK_W

Bit 0 - Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value

pub fn debug_interface_hold(&mut self) -> DEBUG_INTERFACE_HOLD_W

Bit 1 - Use holding registers to assist in timing for external UTMI interface.

pub fn hstpulldown(&mut self) -> HSTPULLDOWN_W

Bits 2:3 - Set bit 3 to 1 to pull down 15-KOhm on USB_DP line

pub fn enhstpulldown(&mut self) -> ENHSTPULLDOWN_W

Bits 4:5 - Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown

pub fn tx2rxcount(&mut self) -> TX2RXCOUNT_W

Bits 8:11 - Delay in between the end of transmit to the beginning of receive

pub fn entx2rxcount(&mut self) -> ENTX2RXCOUNT_W

Bit 12 - Set this bit to allow a countdown to transition in between TX and RX.

pub fn squelchresetcount(&mut self) -> SQUELCHRESETCOUNT_W

Bits 16:20 - Delay in between the detection of squelch to the reset of high-speed RX.

pub fn ensquelchreset(&mut self) -> ENSQUELCHRESET_W

Bit 24 - Set bit to allow squelch to reset high-speed receive.

pub fn squelchresetlength(&mut self) -> SQUELCHRESETLENGTH_W

Bits 25:28 - Duration of RESET in terms of the number of 480-MHz cycles.

pub fn host_resume_debug(&mut self) -> HOST_RESUME_DEBUG_W

Bit 29 - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - Gate Test Clocks

impl W<u32, Reg<u32, _DEBUG_CLR>>

pub fn otgidpiolock(&mut self) -> OTGIDPIOLOCK_W

Bit 0 - Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value

pub fn debug_interface_hold(&mut self) -> DEBUG_INTERFACE_HOLD_W

Bit 1 - Use holding registers to assist in timing for external UTMI interface.

pub fn hstpulldown(&mut self) -> HSTPULLDOWN_W

Bits 2:3 - Set bit 3 to 1 to pull down 15-KOhm on USB_DP line

pub fn enhstpulldown(&mut self) -> ENHSTPULLDOWN_W

Bits 4:5 - Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown

pub fn tx2rxcount(&mut self) -> TX2RXCOUNT_W

Bits 8:11 - Delay in between the end of transmit to the beginning of receive

pub fn entx2rxcount(&mut self) -> ENTX2RXCOUNT_W

Bit 12 - Set this bit to allow a countdown to transition in between TX and RX.

pub fn squelchresetcount(&mut self) -> SQUELCHRESETCOUNT_W

Bits 16:20 - Delay in between the detection of squelch to the reset of high-speed RX.

pub fn ensquelchreset(&mut self) -> ENSQUELCHRESET_W

Bit 24 - Set bit to allow squelch to reset high-speed receive.

pub fn squelchresetlength(&mut self) -> SQUELCHRESETLENGTH_W

Bits 25:28 - Duration of RESET in terms of the number of 480-MHz cycles.

pub fn host_resume_debug(&mut self) -> HOST_RESUME_DEBUG_W

Bit 29 - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - Gate Test Clocks

impl W<u32, Reg<u32, _DEBUG_TOG>>

pub fn otgidpiolock(&mut self) -> OTGIDPIOLOCK_W

Bit 0 - Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value

pub fn debug_interface_hold(&mut self) -> DEBUG_INTERFACE_HOLD_W

Bit 1 - Use holding registers to assist in timing for external UTMI interface.

pub fn hstpulldown(&mut self) -> HSTPULLDOWN_W

Bits 2:3 - Set bit 3 to 1 to pull down 15-KOhm on USB_DP line

pub fn enhstpulldown(&mut self) -> ENHSTPULLDOWN_W

Bits 4:5 - Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown

pub fn tx2rxcount(&mut self) -> TX2RXCOUNT_W

Bits 8:11 - Delay in between the end of transmit to the beginning of receive

pub fn entx2rxcount(&mut self) -> ENTX2RXCOUNT_W

Bit 12 - Set this bit to allow a countdown to transition in between TX and RX.

pub fn squelchresetcount(&mut self) -> SQUELCHRESETCOUNT_W

Bits 16:20 - Delay in between the detection of squelch to the reset of high-speed RX.

pub fn ensquelchreset(&mut self) -> ENSQUELCHRESET_W

Bit 24 - Set bit to allow squelch to reset high-speed receive.

pub fn squelchresetlength(&mut self) -> SQUELCHRESETLENGTH_W

Bits 25:28 - Duration of RESET in terms of the number of 480-MHz cycles.

pub fn host_resume_debug(&mut self) -> HOST_RESUME_DEBUG_W

Bit 29 - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - Gate Test Clocks

impl W<u32, Reg<u32, _DEBUG1>>

pub fn rsvd0(&mut self) -> RSVD0_W

Bits 0:12 - Reserved. Note: This bit should remain clear.

pub fn entailadjvd(&mut self) -> ENTAILADJVD_W

Bits 13:14 - Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%

impl W<u32, Reg<u32, _DEBUG1_SET>>

pub fn rsvd0(&mut self) -> RSVD0_W

Bits 0:12 - Reserved. Note: This bit should remain clear.

pub fn entailadjvd(&mut self) -> ENTAILADJVD_W

Bits 13:14 - Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%

impl W<u32, Reg<u32, _DEBUG1_CLR>>

pub fn rsvd0(&mut self) -> RSVD0_W

Bits 0:12 - Reserved. Note: This bit should remain clear.

pub fn entailadjvd(&mut self) -> ENTAILADJVD_W

Bits 13:14 - Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%

impl W<u32, Reg<u32, _DEBUG1_TOG>>

pub fn rsvd0(&mut self) -> RSVD0_W

Bits 0:12 - Reserved. Note: This bit should remain clear.

pub fn entailadjvd(&mut self) -> ENTAILADJVD_W

Bits 13:14 - Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%