Struct imxrt1062_usb1::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _GPTIMER0LD>>

pub fn gptld(&mut self) -> GPTLD_W

Bits 0:23 - General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'

impl W<u32, Reg<u32, _GPTIMER0CTRL>>

pub fn gptcnt(&mut self) -> GPTCNT_W

Bits 0:23 - General Purpose Timer Counter. This field is the count value of the countdown timer.

pub fn gptmode(&mut self) -> GPTMODE_W

Bit 24 - General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again

pub fn gptrst(&mut self) -> GPTRST_W

Bit 30 - General Purpose Timer Reset

pub fn gptrun(&mut self) -> GPTRUN_W

Bit 31 - General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit.

impl W<u32, Reg<u32, _GPTIMER1LD>>

pub fn gptld(&mut self) -> GPTLD_W

Bits 0:23 - General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'

impl W<u32, Reg<u32, _GPTIMER1CTRL>>

pub fn gptcnt(&mut self) -> GPTCNT_W

Bits 0:23 - General Purpose Timer Counter. This field is the count value of the countdown timer.

pub fn gptmode(&mut self) -> GPTMODE_W

Bit 24 - General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software

pub fn gptrst(&mut self) -> GPTRST_W

Bit 30 - General Purpose Timer Reset

pub fn gptrun(&mut self) -> GPTRUN_W

Bit 31 - General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit.

impl W<u32, Reg<u32, _SBUSCFG>>

pub fn ahbbrst(&mut self) -> AHBBRST_W

Bits 0:2 - AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority)

impl W<u32, Reg<u32, _USBCMD>>

pub fn rs(&mut self) -> RS_W

Bit 0 - Run/Stop (RS) - Read/Write

pub fn rst(&mut self) -> RST_W

Bit 1 - Controller Reset (RESET) - Read/Write

pub fn fs_1(&mut self) -> FS_1_W

Bits 2:3 - See description at bit 15

pub fn pse(&mut self) -> PSE_W

Bit 4 - Periodic Schedule Enable- Read/Write

pub fn ase(&mut self) -> ASE_W

Bit 5 - Asynchronous Schedule Enable - Read/Write

pub fn iaa(&mut self) -> IAA_W

Bit 6 - Interrupt on Async Advance Doorbell - Read/Write

pub fn asp(&mut self) -> ASP_W

Bits 8:9 - Asynchronous Schedule Park Mode Count - Read/Write

pub fn aspe(&mut self) -> ASPE_W

Bit 11 - Asynchronous Schedule Park Mode Enable - Read/Write

pub fn atdtw(&mut self) -> ATDTW_W

Bit 12 - Add dTD TripWire - Read/Write

pub fn sutw(&mut self) -> SUTW_W

Bit 13 - Setup TripWire - Read/Write

pub fn fs_2(&mut self) -> FS_2_W

Bit 15 - See also bits 3-2 Frame List Size - (Read/Write or Read Only)

pub fn itc(&mut self) -> ITC_W

Bits 16:23 - Interrupt Threshold Control -Read/Write

impl W<u32, Reg<u32, _USBSTS>>

pub fn ui(&mut self) -> UI_W

Bit 0 - USB Interrupt (USBINT) - R/WC

pub fn uei(&mut self) -> UEI_W

Bit 1 - USB Error Interrupt (USBERRINT) - R/WC

pub fn pci(&mut self) -> PCI_W

Bit 2 - Port Change Detect - R/WC

pub fn fri(&mut self) -> FRI_W

Bit 3 - Frame List Rollover - R/WC

pub fn sei(&mut self) -> SEI_W

Bit 4 - System Error- R/WC

pub fn aai(&mut self) -> AAI_W

Bit 5 - Interrupt on Async Advance - R/WC

pub fn uri(&mut self) -> URI_W

Bit 6 - USB Reset Received - R/WC

pub fn sri(&mut self) -> SRI_W

Bit 7 - SOF Received - R/WC

pub fn sli(&mut self) -> SLI_W

Bit 8 - DCSuspend - R/WC

pub fn ulpii(&mut self) -> ULPII_W

Bit 10 - ULPI Interrupt - R/WC

pub fn hch(&mut self) -> HCH_W

Bit 12 - HCHaIted - Read Only

pub fn rcl(&mut self) -> RCL_W

Bit 13 - Reclamation - Read Only

pub fn ps(&mut self) -> PS_W

Bit 14 - Periodic Schedule Status - Read Only

pub fn as_(&mut self) -> AS_W

Bit 15 - Asynchronous Schedule Status - Read Only

pub fn ti0(&mut self) -> TI0_W

Bit 24 - General Purpose Timer Interrupt 0(GPTINT0)--R/WC

pub fn ti1(&mut self) -> TI1_W

Bit 25 - General Purpose Timer Interrupt 1(GPTINT1)--R/WC

impl W<u32, Reg<u32, _USBINTR>>

pub fn ue(&mut self) -> UE_W

Bit 0 - USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn uee(&mut self) -> UEE_W

Bit 1 - USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn pce(&mut self) -> PCE_W

Bit 2 - Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn fre(&mut self) -> FRE_W

Bit 3 - Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn see(&mut self) -> SEE_W

Bit 4 - System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn aae(&mut self) -> AAE_W

Bit 5 - Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn ure(&mut self) -> URE_W

Bit 6 - USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn sre(&mut self) -> SRE_W

Bit 7 - SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn sle(&mut self) -> SLE_W

Bit 8 - Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt

pub fn ulpie(&mut self) -> ULPIE_W

Bit 10 - ULPI Interrupt Enable When this bit is one and the UPLII bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn nake(&mut self) -> NAKE_W

Bit 16 - NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn uaie(&mut self) -> UAIE_W

Bit 18 - USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold

pub fn upie(&mut self) -> UPIE_W

Bit 19 - USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold

pub fn tie0(&mut self) -> TIE0_W

Bit 24 - General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn tie1(&mut self) -> TIE1_W

Bit 25 - General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt

impl W<u32, Reg<u32, _FRINDEX>>

pub fn frindex(&mut self) -> FRINDEX_W

Bits 0:13 - Frame Index

impl W<u32, Reg<u32, _DEVICEADDR>>

pub fn usbadra(&mut self) -> USBADRA_W

Bit 24 - Device Address Advance

pub fn usbadr(&mut self) -> USBADR_W

Bits 25:31 - Device Address. These bits correspond to the USB device address

impl W<u32, Reg<u32, _PERIODICLISTBASE>>

pub fn baseadr(&mut self) -> BASEADR_W

Bits 12:31 - Base Address (Low)

impl W<u32, Reg<u32, _ASYNCLISTADDR>>

pub fn asybase(&mut self) -> ASYBASE_W

Bits 5:31 - Link Pointer Low (LPL)

impl W<u32, Reg<u32, _ENDPTLISTADDR>>

pub fn epbase(&mut self) -> EPBASE_W

Bits 11:31 - Endpoint List Pointer(Low)

impl W<u32, Reg<u32, _BURSTSIZE>>

pub fn rxpburst(&mut self) -> RXPBURST_W

Bits 0:7 - Programmable RX Burst Size

pub fn txpburst(&mut self) -> TXPBURST_W

Bits 8:16 - Programmable TX Burst Size

impl W<u32, Reg<u32, _TXFILLTUNING>>

pub fn txschoh(&mut self) -> TXSCHOH_W

Bits 0:7 - Scheduler Overhead

pub fn txschhealth(&mut self) -> TXSCHHEALTH_W

Bits 8:12 - Scheduler Health Counter

pub fn txfifothres(&mut self) -> TXFIFOTHRES_W

Bits 16:21 - FIFO Burst Threshold

impl W<u32, Reg<u32, _ENDPTNAK>>

pub fn eprn(&mut self) -> EPRN_W

Bits 0:7 - RX Endpoint NAK - R/WC

pub fn eptn(&mut self) -> EPTN_W

Bits 16:23 - TX Endpoint NAK - R/WC

impl W<u32, Reg<u32, _ENDPTNAKEN>>

pub fn eprne(&mut self) -> EPRNE_W

Bits 0:7 - RX Endpoint NAK Enable - R/W

pub fn eptne(&mut self) -> EPTNE_W

Bits 16:23 - TX Endpoint NAK Enable - R/W

impl W<u32, Reg<u32, _PORTSC1>>

pub fn csc(&mut self) -> CSC_W

Bit 1 - Connect Status Change-R/WC

pub fn pe(&mut self) -> PE_W

Bit 2 - Port Enabled/Disabled-Read/Write

pub fn pec(&mut self) -> PEC_W

Bit 3 - Port Enable/Disable Change-R/WC

pub fn occ(&mut self) -> OCC_W

Bit 5 - Over-current Change-R/WC

pub fn fpr(&mut self) -> FPR_W

Bit 6 - Force Port Resume -Read/Write

pub fn susp(&mut self) -> SUSP_W

Bit 7 - Suspend - Read/Write or Read Only

pub fn pr(&mut self) -> PR_W

Bit 8 - Port Reset - Read/Write or Read Only

pub fn ls(&mut self) -> LS_W

Bits 10:11 - Line Status-Read Only

pub fn pp(&mut self) -> PP_W

Bit 12 - Port Power (PP)-Read/Write or Read Only

pub fn po(&mut self) -> PO_W

Bit 13 - Port Owner-Read/Write

pub fn pic(&mut self) -> PIC_W

Bits 14:15 - Port Indicator Control - Read/Write

pub fn ptc(&mut self) -> PTC_W

Bits 16:19 - Port Test Control - Read/Write

pub fn wkcn(&mut self) -> WKCN_W

Bit 20 - Wake on Connect Enable (WKCNNT_E) - Read/Write

pub fn wkdc(&mut self) -> WKDC_W

Bit 21 - Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write

pub fn wkoc(&mut self) -> WKOC_W

Bit 22 - Wake on Over-current Enable (WKOC_E) - Read/Write

pub fn phcd(&mut self) -> PHCD_W

Bit 23 - PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write

pub fn pfsc(&mut self) -> PFSC_W

Bit 24 - Port Force Full Speed Connect - Read/Write

pub fn pts_2(&mut self) -> PTS_2_W

Bit 25 - See description at bits 31-30

pub fn pspd(&mut self) -> PSPD_W

Bits 26:27 - Port Speed - Read Only. This register field indicates the speed at which the port is operating.

pub fn ptw(&mut self) -> PTW_W

Bit 28 - Parallel Transceiver Width This bit has no effect if serial interface engine is used

pub fn sts(&mut self) -> STS_W

Bit 29 - Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals

pub fn pts_1(&mut self) -> PTS_1_W

Bits 30:31 - All USB port interface modes are listed in this field description, but not all are supported

impl W<u32, Reg<u32, _OTGSC>>

pub fn vd(&mut self) -> VD_W

Bit 0 - VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor.

pub fn vc(&mut self) -> VC_W

Bit 1 - VBUS Charge - Read/Write

pub fn ot(&mut self) -> OT_W

Bit 3 - OTG Termination - Read/Write

pub fn dp(&mut self) -> DP_W

Bit 4 - Data Pulsing - Read/Write

pub fn idpu(&mut self) -> IDPU_W

Bit 5 - ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]

pub fn idis(&mut self) -> IDIS_W

Bit 16 - USB ID Interrupt Status - Read/Write

pub fn avvis(&mut self) -> AVVIS_W

Bit 17 - A VBus Valid Interrupt Status - Read/Write to Clear

pub fn asvis(&mut self) -> ASVIS_W

Bit 18 - A Session Valid Interrupt Status - Read/Write to Clear

pub fn bsvis(&mut self) -> BSVIS_W

Bit 19 - B Session Valid Interrupt Status - Read/Write to Clear

pub fn bseis(&mut self) -> BSEIS_W

Bit 20 - B Session End Interrupt Status - Read/Write to Clear

pub fn status_1ms(&mut self) -> STATUS_1MS_W

Bit 21 - 1 millisecond timer Interrupt Status - Read/Write to Clear

pub fn dpis(&mut self) -> DPIS_W

Bit 22 - Data Pulse Interrupt Status - Read/Write to Clear

pub fn idie(&mut self) -> IDIE_W

Bit 24 - USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt.

pub fn avvie(&mut self) -> AVVIE_W

Bit 25 - A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt.

pub fn asvie(&mut self) -> ASVIE_W

Bit 26 - A Session Valid Interrupt Enable - Read/Write

pub fn bsvie(&mut self) -> BSVIE_W

Bit 27 - B Session Valid Interrupt Enable - Read/Write

pub fn bseie(&mut self) -> BSEIE_W

Bit 28 - B Session End Interrupt Enable - Read/Write. Setting this bit enables the B session end interrupt.

pub fn en_1ms(&mut self) -> EN_1MS_W

Bit 29 - 1 millisecond timer Interrupt Enable - Read/Write

pub fn dpie(&mut self) -> DPIE_W

Bit 30 - Data Pulse Interrupt Enable

impl W<u32, Reg<u32, _USBMODE>>

pub fn cm(&mut self) -> CM_W

Bits 0:1 - Controller Mode - R/WO

pub fn es(&mut self) -> ES_W

Bit 2 - Endian Select - Read/Write

pub fn slom(&mut self) -> SLOM_W

Bit 3 - Setup Lockout Mode

pub fn sdis(&mut self) -> SDIS_W

Bit 4 - Stream Disable Mode

impl W<u32, Reg<u32, _ENDPTSETUPSTAT>>

pub fn endptsetupstat(&mut self) -> ENDPTSETUPSTAT_W

Bits 0:15 - Setup Endpoint Status

impl W<u32, Reg<u32, _ENDPTPRIME>>

pub fn perb(&mut self) -> PERB_W

Bits 0:7 - Prime Endpoint Receive Buffer - R/WS

pub fn petb(&mut self) -> PETB_W

Bits 16:23 - Prime Endpoint Transmit Buffer - R/WS

impl W<u32, Reg<u32, _ENDPTFLUSH>>

pub fn ferb(&mut self) -> FERB_W

Bits 0:7 - Flush Endpoint Receive Buffer - R/WS

pub fn fetb(&mut self) -> FETB_W

Bits 16:23 - Flush Endpoint Transmit Buffer - R/WS

impl W<u32, Reg<u32, _ENDPTCOMPLETE>>

pub fn erce(&mut self) -> ERCE_W

Bits 0:7 - Endpoint Receive Complete Event - RW/C

pub fn etce(&mut self) -> ETCE_W

Bits 16:23 - Endpoint Transmit Complete Event - R/WC

impl W<u32, Reg<u32, _ENDPTCTRL0>>

pub fn rxs(&mut self) -> RXS_W

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxt(&mut self) -> RXT_W

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control Endpoint0 is fixed as a Control End Point.

pub fn rxe(&mut self) -> RXE_W

Bit 7 - RX Endpoint Enable 1 Enabled Endpoint0 is always enabled.

pub fn txs(&mut self) -> TXS_W

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK [Default] 1 End Point Stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host

pub fn txt(&mut self) -> TXT_W

Bits 18:19 - TX Endpoint Type - Read/Write 00 - Control Endpoint0 is fixed as a Control End Point.

pub fn txe(&mut self) -> TXE_W

Bit 23 - TX Endpoint Enable 1 Enabled Endpoint0 is always enabled.

impl W<u32, Reg<u32, _ENDPTCTRL1>>

pub fn rxs(&mut self) -> RXS_W

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxd(&mut self) -> RXD_W

Bit 1 - RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero

pub fn rxt(&mut self) -> RXT_W

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn rxi(&mut self) -> RXI_W

Bit 5 - RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero

pub fn rxr(&mut self) -> RXR_W

Bit 6 - RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device

pub fn rxe(&mut self) -> RXE_W

Bit 7 - RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

pub fn txs(&mut self) -> TXS_W

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared

pub fn txd(&mut self) -> TXD_W

Bit 17 - TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0

pub fn txt(&mut self) -> TXT_W

Bits 18:19 - TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn txi(&mut self) -> TXI_W

Bit 21 - TX Data Toggle Inhibit 0 PID Sequencing Enabled

pub fn txr(&mut self) -> TXR_W

Bit 22 - TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device

pub fn txe(&mut self) -> TXE_W

Bit 23 - TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

impl W<u32, Reg<u32, _ENDPTCTRL2>>

pub fn rxs(&mut self) -> RXS_W

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxd(&mut self) -> RXD_W

Bit 1 - RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero

pub fn rxt(&mut self) -> RXT_W

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn rxi(&mut self) -> RXI_W

Bit 5 - RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero

pub fn rxr(&mut self) -> RXR_W

Bit 6 - RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device

pub fn rxe(&mut self) -> RXE_W

Bit 7 - RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

pub fn txs(&mut self) -> TXS_W

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared

pub fn txd(&mut self) -> TXD_W

Bit 17 - TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0

pub fn txt(&mut self) -> TXT_W

Bits 18:19 - TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn txi(&mut self) -> TXI_W

Bit 21 - TX Data Toggle Inhibit 0 PID Sequencing Enabled

pub fn txr(&mut self) -> TXR_W

Bit 22 - TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device

pub fn txe(&mut self) -> TXE_W

Bit 23 - TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

impl W<u32, Reg<u32, _ENDPTCTRL3>>

pub fn rxs(&mut self) -> RXS_W

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxd(&mut self) -> RXD_W

Bit 1 - RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero

pub fn rxt(&mut self) -> RXT_W

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn rxi(&mut self) -> RXI_W

Bit 5 - RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero

pub fn rxr(&mut self) -> RXR_W

Bit 6 - RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device

pub fn rxe(&mut self) -> RXE_W

Bit 7 - RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

pub fn txs(&mut self) -> TXS_W

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared

pub fn txd(&mut self) -> TXD_W

Bit 17 - TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0

pub fn txt(&mut self) -> TXT_W

Bits 18:19 - TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn txi(&mut self) -> TXI_W

Bit 21 - TX Data Toggle Inhibit 0 PID Sequencing Enabled

pub fn txr(&mut self) -> TXR_W

Bit 22 - TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device

pub fn txe(&mut self) -> TXE_W

Bit 23 - TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

impl W<u32, Reg<u32, _ENDPTCTRL4>>

pub fn rxs(&mut self) -> RXS_W

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxd(&mut self) -> RXD_W

Bit 1 - RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero

pub fn rxt(&mut self) -> RXT_W

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn rxi(&mut self) -> RXI_W

Bit 5 - RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero

pub fn rxr(&mut self) -> RXR_W

Bit 6 - RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device

pub fn rxe(&mut self) -> RXE_W

Bit 7 - RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

pub fn txs(&mut self) -> TXS_W

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared

pub fn txd(&mut self) -> TXD_W

Bit 17 - TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0

pub fn txt(&mut self) -> TXT_W

Bits 18:19 - TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn txi(&mut self) -> TXI_W

Bit 21 - TX Data Toggle Inhibit 0 PID Sequencing Enabled

pub fn txr(&mut self) -> TXR_W

Bit 22 - TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device

pub fn txe(&mut self) -> TXE_W

Bit 23 - TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

impl W<u32, Reg<u32, _ENDPTCTRL5>>

pub fn rxs(&mut self) -> RXS_W

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxd(&mut self) -> RXD_W

Bit 1 - RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero

pub fn rxt(&mut self) -> RXT_W

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn rxi(&mut self) -> RXI_W

Bit 5 - RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero

pub fn rxr(&mut self) -> RXR_W

Bit 6 - RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device

pub fn rxe(&mut self) -> RXE_W

Bit 7 - RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

pub fn txs(&mut self) -> TXS_W

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared

pub fn txd(&mut self) -> TXD_W

Bit 17 - TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0

pub fn txt(&mut self) -> TXT_W

Bits 18:19 - TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn txi(&mut self) -> TXI_W

Bit 21 - TX Data Toggle Inhibit 0 PID Sequencing Enabled

pub fn txr(&mut self) -> TXR_W

Bit 22 - TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device

pub fn txe(&mut self) -> TXE_W

Bit 23 - TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

impl W<u32, Reg<u32, _ENDPTCTRL6>>

pub fn rxs(&mut self) -> RXS_W

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxd(&mut self) -> RXD_W

Bit 1 - RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero

pub fn rxt(&mut self) -> RXT_W

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn rxi(&mut self) -> RXI_W

Bit 5 - RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero

pub fn rxr(&mut self) -> RXR_W

Bit 6 - RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device

pub fn rxe(&mut self) -> RXE_W

Bit 7 - RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

pub fn txs(&mut self) -> TXS_W

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared

pub fn txd(&mut self) -> TXD_W

Bit 17 - TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0

pub fn txt(&mut self) -> TXT_W

Bits 18:19 - TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn txi(&mut self) -> TXI_W

Bit 21 - TX Data Toggle Inhibit 0 PID Sequencing Enabled

pub fn txr(&mut self) -> TXR_W

Bit 22 - TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device

pub fn txe(&mut self) -> TXE_W

Bit 23 - TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

impl W<u32, Reg<u32, _ENDPTCTRL7>>

pub fn rxs(&mut self) -> RXS_W

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxd(&mut self) -> RXD_W

Bit 1 - RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero

pub fn rxt(&mut self) -> RXT_W

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn rxi(&mut self) -> RXI_W

Bit 5 - RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero

pub fn rxr(&mut self) -> RXR_W

Bit 6 - RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device

pub fn rxe(&mut self) -> RXE_W

Bit 7 - RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

pub fn txs(&mut self) -> TXS_W

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared

pub fn txd(&mut self) -> TXD_W

Bit 17 - TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0

pub fn txt(&mut self) -> TXT_W

Bits 18:19 - TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn txi(&mut self) -> TXI_W

Bit 21 - TX Data Toggle Inhibit 0 PID Sequencing Enabled

pub fn txr(&mut self) -> TXR_W

Bit 22 - TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device

pub fn txe(&mut self) -> TXE_W

Bit 23 - TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured