Module imxrt1062_system_control::ccr

Configuration and Control Register

Structs

BFHFNMIGN_W	Write proxy for field BFHFNMIGN
DC_W	Write proxy for field DC
DIV_0_TRP_W	Write proxy for field DIV_0_TRP
IC_W	Write proxy for field IC
NONBASETHRDENA_W	Write proxy for field NONBASETHRDENA
STKALIGN_W	Write proxy for field STKALIGN
UNALIGN_TRP_W	Write proxy for field UNALIGN_TRP
USERSETMPEND_W	Write proxy for field USERSETMPEND

Enums

BFHFNMIGN_A	Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.
DC_A	Enables L1 data cache.
DIV_0_TRP_A	Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
IC_A	Enables L1 instruction cache.
NONBASETHRDENA_A	Indicates how the processor enters Thread mode
STKALIGN_A	Indicates stack alignment on exception entry
UNALIGN_TRP_A	Enables unaligned access traps
USERSETMPEND_A	Enables unprivileged software access to the STIR

Type Definitions

BFHFNMIGN_R	Reader of field BFHFNMIGN
BP_R	Reader of field BP
DC_R	Reader of field DC
DIV_0_TRP_R	Reader of field DIV_0_TRP
IC_R	Reader of field IC
NONBASETHRDENA_R	Reader of field NONBASETHRDENA
R	Reader of register CCR
STKALIGN_R	Reader of field STKALIGN
UNALIGN_TRP_R	Reader of field UNALIGN_TRP
USERSETMPEND_R	Reader of field USERSETMPEND
W	Writer for register CCR