[−][src]Crate imxrt1062_system_control
Modules
actlr | Auxiliary Control Register, |
aircr | Application Interrupt and Reset Control Register |
bfar | BusFault Address Register |
ccr | Configuration and Control Register |
ccsidr | Cache Size ID Register |
cfsr | Configurable Fault Status Register |
clidr | Cache Level ID register |
cm7_itcmcr | Instruction Tightly-Coupled Memory Control Register |
cm7_dtcmcr | Data Tightly-Coupled Memory Control Register |
cm7_ahbpcr | AHBP Control Register |
cm7_cacr | L1 Cache Control Register |
cm7_ahbscr | AHB Slave Control Register |
cm7_abfsr | Auxiliary Bus Fault Status Register |
cpacr | Coprocessor Access Control Register |
cpuid | CPUID Base Register |
csselr | Cache Size Selection Register |
ctr | Cache Type register |
dccimvac | Data cache clean and invalidate by address to PoC |
dccisw | Data cache clean and invalidate by set/way |
dccmvac | Data cache clean by address to PoC |
dccmvau | Data cache by address to PoU |
dccsw | Data cache clean by set/way |
dcimvac | Data cache invalidate by address to Point of Coherency (PoC) |
dcisw | Data cache invalidate by set/way |
dfsr | Debug Fault Status Register |
hfsr | HardFault Status register |
iciallu | Instruction cache invalidate all to Point of Unification (PoU) |
icimvau | Instruction cache invalidate by address to PoU |
icsr | Interrupt Control and State Register |
id_afr0 | Auxiliary Feature Register |
id_dfr0 | Debug Feature Register |
id_isar0 | Instruction Set Attributes Register 0 |
id_isar1 | Instruction Set Attributes Register 1 |
id_isar2 | Instruction Set Attributes Register 2 |
id_isar3 | Instruction Set Attributes Register 3 |
id_isar4 | Instruction Set Attributes Register 4 |
id_mmfr0 | Memory Model Feature Register 0 |
id_mmfr1 | Memory Model Feature Register 1 |
id_mmfr2 | Memory Model Feature Register 2 |
id_mmfr3 | Memory Model Feature Register 3 |
id_pfr0 | Processor Feature Register 0 |
id_pfr1 | Processor Feature Register 1 |
mmfar | MemManage Fault Address Register |
scr | System Control Register |
shcsr | System Handler Control and State Register |
shpr1 | System Handler Priority Register 1 |
shpr2 | System Handler Priority Register 2 |
shpr3 | System Handler Priority Register 3 |
stir | Instruction cache invalidate all to Point of Unification (PoU) |
vtor | Vector Table Offset Register |
Structs
R | Register/field reader |
Reg | This structure provides volatile access to register |
RegisterBlock | Register block |
W | Register writer |
Enums
Variant | Used if enumerated values cover not the whole range |
Traits
Readable | This trait shows that register has |
ResetValue | Reset value of the register |
Writable | This trait shows that register has |
Type Definitions
ACTLR | Auxiliary Control Register, |
AIRCR | Application Interrupt and Reset Control Register |
BFAR | BusFault Address Register |
CCR | Configuration and Control Register |
CCSIDR | Cache Size ID Register |
CFSR | Configurable Fault Status Register |
CLIDR | Cache Level ID register |
CM7_ITCMCR | Instruction Tightly-Coupled Memory Control Register |
CM7_DTCMCR | Data Tightly-Coupled Memory Control Register |
CM7_AHBPCR | AHBP Control Register |
CM7_CACR | L1 Cache Control Register |
CM7_AHBSCR | AHB Slave Control Register |
CM7_ABFSR | Auxiliary Bus Fault Status Register |
CPACR | Coprocessor Access Control Register |
CPUID | CPUID Base Register |
CSSELR | Cache Size Selection Register |
CTR | Cache Type register |
DCCIMVAC | Data cache clean and invalidate by address to PoC |
DCCISW | Data cache clean and invalidate by set/way |
DCCMVAC | Data cache clean by address to PoC |
DCCMVAU | Data cache by address to PoU |
DCCSW | Data cache clean by set/way |
DCIMVAC | Data cache invalidate by address to Point of Coherency (PoC) |
DCISW | Data cache invalidate by set/way |
DFSR | Debug Fault Status Register |
HFSR | HardFault Status register |
ICIALLU | Instruction cache invalidate all to Point of Unification (PoU) |
ICIMVAU | Instruction cache invalidate by address to PoU |
ICSR | Interrupt Control and State Register |
ID_AFR0 | Auxiliary Feature Register |
ID_DFR0 | Debug Feature Register |
ID_ISAR0 | Instruction Set Attributes Register 0 |
ID_ISAR1 | Instruction Set Attributes Register 1 |
ID_ISAR2 | Instruction Set Attributes Register 2 |
ID_ISAR3 | Instruction Set Attributes Register 3 |
ID_ISAR4 | Instruction Set Attributes Register 4 |
ID_MMFR0 | Memory Model Feature Register 0 |
ID_MMFR1 | Memory Model Feature Register 1 |
ID_MMFR2 | Memory Model Feature Register 2 |
ID_MMFR3 | Memory Model Feature Register 3 |
ID_PFR0 | Processor Feature Register 0 |
ID_PFR1 | Processor Feature Register 1 |
MMFAR | MemManage Fault Address Register |
SCR | System Control Register |
SHCSR | System Handler Control and State Register |
SHPR1 | System Handler Priority Register 1 |
SHPR2 | System Handler Priority Register 2 |
SHPR3 | System Handler Priority Register 3 |
STIR | Instruction cache invalidate all to Point of Unification (PoU) |
VTOR | Vector Table Offset Register |