[−][src]Struct imxrt1062_spdif::R
Register/field reader
Result of the read method of a register.
Also it can be used in the modify method
Methods
impl<U, T> R<U, T> where
U: Copy, [src]
U: Copy,
impl<FI> R<bool, FI>[src]
pub fn bit(&self) -> bool[src]
Value of the field as raw bits
pub fn bit_is_clear(&self) -> bool[src]
Returns true if the bit is clear (0)
pub fn bit_is_set(&self) -> bool[src]
Returns true if the bit is set (1)
impl R<u8, USRC_SEL_A>[src]
pub fn variant(&self) -> Variant<u8, USRC_SEL_A>[src]
Get enumerated values variant
pub fn is_usrc_sel_0(&self) -> bool[src]
Checks if the value of the field is USRC_SEL_0
pub fn is_usrc_sel_1(&self) -> bool[src]
Checks if the value of the field is USRC_SEL_1
pub fn is_usrc_sel_3(&self) -> bool[src]
Checks if the value of the field is USRC_SEL_3
impl R<u8, TXSEL_A>[src]
pub fn variant(&self) -> Variant<u8, TXSEL_A>[src]
Get enumerated values variant
pub fn is_tx_sel_0(&self) -> bool[src]
Checks if the value of the field is TXSEL_0
pub fn is_tx_sel_1(&self) -> bool[src]
Checks if the value of the field is TXSEL_1
pub fn is_tx_sel_5(&self) -> bool[src]
Checks if the value of the field is TXSEL_5
impl R<bool, VALCTRL_A>[src]
pub fn variant(&self) -> VALCTRL_A[src]
Get enumerated values variant
pub fn is_val_ctrl_0(&self) -> bool[src]
Checks if the value of the field is VALCTRL_0
pub fn is_val_ctrl_1(&self) -> bool[src]
Checks if the value of the field is VALCTRL_1
impl R<u8, TXFIFO_CTRL_A>[src]
pub fn variant(&self) -> Variant<u8, TXFIFO_CTRL_A>[src]
Get enumerated values variant
pub fn is_tx_fifo_ctrl_0(&self) -> bool[src]
Checks if the value of the field is TXFIFO_CTRL_0
pub fn is_tx_fifo_ctrl_1(&self) -> bool[src]
Checks if the value of the field is TXFIFO_CTRL_1
pub fn is_tx_fifo_ctrl_2(&self) -> bool[src]
Checks if the value of the field is TXFIFO_CTRL_2
impl R<u8, TXFIFOEMPTY_SEL_A>[src]
pub fn variant(&self) -> TXFIFOEMPTY_SEL_A[src]
Get enumerated values variant
pub fn is_tx_fifoempty_sel_0(&self) -> bool[src]
Checks if the value of the field is TXFIFOEMPTY_SEL_0
pub fn is_tx_fifoempty_sel_1(&self) -> bool[src]
Checks if the value of the field is TXFIFOEMPTY_SEL_1
pub fn is_tx_fifoempty_sel_2(&self) -> bool[src]
Checks if the value of the field is TXFIFOEMPTY_SEL_2
pub fn is_tx_fifoempty_sel_3(&self) -> bool[src]
Checks if the value of the field is TXFIFOEMPTY_SEL_3
impl R<bool, TXAUTOSYNC_A>[src]
pub fn variant(&self) -> TXAUTOSYNC_A[src]
Get enumerated values variant
pub fn is_tx_auto_sync_0(&self) -> bool[src]
Checks if the value of the field is TXAUTOSYNC_0
pub fn is_tx_auto_sync_1(&self) -> bool[src]
Checks if the value of the field is TXAUTOSYNC_1
impl R<bool, RXAUTOSYNC_A>[src]
pub fn variant(&self) -> RXAUTOSYNC_A[src]
Get enumerated values variant
pub fn is_rx_auto_sync_0(&self) -> bool[src]
Checks if the value of the field is RXAUTOSYNC_0
pub fn is_rx_auto_sync_1(&self) -> bool[src]
Checks if the value of the field is RXAUTOSYNC_1
impl R<u8, RXFIFOFULL_SEL_A>[src]
pub fn variant(&self) -> RXFIFOFULL_SEL_A[src]
Get enumerated values variant
pub fn is_rx_fifofull_sel_0(&self) -> bool[src]
Checks if the value of the field is RXFIFOFULL_SEL_0
pub fn is_rx_fifofull_sel_1(&self) -> bool[src]
Checks if the value of the field is RXFIFOFULL_SEL_1
pub fn is_rx_fifofull_sel_2(&self) -> bool[src]
Checks if the value of the field is RXFIFOFULL_SEL_2
pub fn is_rx_fifofull_sel_3(&self) -> bool[src]
Checks if the value of the field is RXFIFOFULL_SEL_3
impl R<bool, RXFIFO_RST_A>[src]
pub fn variant(&self) -> RXFIFO_RST_A[src]
Get enumerated values variant
pub fn is_rx_fifo_rst_0(&self) -> bool[src]
Checks if the value of the field is RXFIFO_RST_0
pub fn is_rx_fifo_rst_1(&self) -> bool[src]
Checks if the value of the field is RXFIFO_RST_1
impl R<bool, RXFIFO_OFF_ON_A>[src]
pub fn variant(&self) -> RXFIFO_OFF_ON_A[src]
Get enumerated values variant
pub fn is_rx_fifo_off_on_0(&self) -> bool[src]
Checks if the value of the field is RXFIFO_OFF_ON_0
pub fn is_rx_fifo_off_on_1(&self) -> bool[src]
Checks if the value of the field is RXFIFO_OFF_ON_1
impl R<bool, RXFIFO_CTRL_A>[src]
pub fn variant(&self) -> RXFIFO_CTRL_A[src]
Get enumerated values variant
pub fn is_rx_fifo_ctrl_0(&self) -> bool[src]
Checks if the value of the field is RXFIFO_CTRL_0
pub fn is_rx_fifo_ctrl_1(&self) -> bool[src]
Checks if the value of the field is RXFIFO_CTRL_1
impl R<u32, Reg<u32, _SCR>>[src]
pub fn usrc_sel(&self) -> USRC_SEL_R[src]
Bits 0:1 - no description available
pub fn tx_sel(&self) -> TXSEL_R[src]
Bits 2:4 - no description available
pub fn val_ctrl(&self) -> VALCTRL_R[src]
Bit 5 - no description available
pub fn dma_tx_en(&self) -> DMA_TX_EN_R[src]
Bit 8 - DMA Transmit Request Enable (Tx FIFO empty)
pub fn dma_rx_en(&self) -> DMA_RX_EN_R[src]
Bit 9 - DMA Receive Request Enable (RX FIFO full)
pub fn tx_fifo_ctrl(&self) -> TXFIFO_CTRL_R[src]
Bits 10:11 - no description available
pub fn soft_reset(&self) -> SOFT_RESET_R[src]
Bit 12 - When write 1 to this bit, it will cause SPDIF software reset
pub fn low_power(&self) -> LOW_POWER_R[src]
Bit 13 - When write 1 to this bit, it will cause SPDIF enter low-power mode
pub fn tx_fifoempty_sel(&self) -> TXFIFOEMPTY_SEL_R[src]
Bits 15:16 - no description available
pub fn tx_auto_sync(&self) -> TXAUTOSYNC_R[src]
Bit 17 - no description available
pub fn rx_auto_sync(&self) -> RXAUTOSYNC_R[src]
Bit 18 - no description available
pub fn rx_fifofull_sel(&self) -> RXFIFOFULL_SEL_R[src]
Bits 19:20 - no description available
pub fn rx_fifo_rst(&self) -> RXFIFO_RST_R[src]
Bit 21 - no description available
pub fn rx_fifo_off_on(&self) -> RXFIFO_OFF_ON_R[src]
Bit 22 - no description available
pub fn rx_fifo_ctrl(&self) -> RXFIFO_CTRL_R[src]
Bit 23 - no description available
impl R<bool, USYNCMODE_A>[src]
pub fn variant(&self) -> USYNCMODE_A[src]
Get enumerated values variant
pub fn is_usync_mode_0(&self) -> bool[src]
Checks if the value of the field is USYNCMODE_0
pub fn is_usync_mode_1(&self) -> bool[src]
Checks if the value of the field is USYNCMODE_1
impl R<u32, Reg<u32, _SRCD>>[src]
pub fn usync_mode(&self) -> USYNCMODE_R[src]
Bit 1 - no description available
impl R<u8, GAINSEL_A>[src]
pub fn variant(&self) -> Variant<u8, GAINSEL_A>[src]
Get enumerated values variant
pub fn is_gain_sel_0(&self) -> bool[src]
Checks if the value of the field is GAINSEL_0
pub fn is_gain_sel_1(&self) -> bool[src]
Checks if the value of the field is GAINSEL_1
pub fn is_gain_sel_2(&self) -> bool[src]
Checks if the value of the field is GAINSEL_2
pub fn is_gain_sel_3(&self) -> bool[src]
Checks if the value of the field is GAINSEL_3
pub fn is_gain_sel_4(&self) -> bool[src]
Checks if the value of the field is GAINSEL_4
pub fn is_gain_sel_5(&self) -> bool[src]
Checks if the value of the field is GAINSEL_5
pub fn is_gain_sel_6(&self) -> bool[src]
Checks if the value of the field is GAINSEL_6
impl R<u8, CLKSRC_SEL_A>[src]
pub fn variant(&self) -> Variant<u8, CLKSRC_SEL_A>[src]
Get enumerated values variant
pub fn is_clk_src_sel_0(&self) -> bool[src]
Checks if the value of the field is CLKSRC_SEL_0
pub fn is_clk_src_sel_1(&self) -> bool[src]
Checks if the value of the field is CLKSRC_SEL_1
pub fn is_clk_src_sel_3(&self) -> bool[src]
Checks if the value of the field is CLKSRC_SEL_3
pub fn is_clk_src_sel_5(&self) -> bool[src]
Checks if the value of the field is CLKSRC_SEL_5
pub fn is_clk_src_sel_6(&self) -> bool[src]
Checks if the value of the field is CLKSRC_SEL_6
pub fn is_clk_src_sel_8(&self) -> bool[src]
Checks if the value of the field is CLKSRC_SEL_8
impl R<u32, Reg<u32, _SRPC>>[src]
pub fn gain_sel(&self) -> GAINSEL_R[src]
Bits 3:5 - Gain selection:
pub fn lock(&self) -> LOCK_R[src]
Bit 6 - LOCK bit to show that the internal DPLL is locked, read only
pub fn clk_src_sel(&self) -> CLKSRC_SEL_R[src]
Bits 7:10 - Clock source selection, all other settings not shown are reserved:
impl R<u32, Reg<u32, _SIE>>[src]
pub fn rx_fifoful(&self) -> RXFIFOFUL_R[src]
Bit 0 - SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO.
pub fn tx_em(&self) -> TXEM_R[src]
Bit 1 - SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO.
pub fn lock_loss(&self) -> LOCKLOSS_R[src]
Bit 2 - SPDIF receiver loss of lock
pub fn rx_fiforesyn(&self) -> RXFIFORESYN_R[src]
Bit 3 - Rx FIFO resync
pub fn rx_fifoun_ov(&self) -> RXFIFOUNOV_R[src]
Bit 4 - Rx FIFO underrun/overrun
pub fn uqerr(&self) -> UQERR_R[src]
Bit 5 - U/Q Channel framing error
pub fn uqsync(&self) -> UQSYNC_R[src]
Bit 6 - U/Q Channel sync found
pub fn qrx_ov(&self) -> QRXOV_R[src]
Bit 7 - Q Channel receive register overrun
pub fn qrx_ful(&self) -> QRXFUL_R[src]
Bit 8 - Q Channel receive register full, can't be cleared with reg
pub fn urx_ov(&self) -> URXOV_R[src]
Bit 9 - U Channel receive register overrun
pub fn urx_ful(&self) -> URXFUL_R[src]
Bit 10 - U Channel receive register full, can't be cleared with reg
pub fn bit_err(&self) -> BITERR_R[src]
Bit 14 - SPDIF receiver found parity bit error
pub fn sym_err(&self) -> SYMERR_R[src]
Bit 15 - SPDIF receiver found illegal symbol
pub fn val_no_good(&self) -> VALNOGOOD_R[src]
Bit 16 - SPDIF validity flag no good
pub fn cnew(&self) -> CNEW_R[src]
Bit 17 - SPDIF receive change in value of control channel
pub fn tx_resyn(&self) -> TXRESYN_R[src]
Bit 18 - SPDIF Tx FIFO resync
pub fn tx_un_ov(&self) -> TXUNOV_R[src]
Bit 19 - SPDIF Tx FIFO under/overrun
pub fn lock(&self) -> LOCK_R[src]
Bit 20 - SPDIF receiver's DPLL is locked
impl R<u32, Reg<u32, _SIS>>[src]
pub fn rx_fifoful(&self) -> RXFIFOFUL_R[src]
Bit 0 - SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO.
pub fn tx_em(&self) -> TXEM_R[src]
Bit 1 - SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO.
pub fn lock_loss(&self) -> LOCKLOSS_R[src]
Bit 2 - SPDIF receiver loss of lock
pub fn rx_fiforesyn(&self) -> RXFIFORESYN_R[src]
Bit 3 - Rx FIFO resync
pub fn rx_fifoun_ov(&self) -> RXFIFOUNOV_R[src]
Bit 4 - Rx FIFO underrun/overrun
pub fn uqerr(&self) -> UQERR_R[src]
Bit 5 - U/Q Channel framing error
pub fn uqsync(&self) -> UQSYNC_R[src]
Bit 6 - U/Q Channel sync found
pub fn qrx_ov(&self) -> QRXOV_R[src]
Bit 7 - Q Channel receive register overrun
pub fn qrx_ful(&self) -> QRXFUL_R[src]
Bit 8 - Q Channel receive register full, can't be cleared with reg
pub fn urx_ov(&self) -> URXOV_R[src]
Bit 9 - U Channel receive register overrun
pub fn urx_ful(&self) -> URXFUL_R[src]
Bit 10 - U Channel receive register full, can't be cleared with reg
pub fn bit_err(&self) -> BITERR_R[src]
Bit 14 - SPDIF receiver found parity bit error
pub fn sym_err(&self) -> SYMERR_R[src]
Bit 15 - SPDIF receiver found illegal symbol
pub fn val_no_good(&self) -> VALNOGOOD_R[src]
Bit 16 - SPDIF validity flag no good
pub fn cnew(&self) -> CNEW_R[src]
Bit 17 - SPDIF receive change in value of control channel
pub fn tx_resyn(&self) -> TXRESYN_R[src]
Bit 18 - SPDIF Tx FIFO resync
pub fn tx_un_ov(&self) -> TXUNOV_R[src]
Bit 19 - SPDIF Tx FIFO under/overrun
pub fn lock(&self) -> LOCK_R[src]
Bit 20 - SPDIF receiver's DPLL is locked
impl R<u32, Reg<u32, _SRL>>[src]
pub fn rx_data_left(&self) -> RXDATALEFT_R[src]
Bits 0:23 - Processor receive SPDIF data left
impl R<u32, Reg<u32, _SRR>>[src]
pub fn rx_data_right(&self) -> RXDATARIGHT_R[src]
Bits 0:23 - Processor receive SPDIF data right
impl R<u32, Reg<u32, _SRCSH>>[src]
pub fn rx_cchannel_h(&self) -> RXCCHANNEL_H_R[src]
Bits 0:23 - SPDIF receive C channel register, contains first 24 bits of C channel without interpretation
impl R<u32, Reg<u32, _SRCSL>>[src]
pub fn rx_cchannel_l(&self) -> RXCCHANNEL_L_R[src]
Bits 0:23 - SPDIF receive C channel register, contains next 24 bits of C channel without interpretation
impl R<u32, Reg<u32, _SRU>>[src]
pub fn rx_uchannel(&self) -> RXUCHANNEL_R[src]
Bits 0:23 - SPDIF receive U channel register, contains next 3 U channel bytes
impl R<u32, Reg<u32, _SRQ>>[src]
pub fn rx_qchannel(&self) -> RXQCHANNEL_R[src]
Bits 0:23 - SPDIF receive Q channel register, contains next 3 Q channel bytes
impl R<u32, Reg<u32, _STCSCH>>[src]
pub fn tx_cchannel_cons_h(&self) -> TXCCHANNELCONS_H_R[src]
Bits 0:23 - SPDIF transmit Cons
impl R<u32, Reg<u32, _STCSCL>>[src]
pub fn tx_cchannel_cons_l(&self) -> TXCCHANNELCONS_L_R[src]
Bits 0:23 - SPDIF transmit Cons
impl R<u32, Reg<u32, _SRFM>>[src]
pub fn freq_meas(&self) -> FREQMEAS_R[src]
Bits 0:23 - Frequency measurement data
impl R<u8, TXCLK_DF_A>[src]
pub fn variant(&self) -> Variant<u8, TXCLK_DF_A>[src]
Get enumerated values variant
pub fn is_tx_clk_df_0(&self) -> bool[src]
Checks if the value of the field is TXCLK_DF_0
pub fn is_tx_clk_df_1(&self) -> bool[src]
Checks if the value of the field is TXCLK_DF_1
pub fn is_tx_clk_df_127(&self) -> bool[src]
Checks if the value of the field is TXCLK_DF_127
impl R<bool, TX_ALL_CLK_EN_A>[src]
pub fn variant(&self) -> TX_ALL_CLK_EN_A[src]
Get enumerated values variant
pub fn is_tx_all_clk_en_0(&self) -> bool[src]
Checks if the value of the field is TX_ALL_CLK_EN_0
pub fn is_tx_all_clk_en_1(&self) -> bool[src]
Checks if the value of the field is TX_ALL_CLK_EN_1
impl R<u8, TXCLK_SOURCE_A>[src]
pub fn variant(&self) -> Variant<u8, TXCLK_SOURCE_A>[src]
Get enumerated values variant
pub fn is_tx_clk_source_0(&self) -> bool[src]
Checks if the value of the field is TXCLK_SOURCE_0
pub fn is_tx_clk_source_1(&self) -> bool[src]
Checks if the value of the field is TXCLK_SOURCE_1
pub fn is_tx_clk_source_2(&self) -> bool[src]
Checks if the value of the field is TXCLK_SOURCE_2
pub fn is_tx_clk_source_3(&self) -> bool[src]
Checks if the value of the field is TXCLK_SOURCE_3
pub fn is_tx_clk_source_4(&self) -> bool[src]
Checks if the value of the field is TXCLK_SOURCE_4
pub fn is_tx_clk_source_5(&self) -> bool[src]
Checks if the value of the field is TXCLK_SOURCE_5
pub fn is_tx_clk_source_6(&self) -> bool[src]
Checks if the value of the field is TXCLK_SOURCE_6
impl R<u16, SYSCLK_DF_A>[src]
pub fn variant(&self) -> Variant<u16, SYSCLK_DF_A>[src]
Get enumerated values variant
pub fn is_sysclk_df_0(&self) -> bool[src]
Checks if the value of the field is SYSCLK_DF_0
pub fn is_sysclk_df_1(&self) -> bool[src]
Checks if the value of the field is SYSCLK_DF_1
pub fn is_sysclk_df_511(&self) -> bool[src]
Checks if the value of the field is SYSCLK_DF_511
impl R<u32, Reg<u32, _STC>>[src]
pub fn tx_clk_df(&self) -> TXCLK_DF_R[src]
Bits 0:6 - Divider factor (1-128)
pub fn tx_all_clk_en(&self) -> TX_ALL_CLK_EN_R[src]
Bit 7 - Spdif transfer clock enable. When data is going to be transfered, this bit should be set to1.
pub fn tx_clk_source(&self) -> TXCLK_SOURCE_R[src]
Bits 8:10 - no description available
pub fn sysclk_df(&self) -> SYSCLK_DF_R[src]
Bits 11:19 - system clock divider factor, 2~512.
Trait Implementations
Auto Trait Implementations
impl<U, T> Send for R<U, T> where
T: Send,
U: Send,
T: Send,
U: Send,
impl<U, T> Sync for R<U, T> where
T: Sync,
U: Sync,
T: Sync,
U: Sync,
impl<U, T> Unpin for R<U, T> where
T: Unpin,
U: Unpin,
T: Unpin,
U: Unpin,
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized, [src]
T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized, [src]
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized, [src]
T: ?Sized,
fn borrow_mut(&mut self) -> &mut T[src]
impl<T> From<T> for T[src]
impl<T, U> Into<U> for T where
U: From<T>, [src]
U: From<T>,
impl<T, U> TryFrom<U> for T where
U: Into<T>, [src]
U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>[src]
impl<T, U> TryInto<U> for T where
U: TryFrom<T>, [src]
U: TryFrom<T>,