Struct imxrt1062_spdif::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _SCR>>

pub fn usrc_sel(&mut self) -> USRC_SEL_W

Bits 0:1 - no description available

pub fn tx_sel(&mut self) -> TXSEL_W

Bits 2:4 - no description available

pub fn val_ctrl(&mut self) -> VALCTRL_W

Bit 5 - no description available

pub fn dma_tx_en(&mut self) -> DMA_TX_EN_W

Bit 8 - DMA Transmit Request Enable (Tx FIFO empty)

pub fn dma_rx_en(&mut self) -> DMA_RX_EN_W

Bit 9 - DMA Receive Request Enable (RX FIFO full)

pub fn tx_fifo_ctrl(&mut self) -> TXFIFO_CTRL_W

Bits 10:11 - no description available

pub fn soft_reset(&mut self) -> SOFT_RESET_W

Bit 12 - When write 1 to this bit, it will cause SPDIF software reset

pub fn low_power(&mut self) -> LOW_POWER_W

Bit 13 - When write 1 to this bit, it will cause SPDIF enter low-power mode

pub fn tx_fifoempty_sel(&mut self) -> TXFIFOEMPTY_SEL_W

Bits 15:16 - no description available

pub fn tx_auto_sync(&mut self) -> TXAUTOSYNC_W

Bit 17 - no description available

pub fn rx_auto_sync(&mut self) -> RXAUTOSYNC_W

Bit 18 - no description available

pub fn rx_fifofull_sel(&mut self) -> RXFIFOFULL_SEL_W

Bits 19:20 - no description available

pub fn rx_fifo_rst(&mut self) -> RXFIFO_RST_W

Bit 21 - no description available

pub fn rx_fifo_off_on(&mut self) -> RXFIFO_OFF_ON_W

Bit 22 - no description available

pub fn rx_fifo_ctrl(&mut self) -> RXFIFO_CTRL_W

Bit 23 - no description available

impl W<u32, Reg<u32, _SRCD>>

pub fn usync_mode(&mut self) -> USYNCMODE_W

Bit 1 - no description available

impl W<u32, Reg<u32, _SRPC>>

pub fn gain_sel(&mut self) -> GAINSEL_W

Bits 3:5 - Gain selection:

pub fn clk_src_sel(&mut self) -> CLKSRC_SEL_W

Bits 7:10 - Clock source selection, all other settings not shown are reserved:

impl W<u32, Reg<u32, _SIE>>

pub fn rx_fifoful(&mut self) -> RXFIFOFUL_W

Bit 0 - SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO.

pub fn tx_em(&mut self) -> TXEM_W

Bit 1 - SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO.

pub fn lock_loss(&mut self) -> LOCKLOSS_W

Bit 2 - SPDIF receiver loss of lock

pub fn rx_fiforesyn(&mut self) -> RXFIFORESYN_W

Bit 3 - Rx FIFO resync

pub fn rx_fifoun_ov(&mut self) -> RXFIFOUNOV_W

Bit 4 - Rx FIFO underrun/overrun

pub fn uqerr(&mut self) -> UQERR_W

Bit 5 - U/Q Channel framing error

pub fn uqsync(&mut self) -> UQSYNC_W

Bit 6 - U/Q Channel sync found

pub fn qrx_ov(&mut self) -> QRXOV_W

Bit 7 - Q Channel receive register overrun

pub fn qrx_ful(&mut self) -> QRXFUL_W

Bit 8 - Q Channel receive register full, can't be cleared with reg

pub fn urx_ov(&mut self) -> URXOV_W

Bit 9 - U Channel receive register overrun

pub fn urx_ful(&mut self) -> URXFUL_W

Bit 10 - U Channel receive register full, can't be cleared with reg

pub fn bit_err(&mut self) -> BITERR_W

Bit 14 - SPDIF receiver found parity bit error

pub fn sym_err(&mut self) -> SYMERR_W

Bit 15 - SPDIF receiver found illegal symbol

pub fn val_no_good(&mut self) -> VALNOGOOD_W

Bit 16 - SPDIF validity flag no good

pub fn cnew(&mut self) -> CNEW_W

Bit 17 - SPDIF receive change in value of control channel

pub fn tx_resyn(&mut self) -> TXRESYN_W

Bit 18 - SPDIF Tx FIFO resync

pub fn tx_un_ov(&mut self) -> TXUNOV_W

Bit 19 - SPDIF Tx FIFO under/overrun

pub fn lock(&mut self) -> LOCK_W

Bit 20 - SPDIF receiver's DPLL is locked

impl W<u32, Reg<u32, _SIC>>

pub fn lock_loss(&mut self) -> LOCKLOSS_W

Bit 2 - SPDIF receiver loss of lock

pub fn rx_fiforesyn(&mut self) -> RXFIFORESYN_W

Bit 3 - Rx FIFO resync

pub fn rx_fifoun_ov(&mut self) -> RXFIFOUNOV_W

Bit 4 - Rx FIFO underrun/overrun

pub fn uqerr(&mut self) -> UQERR_W

Bit 5 - U/Q Channel framing error

pub fn uqsync(&mut self) -> UQSYNC_W

Bit 6 - U/Q Channel sync found

pub fn qrx_ov(&mut self) -> QRXOV_W

Bit 7 - Q Channel receive register overrun

pub fn urx_ov(&mut self) -> URXOV_W

Bit 9 - U Channel receive register overrun

pub fn bit_err(&mut self) -> BITERR_W

Bit 14 - SPDIF receiver found parity bit error

pub fn sym_err(&mut self) -> SYMERR_W

Bit 15 - SPDIF receiver found illegal symbol

pub fn val_no_good(&mut self) -> VALNOGOOD_W

Bit 16 - SPDIF validity flag no good

pub fn cnew(&mut self) -> CNEW_W

Bit 17 - SPDIF receive change in value of control channel

pub fn tx_resyn(&mut self) -> TXRESYN_W

Bit 18 - SPDIF Tx FIFO resync

pub fn tx_un_ov(&mut self) -> TXUNOV_W

Bit 19 - SPDIF Tx FIFO under/overrun

pub fn lock(&mut self) -> LOCK_W

Bit 20 - SPDIF receiver's DPLL is locked

impl W<u32, Reg<u32, _STL>>

pub fn tx_data_left(&mut self) -> TXDATALEFT_W

Bits 0:23 - SPDIF transmit left channel data. It is write-only, and always returns zeros when read

impl W<u32, Reg<u32, _STR>>

pub fn tx_data_right(&mut self) -> TXDATARIGHT_W

Bits 0:23 - SPDIF transmit right channel data. It is write-only, and always returns zeros when read

impl W<u32, Reg<u32, _STCSCH>>

pub fn tx_cchannel_cons_h(&mut self) -> TXCCHANNELCONS_H_W

Bits 0:23 - SPDIF transmit Cons

impl W<u32, Reg<u32, _STCSCL>>

pub fn tx_cchannel_cons_l(&mut self) -> TXCCHANNELCONS_L_W

Bits 0:23 - SPDIF transmit Cons

impl W<u32, Reg<u32, _STC>>

pub fn tx_clk_df(&mut self) -> TXCLK_DF_W

Bits 0:6 - Divider factor (1-128)

pub fn tx_all_clk_en(&mut self) -> TX_ALL_CLK_EN_W

Bit 7 - Spdif transfer clock enable. When data is going to be transfered, this bit should be set to1.

pub fn tx_clk_source(&mut self) -> TXCLK_SOURCE_W

Bits 8:10 - no description available

pub fn sysclk_df(&mut self) -> SYSCLK_DF_W

Bits 11:19 - system clock divider factor, 2~512.