Type Definition imxrt1062_pmu::reg_core_clr::W

type W = W<u32, REG_CORE_CLR>;

Writer for register REG_CORE_CLR

Methods

impl W

pub fn reg0_targ(&mut self) -> REG0_TARG_W

Bits 0:4 - This field defines the target voltage for the ARM core power domain

pub fn reg0_adj(&mut self) -> REG0_ADJ_W

Bits 5:8 - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub fn reg1_targ(&mut self) -> REG1_TARG_W

Bits 9:13 - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.

pub fn reg1_adj(&mut self) -> REG1_ADJ_W

Bits 14:17 - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub fn reg2_targ(&mut self) -> REG2_TARG_W

Bits 18:22 - This field defines the target voltage for the SOC power domain

pub fn reg2_adj(&mut self) -> REG2_ADJ_W

Bits 23:26 - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub fn ramp_rate(&mut self) -> RAMP_RATE_W

Bits 27:28 - Regulator voltage ramp rate.

pub fn fet_odrive(&mut self) -> FET_ODRIVE_W

Bit 29 - If set, increases the gate drive on power gating FETs to reduce leakage in the off state