Struct imxrt1062_lcdif::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _CTRL>>

pub fn run(&mut self) -> RUN_W

Bit 0 - When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display

pub fn data_format_24_bit(&mut self) -> DATA_FORMAT_24_BIT_W

Bit 1 - Used only when WORD_LENGTH = 3, i

pub fn data_format_18_bit(&mut self) -> DATA_FORMAT_18_BIT_W

Bit 2 - Used only when WORD_LENGTH = 2, i.e. 18-bit.

pub fn data_format_16_bit(&mut self) -> DATA_FORMAT_16_BIT_W

Bit 3 - When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format

pub fn master(&mut self) -> MASTER_W

Bit 5 - Set this bit to make the LCDIF act as a bus master

pub fn enable_pxp_handshake(&mut self) -> ENABLE_PXP_HANDSHAKE_W

Bit 6 - If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on

pub fn word_length(&mut self) -> WORD_LENGTH_W

Bits 8:9 - Input data format.

pub fn lcd_databus_width(&mut self) -> LCD_DATABUS_WIDTH_W

Bits 10:11 - LCD Data bus transfer width.

pub fn csc_data_swizzle(&mut self) -> CSC_DATA_SWIZZLE_W

Bits 12:13 - This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus

pub fn input_data_swizzle(&mut self) -> INPUT_DATA_SWIZZLE_W

Bits 14:15 - This field specifies how to swap the bytes fetched by the bus master interface

pub fn dotclk_mode(&mut self) -> DOTCLK_MODE_W

Bit 17 - Set this bit to 1 to make the hardware go into the DOTCLK mode, i

pub fn bypass_count(&mut self) -> BYPASS_COUNT_W

Bit 19 - When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out

pub fn shift_num_bits(&mut self) -> SHIFT_NUM_BITS_W

Bits 21:25 - The data to be transmitted is shifted left or right by this number of bits.

pub fn data_shift_dir(&mut self) -> DATA_SHIFT_DIR_W

Bit 26 - Use this bit to determine the direction of shift of transmit data.

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - This bit must be set to zero for normal operation

pub fn sftrst(&mut self) -> SFTRST_W

Bit 31 - This bit must be set to zero to enable normal operation of the LCDIF

impl W<u32, Reg<u32, _CTRL_SET>>

pub fn run(&mut self) -> RUN_W

Bit 0 - When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display

pub fn data_format_24_bit(&mut self) -> DATA_FORMAT_24_BIT_W

Bit 1 - Used only when WORD_LENGTH = 3, i

pub fn data_format_18_bit(&mut self) -> DATA_FORMAT_18_BIT_W

Bit 2 - Used only when WORD_LENGTH = 2, i.e. 18-bit.

pub fn data_format_16_bit(&mut self) -> DATA_FORMAT_16_BIT_W

Bit 3 - When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format

pub fn master(&mut self) -> MASTER_W

Bit 5 - Set this bit to make the LCDIF act as a bus master

pub fn enable_pxp_handshake(&mut self) -> ENABLE_PXP_HANDSHAKE_W

Bit 6 - If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on

pub fn word_length(&mut self) -> WORD_LENGTH_W

Bits 8:9 - Input data format.

pub fn lcd_databus_width(&mut self) -> LCD_DATABUS_WIDTH_W

Bits 10:11 - LCD Data bus transfer width.

pub fn csc_data_swizzle(&mut self) -> CSC_DATA_SWIZZLE_W

Bits 12:13 - This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus

pub fn input_data_swizzle(&mut self) -> INPUT_DATA_SWIZZLE_W

Bits 14:15 - This field specifies how to swap the bytes fetched by the bus master interface

pub fn dotclk_mode(&mut self) -> DOTCLK_MODE_W

Bit 17 - Set this bit to 1 to make the hardware go into the DOTCLK mode, i

pub fn bypass_count(&mut self) -> BYPASS_COUNT_W

Bit 19 - When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out

pub fn shift_num_bits(&mut self) -> SHIFT_NUM_BITS_W

Bits 21:25 - The data to be transmitted is shifted left or right by this number of bits.

pub fn data_shift_dir(&mut self) -> DATA_SHIFT_DIR_W

Bit 26 - Use this bit to determine the direction of shift of transmit data.

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - This bit must be set to zero for normal operation

pub fn sftrst(&mut self) -> SFTRST_W

Bit 31 - This bit must be set to zero to enable normal operation of the LCDIF

impl W<u32, Reg<u32, _CTRL_CLR>>

pub fn run(&mut self) -> RUN_W

Bit 0 - When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display

pub fn data_format_24_bit(&mut self) -> DATA_FORMAT_24_BIT_W

Bit 1 - Used only when WORD_LENGTH = 3, i

pub fn data_format_18_bit(&mut self) -> DATA_FORMAT_18_BIT_W

Bit 2 - Used only when WORD_LENGTH = 2, i.e. 18-bit.

pub fn data_format_16_bit(&mut self) -> DATA_FORMAT_16_BIT_W

Bit 3 - When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format

pub fn master(&mut self) -> MASTER_W

Bit 5 - Set this bit to make the LCDIF act as a bus master

pub fn enable_pxp_handshake(&mut self) -> ENABLE_PXP_HANDSHAKE_W

Bit 6 - If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on

pub fn word_length(&mut self) -> WORD_LENGTH_W

Bits 8:9 - Input data format.

pub fn lcd_databus_width(&mut self) -> LCD_DATABUS_WIDTH_W

Bits 10:11 - LCD Data bus transfer width.

pub fn csc_data_swizzle(&mut self) -> CSC_DATA_SWIZZLE_W

Bits 12:13 - This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus

pub fn input_data_swizzle(&mut self) -> INPUT_DATA_SWIZZLE_W

Bits 14:15 - This field specifies how to swap the bytes fetched by the bus master interface

pub fn dotclk_mode(&mut self) -> DOTCLK_MODE_W

Bit 17 - Set this bit to 1 to make the hardware go into the DOTCLK mode, i

pub fn bypass_count(&mut self) -> BYPASS_COUNT_W

Bit 19 - When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out

pub fn shift_num_bits(&mut self) -> SHIFT_NUM_BITS_W

Bits 21:25 - The data to be transmitted is shifted left or right by this number of bits.

pub fn data_shift_dir(&mut self) -> DATA_SHIFT_DIR_W

Bit 26 - Use this bit to determine the direction of shift of transmit data.

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - This bit must be set to zero for normal operation

pub fn sftrst(&mut self) -> SFTRST_W

Bit 31 - This bit must be set to zero to enable normal operation of the LCDIF

impl W<u32, Reg<u32, _CTRL_TOG>>

pub fn run(&mut self) -> RUN_W

Bit 0 - When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display

pub fn data_format_24_bit(&mut self) -> DATA_FORMAT_24_BIT_W

Bit 1 - Used only when WORD_LENGTH = 3, i

pub fn data_format_18_bit(&mut self) -> DATA_FORMAT_18_BIT_W

Bit 2 - Used only when WORD_LENGTH = 2, i.e. 18-bit.

pub fn data_format_16_bit(&mut self) -> DATA_FORMAT_16_BIT_W

Bit 3 - When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format

pub fn master(&mut self) -> MASTER_W

Bit 5 - Set this bit to make the LCDIF act as a bus master

pub fn enable_pxp_handshake(&mut self) -> ENABLE_PXP_HANDSHAKE_W

Bit 6 - If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on

pub fn word_length(&mut self) -> WORD_LENGTH_W

Bits 8:9 - Input data format.

pub fn lcd_databus_width(&mut self) -> LCD_DATABUS_WIDTH_W

Bits 10:11 - LCD Data bus transfer width.

pub fn csc_data_swizzle(&mut self) -> CSC_DATA_SWIZZLE_W

Bits 12:13 - This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus

pub fn input_data_swizzle(&mut self) -> INPUT_DATA_SWIZZLE_W

Bits 14:15 - This field specifies how to swap the bytes fetched by the bus master interface

pub fn dotclk_mode(&mut self) -> DOTCLK_MODE_W

Bit 17 - Set this bit to 1 to make the hardware go into the DOTCLK mode, i

pub fn bypass_count(&mut self) -> BYPASS_COUNT_W

Bit 19 - When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out

pub fn shift_num_bits(&mut self) -> SHIFT_NUM_BITS_W

Bits 21:25 - The data to be transmitted is shifted left or right by this number of bits.

pub fn data_shift_dir(&mut self) -> DATA_SHIFT_DIR_W

Bit 26 - Use this bit to determine the direction of shift of transmit data.

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - This bit must be set to zero for normal operation

pub fn sftrst(&mut self) -> SFTRST_W

Bit 31 - This bit must be set to zero to enable normal operation of the LCDIF

impl W<u32, Reg<u32, _CTRL1>>

pub fn vsync_edge_irq(&mut self) -> VSYNC_EDGE_IRQ_W

Bit 8 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn cur_frame_done_irq(&mut self) -> CUR_FRAME_DONE_IRQ_W

Bit 9 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn underflow_irq(&mut self) -> UNDERFLOW_IRQ_W

Bit 10 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn overflow_irq(&mut self) -> OVERFLOW_IRQ_W

Bit 11 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn vsync_edge_irq_en(&mut self) -> VSYNC_EDGE_IRQ_EN_W

Bit 12 - This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode

pub fn cur_frame_done_irq_en(&mut self) -> CUR_FRAME_DONE_IRQ_EN_W

Bit 13 - This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state

pub fn underflow_irq_en(&mut self) -> UNDERFLOW_IRQ_EN_W

Bit 14 - This bit is set to enable an underflow interrupt in the TXFIFO in the write mode.

pub fn overflow_irq_en(&mut self) -> OVERFLOW_IRQ_EN_W

Bit 15 - This bit is set to enable an overflow interrupt in the TXFIFO in the write mode.

pub fn byte_packing_format(&mut self) -> BYTE_PACKING_FORMAT_W

Bits 16:19 - This bitfield is used to show which data bytes in a 32-bit word are valid

pub fn irq_on_alternate_fields(&mut self) -> IRQ_ON_ALTERNATE_FIELDS_W

Bit 20 - If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field

pub fn fifo_clear(&mut self) -> FIFO_CLEAR_W

Bit 21 - Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO.

pub fn start_interlace_from_second_field(
    &mut self
) -> START_INTERLACE_FROM_SECOND_FIELD_W

Bit 22 - The default is to grab the odd lines first and then the even lines

pub fn interlace_fields(&mut self) -> INTERLACE_FIELDS_W

Bit 23 - Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field

pub fn recover_on_underflow(&mut self) -> RECOVER_ON_UNDERFLOW_W

Bit 24 - Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame

pub fn bm_error_irq(&mut self) -> BM_ERROR_IRQ_W

Bit 25 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn bm_error_irq_en(&mut self) -> BM_ERROR_IRQ_EN_W

Bit 26 - This bit is set to enable bus master error interrupt in the LCDIF master mode.

pub fn cs_out_select(&mut self) -> CS_OUT_SELECT_W

Bit 30 - This bit is CS0/CS1 valid select signals

pub fn image_data_select(&mut self) -> IMAGE_DATA_SELECT_W

Bit 31 - Command Mode MIPI image data select bit

impl W<u32, Reg<u32, _CTRL1_SET>>

pub fn vsync_edge_irq(&mut self) -> VSYNC_EDGE_IRQ_W

Bit 8 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn cur_frame_done_irq(&mut self) -> CUR_FRAME_DONE_IRQ_W

Bit 9 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn underflow_irq(&mut self) -> UNDERFLOW_IRQ_W

Bit 10 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn overflow_irq(&mut self) -> OVERFLOW_IRQ_W

Bit 11 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn vsync_edge_irq_en(&mut self) -> VSYNC_EDGE_IRQ_EN_W

Bit 12 - This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode

pub fn cur_frame_done_irq_en(&mut self) -> CUR_FRAME_DONE_IRQ_EN_W

Bit 13 - This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state

pub fn underflow_irq_en(&mut self) -> UNDERFLOW_IRQ_EN_W

Bit 14 - This bit is set to enable an underflow interrupt in the TXFIFO in the write mode.

pub fn overflow_irq_en(&mut self) -> OVERFLOW_IRQ_EN_W

Bit 15 - This bit is set to enable an overflow interrupt in the TXFIFO in the write mode.

pub fn byte_packing_format(&mut self) -> BYTE_PACKING_FORMAT_W

Bits 16:19 - This bitfield is used to show which data bytes in a 32-bit word are valid

pub fn irq_on_alternate_fields(&mut self) -> IRQ_ON_ALTERNATE_FIELDS_W

Bit 20 - If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field

pub fn fifo_clear(&mut self) -> FIFO_CLEAR_W

Bit 21 - Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO.

pub fn start_interlace_from_second_field(
    &mut self
) -> START_INTERLACE_FROM_SECOND_FIELD_W

Bit 22 - The default is to grab the odd lines first and then the even lines

pub fn interlace_fields(&mut self) -> INTERLACE_FIELDS_W

Bit 23 - Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field

pub fn recover_on_underflow(&mut self) -> RECOVER_ON_UNDERFLOW_W

Bit 24 - Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame

pub fn bm_error_irq(&mut self) -> BM_ERROR_IRQ_W

Bit 25 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn bm_error_irq_en(&mut self) -> BM_ERROR_IRQ_EN_W

Bit 26 - This bit is set to enable bus master error interrupt in the LCDIF master mode.

pub fn cs_out_select(&mut self) -> CS_OUT_SELECT_W

Bit 30 - This bit is CS0/CS1 valid select signals

pub fn image_data_select(&mut self) -> IMAGE_DATA_SELECT_W

Bit 31 - Command Mode MIPI image data select bit

impl W<u32, Reg<u32, _CTRL1_CLR>>

pub fn vsync_edge_irq(&mut self) -> VSYNC_EDGE_IRQ_W

Bit 8 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn cur_frame_done_irq(&mut self) -> CUR_FRAME_DONE_IRQ_W

Bit 9 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn underflow_irq(&mut self) -> UNDERFLOW_IRQ_W

Bit 10 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn overflow_irq(&mut self) -> OVERFLOW_IRQ_W

Bit 11 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn vsync_edge_irq_en(&mut self) -> VSYNC_EDGE_IRQ_EN_W

Bit 12 - This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode

pub fn cur_frame_done_irq_en(&mut self) -> CUR_FRAME_DONE_IRQ_EN_W

Bit 13 - This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state

pub fn underflow_irq_en(&mut self) -> UNDERFLOW_IRQ_EN_W

Bit 14 - This bit is set to enable an underflow interrupt in the TXFIFO in the write mode.

pub fn overflow_irq_en(&mut self) -> OVERFLOW_IRQ_EN_W

Bit 15 - This bit is set to enable an overflow interrupt in the TXFIFO in the write mode.

pub fn byte_packing_format(&mut self) -> BYTE_PACKING_FORMAT_W

Bits 16:19 - This bitfield is used to show which data bytes in a 32-bit word are valid

pub fn irq_on_alternate_fields(&mut self) -> IRQ_ON_ALTERNATE_FIELDS_W

Bit 20 - If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field

pub fn fifo_clear(&mut self) -> FIFO_CLEAR_W

Bit 21 - Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO.

pub fn start_interlace_from_second_field(
    &mut self
) -> START_INTERLACE_FROM_SECOND_FIELD_W

Bit 22 - The default is to grab the odd lines first and then the even lines

pub fn interlace_fields(&mut self) -> INTERLACE_FIELDS_W

Bit 23 - Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field

pub fn recover_on_underflow(&mut self) -> RECOVER_ON_UNDERFLOW_W

Bit 24 - Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame

pub fn bm_error_irq(&mut self) -> BM_ERROR_IRQ_W

Bit 25 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn bm_error_irq_en(&mut self) -> BM_ERROR_IRQ_EN_W

Bit 26 - This bit is set to enable bus master error interrupt in the LCDIF master mode.

pub fn cs_out_select(&mut self) -> CS_OUT_SELECT_W

Bit 30 - This bit is CS0/CS1 valid select signals

pub fn image_data_select(&mut self) -> IMAGE_DATA_SELECT_W

Bit 31 - Command Mode MIPI image data select bit

impl W<u32, Reg<u32, _CTRL1_TOG>>

pub fn vsync_edge_irq(&mut self) -> VSYNC_EDGE_IRQ_W

Bit 8 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn cur_frame_done_irq(&mut self) -> CUR_FRAME_DONE_IRQ_W

Bit 9 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn underflow_irq(&mut self) -> UNDERFLOW_IRQ_W

Bit 10 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn overflow_irq(&mut self) -> OVERFLOW_IRQ_W

Bit 11 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn vsync_edge_irq_en(&mut self) -> VSYNC_EDGE_IRQ_EN_W

Bit 12 - This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode

pub fn cur_frame_done_irq_en(&mut self) -> CUR_FRAME_DONE_IRQ_EN_W

Bit 13 - This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state

pub fn underflow_irq_en(&mut self) -> UNDERFLOW_IRQ_EN_W

Bit 14 - This bit is set to enable an underflow interrupt in the TXFIFO in the write mode.

pub fn overflow_irq_en(&mut self) -> OVERFLOW_IRQ_EN_W

Bit 15 - This bit is set to enable an overflow interrupt in the TXFIFO in the write mode.

pub fn byte_packing_format(&mut self) -> BYTE_PACKING_FORMAT_W

Bits 16:19 - This bitfield is used to show which data bytes in a 32-bit word are valid

pub fn irq_on_alternate_fields(&mut self) -> IRQ_ON_ALTERNATE_FIELDS_W

Bit 20 - If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field

pub fn fifo_clear(&mut self) -> FIFO_CLEAR_W

Bit 21 - Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO.

pub fn start_interlace_from_second_field(
    &mut self
) -> START_INTERLACE_FROM_SECOND_FIELD_W

Bit 22 - The default is to grab the odd lines first and then the even lines

pub fn interlace_fields(&mut self) -> INTERLACE_FIELDS_W

Bit 23 - Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field

pub fn recover_on_underflow(&mut self) -> RECOVER_ON_UNDERFLOW_W

Bit 24 - Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame

pub fn bm_error_irq(&mut self) -> BM_ERROR_IRQ_W

Bit 25 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn bm_error_irq_en(&mut self) -> BM_ERROR_IRQ_EN_W

Bit 26 - This bit is set to enable bus master error interrupt in the LCDIF master mode.

pub fn cs_out_select(&mut self) -> CS_OUT_SELECT_W

Bit 30 - This bit is CS0/CS1 valid select signals

pub fn image_data_select(&mut self) -> IMAGE_DATA_SELECT_W

Bit 31 - Command Mode MIPI image data select bit

impl W<u32, Reg<u32, _CTRL2>>

pub fn even_line_pattern(&mut self) -> EVEN_LINE_PATTERN_W

Bits 12:14 - This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,

pub fn odd_line_pattern(&mut self) -> ODD_LINE_PATTERN_W

Bits 16:18 - This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,

pub fn burst_len_8(&mut self) -> BURST_LEN_8_W

Bit 20 - By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)

pub fn outstanding_reqs(&mut self) -> OUTSTANDING_REQS_W

Bits 21:23 - This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master

impl W<u32, Reg<u32, _CTRL2_SET>>

pub fn even_line_pattern(&mut self) -> EVEN_LINE_PATTERN_W

Bits 12:14 - This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,

pub fn odd_line_pattern(&mut self) -> ODD_LINE_PATTERN_W

Bits 16:18 - This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,

pub fn burst_len_8(&mut self) -> BURST_LEN_8_W

Bit 20 - By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)

pub fn outstanding_reqs(&mut self) -> OUTSTANDING_REQS_W

Bits 21:23 - This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master

impl W<u32, Reg<u32, _CTRL2_CLR>>

pub fn even_line_pattern(&mut self) -> EVEN_LINE_PATTERN_W

Bits 12:14 - This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,

pub fn odd_line_pattern(&mut self) -> ODD_LINE_PATTERN_W

Bits 16:18 - This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,

pub fn burst_len_8(&mut self) -> BURST_LEN_8_W

Bit 20 - By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)

pub fn outstanding_reqs(&mut self) -> OUTSTANDING_REQS_W

Bits 21:23 - This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master

impl W<u32, Reg<u32, _CTRL2_TOG>>

pub fn even_line_pattern(&mut self) -> EVEN_LINE_PATTERN_W

Bits 12:14 - This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,

pub fn odd_line_pattern(&mut self) -> ODD_LINE_PATTERN_W

Bits 16:18 - This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,

pub fn burst_len_8(&mut self) -> BURST_LEN_8_W

Bit 20 - By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)

pub fn outstanding_reqs(&mut self) -> OUTSTANDING_REQS_W

Bits 21:23 - This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master

impl W<u32, Reg<u32, _TRANSFER_COUNT>>

pub fn h_count(&mut self) -> H_COUNT_W

Bits 0:15 - Total valid data (pixels) in each horizontal line

pub fn v_count(&mut self) -> V_COUNT_W

Bits 16:31 - Number of horizontal lines per frame which contain valid data

impl W<u32, Reg<u32, _CUR_BUF>>

pub fn addr(&mut self) -> ADDR_W

Bits 0:31 - Address of the current frame being transmitted by LCDIF.

impl W<u32, Reg<u32, _NEXT_BUF>>

pub fn addr(&mut self) -> ADDR_W

Bits 0:31 - Address of the next frame that will be transmitted by LCDIF.

impl W<u32, Reg<u32, _VDCTRL0>>

pub fn vsync_pulse_width(&mut self) -> VSYNC_PULSE_WIDTH_W

Bits 0:17 - Number of units for which VSYNC signal is active

pub fn half_line_mode(&mut self) -> HALF_LINE_MODE_W

Bit 18 - When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line

pub fn half_line(&mut self) -> HALF_LINE_W

Bit 19 - Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i

pub fn vsync_pulse_width_unit(&mut self) -> VSYNC_PULSE_WIDTH_UNIT_W

Bit 20 - Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn vsync_period_unit(&mut self) -> VSYNC_PERIOD_UNIT_W

Bit 21 - Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn enable_pol(&mut self) -> ENABLE_POL_W

Bit 24 - Default 0 active low during valid data transfer on each horizontal line.

pub fn dotclk_pol(&mut self) -> DOTCLK_POL_W

Bit 25 - Default is data launched at negative edge of DOTCLK and captured at positive edge

pub fn hsync_pol(&mut self) -> HSYNC_POL_W

Bit 26 - Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period

pub fn vsync_pol(&mut self) -> VSYNC_POL_W

Bit 27 - Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period

pub fn enable_present(&mut self) -> ENABLE_PRESENT_W

Bit 28 - Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK

impl W<u32, Reg<u32, _VDCTRL0_SET>>

pub fn vsync_pulse_width(&mut self) -> VSYNC_PULSE_WIDTH_W

Bits 0:17 - Number of units for which VSYNC signal is active

pub fn half_line_mode(&mut self) -> HALF_LINE_MODE_W

Bit 18 - When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line

pub fn half_line(&mut self) -> HALF_LINE_W

Bit 19 - Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i

pub fn vsync_pulse_width_unit(&mut self) -> VSYNC_PULSE_WIDTH_UNIT_W

Bit 20 - Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn vsync_period_unit(&mut self) -> VSYNC_PERIOD_UNIT_W

Bit 21 - Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn enable_pol(&mut self) -> ENABLE_POL_W

Bit 24 - Default 0 active low during valid data transfer on each horizontal line.

pub fn dotclk_pol(&mut self) -> DOTCLK_POL_W

Bit 25 - Default is data launched at negative edge of DOTCLK and captured at positive edge

pub fn hsync_pol(&mut self) -> HSYNC_POL_W

Bit 26 - Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period

pub fn vsync_pol(&mut self) -> VSYNC_POL_W

Bit 27 - Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period

pub fn enable_present(&mut self) -> ENABLE_PRESENT_W

Bit 28 - Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK

impl W<u32, Reg<u32, _VDCTRL0_CLR>>

pub fn vsync_pulse_width(&mut self) -> VSYNC_PULSE_WIDTH_W

Bits 0:17 - Number of units for which VSYNC signal is active

pub fn half_line_mode(&mut self) -> HALF_LINE_MODE_W

Bit 18 - When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line

pub fn half_line(&mut self) -> HALF_LINE_W

Bit 19 - Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i

pub fn vsync_pulse_width_unit(&mut self) -> VSYNC_PULSE_WIDTH_UNIT_W

Bit 20 - Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn vsync_period_unit(&mut self) -> VSYNC_PERIOD_UNIT_W

Bit 21 - Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn enable_pol(&mut self) -> ENABLE_POL_W

Bit 24 - Default 0 active low during valid data transfer on each horizontal line.

pub fn dotclk_pol(&mut self) -> DOTCLK_POL_W

Bit 25 - Default is data launched at negative edge of DOTCLK and captured at positive edge

pub fn hsync_pol(&mut self) -> HSYNC_POL_W

Bit 26 - Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period

pub fn vsync_pol(&mut self) -> VSYNC_POL_W

Bit 27 - Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period

pub fn enable_present(&mut self) -> ENABLE_PRESENT_W

Bit 28 - Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK

impl W<u32, Reg<u32, _VDCTRL0_TOG>>

pub fn vsync_pulse_width(&mut self) -> VSYNC_PULSE_WIDTH_W

Bits 0:17 - Number of units for which VSYNC signal is active

pub fn half_line_mode(&mut self) -> HALF_LINE_MODE_W

Bit 18 - When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line

pub fn half_line(&mut self) -> HALF_LINE_W

Bit 19 - Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i

pub fn vsync_pulse_width_unit(&mut self) -> VSYNC_PULSE_WIDTH_UNIT_W

Bit 20 - Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn vsync_period_unit(&mut self) -> VSYNC_PERIOD_UNIT_W

Bit 21 - Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn enable_pol(&mut self) -> ENABLE_POL_W

Bit 24 - Default 0 active low during valid data transfer on each horizontal line.

pub fn dotclk_pol(&mut self) -> DOTCLK_POL_W

Bit 25 - Default is data launched at negative edge of DOTCLK and captured at positive edge

pub fn hsync_pol(&mut self) -> HSYNC_POL_W

Bit 26 - Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period

pub fn vsync_pol(&mut self) -> VSYNC_POL_W

Bit 27 - Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period

pub fn enable_present(&mut self) -> ENABLE_PRESENT_W

Bit 28 - Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK

impl W<u32, Reg<u32, _VDCTRL1>>

pub fn vsync_period(&mut self) -> VSYNC_PERIOD_W

Bits 0:31 - Total number of units between two positive or two negative edges of the VSYNC signal

impl W<u32, Reg<u32, _VDCTRL2>>

pub fn hsync_period(&mut self) -> HSYNC_PERIOD_W

Bits 0:17 - Total number of DISPLAY CLOCK (pix_clk) cycles between two positive or two negative edges of the HSYNC signal

pub fn hsync_pulse_width(&mut self) -> HSYNC_PULSE_WIDTH_W

Bits 18:31 - Number of DISPLAY CLOCK (pix_clk) cycles for which HSYNC signal is active.

impl W<u32, Reg<u32, _VDCTRL3>>

pub fn vertical_wait_cnt(&mut self) -> VERTICAL_WAIT_CNT_W

Bits 0:15 - In the VSYNC interface mode, wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set

pub fn horizontal_wait_cnt(&mut self) -> HORIZONTAL_WAIT_CNT_W

Bits 16:27 - In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins

pub fn vsync_only(&mut self) -> VSYNC_ONLY_W

Bit 28 - This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation.

pub fn mux_sync_signals(&mut self) -> MUX_SYNC_SIGNALS_W

Bit 29 - When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins

impl W<u32, Reg<u32, _VDCTRL4>>

pub fn dotclk_h_valid_data_cnt(&mut self) -> DOTCLK_H_VALID_DATA_CNT_W

Bits 0:17 - Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode

pub fn sync_signals_on(&mut self) -> SYNC_SIGNALS_ON_W

Bit 18 - Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end

pub fn dotclk_dly_sel(&mut self) -> DOTCLK_DLY_SEL_W

Bits 29:31 - This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin

impl W<u32, Reg<u32, _BM_ERROR_STAT>>

pub fn addr(&mut self) -> ADDR_W

Bits 0:31 - Virtual address at which bus master error occurred.

impl W<u32, Reg<u32, _CRC_STAT>>

pub fn crc_value(&mut self) -> CRC_VALUE_W

Bits 0:31 - Calculated CRC value.

impl W<u32, Reg<u32, _PIGEONCTRL0>>

pub fn fd_period(&mut self) -> FD_PERIOD_W

Bits 0:11 - Period of line counter during FD phase

pub fn ld_period(&mut self) -> LD_PERIOD_W

Bits 16:27 - Period of pclk counter during LD phase

impl W<u32, Reg<u32, _PIGEONCTRL0_SET>>

pub fn fd_period(&mut self) -> FD_PERIOD_W

Bits 0:11 - Period of line counter during FD phase

pub fn ld_period(&mut self) -> LD_PERIOD_W

Bits 16:27 - Period of pclk counter during LD phase

impl W<u32, Reg<u32, _PIGEONCTRL0_CLR>>

pub fn fd_period(&mut self) -> FD_PERIOD_W

Bits 0:11 - Period of line counter during FD phase

pub fn ld_period(&mut self) -> LD_PERIOD_W

Bits 16:27 - Period of pclk counter during LD phase

impl W<u32, Reg<u32, _PIGEONCTRL0_TOG>>

pub fn fd_period(&mut self) -> FD_PERIOD_W

Bits 0:11 - Period of line counter during FD phase

pub fn ld_period(&mut self) -> LD_PERIOD_W

Bits 16:27 - Period of pclk counter during LD phase

impl W<u32, Reg<u32, _PIGEONCTRL1>>

pub fn frame_cnt_period(&mut self) -> FRAME_CNT_PERIOD_W

Bits 0:11 - Period of frame counter

pub fn frame_cnt_cycles(&mut self) -> FRAME_CNT_CYCLES_W

Bits 16:27 - Max cycles of frame counter

impl W<u32, Reg<u32, _PIGEONCTRL1_SET>>

pub fn frame_cnt_period(&mut self) -> FRAME_CNT_PERIOD_W

Bits 0:11 - Period of frame counter

pub fn frame_cnt_cycles(&mut self) -> FRAME_CNT_CYCLES_W

Bits 16:27 - Max cycles of frame counter

impl W<u32, Reg<u32, _PIGEONCTRL1_CLR>>

pub fn frame_cnt_period(&mut self) -> FRAME_CNT_PERIOD_W

Bits 0:11 - Period of frame counter

pub fn frame_cnt_cycles(&mut self) -> FRAME_CNT_CYCLES_W

Bits 16:27 - Max cycles of frame counter

impl W<u32, Reg<u32, _PIGEONCTRL1_TOG>>

pub fn frame_cnt_period(&mut self) -> FRAME_CNT_PERIOD_W

Bits 0:11 - Period of frame counter

pub fn frame_cnt_cycles(&mut self) -> FRAME_CNT_CYCLES_W

Bits 16:27 - Max cycles of frame counter

impl W<u32, Reg<u32, _PIGEONCTRL2>>

pub fn pigeon_data_en(&mut self) -> PIGEON_DATA_EN_W

Bit 0 - Pigeon mode data enable

pub fn pigeon_clk_gate(&mut self) -> PIGEON_CLK_GATE_W

Bit 1 - Pigeon mode dot clock gate enable

impl W<u32, Reg<u32, _PIGEONCTRL2_SET>>

pub fn pigeon_data_en(&mut self) -> PIGEON_DATA_EN_W

Bit 0 - Pigeon mode data enable

pub fn pigeon_clk_gate(&mut self) -> PIGEON_CLK_GATE_W

Bit 1 - Pigeon mode dot clock gate enable

impl W<u32, Reg<u32, _PIGEONCTRL2_CLR>>

pub fn pigeon_data_en(&mut self) -> PIGEON_DATA_EN_W

Bit 0 - Pigeon mode data enable

pub fn pigeon_clk_gate(&mut self) -> PIGEON_CLK_GATE_W

Bit 1 - Pigeon mode dot clock gate enable

impl W<u32, Reg<u32, _PIGEONCTRL2_TOG>>

pub fn pigeon_data_en(&mut self) -> PIGEON_DATA_EN_W

Bit 0 - Pigeon mode data enable

pub fn pigeon_clk_gate(&mut self) -> PIGEON_CLK_GATE_W

Bit 1 - Pigeon mode dot clock gate enable

impl W<u32, Reg<u32, _PIGEON_0_0>>

pub fn en(&mut self) -> EN_W

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&mut self) -> POL_W

Bit 1 - Polarity of signal output

pub fn inc_sel(&mut self) -> INC_SEL_W

Bits 2:3 - Event to incrment local counter

pub fn offset(&mut self) -> OFFSET_W

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&mut self) -> MASK_CNT_SEL_W

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&mut self) -> MASK_CNT_W

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&mut self) -> STATE_MASK_W

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl W<u32, Reg<u32, _PIGEON_0_1>>

pub fn set_cnt(&mut self) -> SET_CNT_W

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&mut self) -> CLR_CNT_W

Bits 16:31 - Deassert signal output when counter match this value

impl W<u32, Reg<u32, _PIGEON_0_2>>

pub fn sig_logic(&mut self) -> SIG_LOGIC_W

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&mut self) -> SIG_ANOTHER_W

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl W<u32, Reg<u32, _PIGEON_1_0>>

pub fn en(&mut self) -> EN_W

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&mut self) -> POL_W

Bit 1 - Polarity of signal output

pub fn inc_sel(&mut self) -> INC_SEL_W

Bits 2:3 - Event to incrment local counter

pub fn offset(&mut self) -> OFFSET_W

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&mut self) -> MASK_CNT_SEL_W

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&mut self) -> MASK_CNT_W

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&mut self) -> STATE_MASK_W

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl W<u32, Reg<u32, _PIGEON_1_1>>

pub fn set_cnt(&mut self) -> SET_CNT_W

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&mut self) -> CLR_CNT_W

Bits 16:31 - Deassert signal output when counter match this value

impl W<u32, Reg<u32, _PIGEON_1_2>>

pub fn sig_logic(&mut self) -> SIG_LOGIC_W

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&mut self) -> SIG_ANOTHER_W

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl W<u32, Reg<u32, _PIGEON_2_0>>

pub fn en(&mut self) -> EN_W

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&mut self) -> POL_W

Bit 1 - Polarity of signal output

pub fn inc_sel(&mut self) -> INC_SEL_W

Bits 2:3 - Event to incrment local counter

pub fn offset(&mut self) -> OFFSET_W

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&mut self) -> MASK_CNT_SEL_W

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&mut self) -> MASK_CNT_W

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&mut self) -> STATE_MASK_W

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl W<u32, Reg<u32, _PIGEON_2_1>>

pub fn set_cnt(&mut self) -> SET_CNT_W

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&mut self) -> CLR_CNT_W

Bits 16:31 - Deassert signal output when counter match this value

impl W<u32, Reg<u32, _PIGEON_2_2>>

pub fn sig_logic(&mut self) -> SIG_LOGIC_W

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&mut self) -> SIG_ANOTHER_W

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl W<u32, Reg<u32, _PIGEON_3_0>>

pub fn en(&mut self) -> EN_W

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&mut self) -> POL_W

Bit 1 - Polarity of signal output

pub fn inc_sel(&mut self) -> INC_SEL_W

Bits 2:3 - Event to incrment local counter

pub fn offset(&mut self) -> OFFSET_W

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&mut self) -> MASK_CNT_SEL_W

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&mut self) -> MASK_CNT_W

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&mut self) -> STATE_MASK_W

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl W<u32, Reg<u32, _PIGEON_3_1>>

pub fn set_cnt(&mut self) -> SET_CNT_W

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&mut self) -> CLR_CNT_W

Bits 16:31 - Deassert signal output when counter match this value

impl W<u32, Reg<u32, _PIGEON_3_2>>

pub fn sig_logic(&mut self) -> SIG_LOGIC_W

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&mut self) -> SIG_ANOTHER_W

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl W<u32, Reg<u32, _PIGEON_4_0>>

pub fn en(&mut self) -> EN_W

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&mut self) -> POL_W

Bit 1 - Polarity of signal output

pub fn inc_sel(&mut self) -> INC_SEL_W

Bits 2:3 - Event to incrment local counter

pub fn offset(&mut self) -> OFFSET_W

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&mut self) -> MASK_CNT_SEL_W

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&mut self) -> MASK_CNT_W

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&mut self) -> STATE_MASK_W

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl W<u32, Reg<u32, _PIGEON_4_1>>

pub fn set_cnt(&mut self) -> SET_CNT_W

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&mut self) -> CLR_CNT_W

Bits 16:31 - Deassert signal output when counter match this value

impl W<u32, Reg<u32, _PIGEON_4_2>>

pub fn sig_logic(&mut self) -> SIG_LOGIC_W

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&mut self) -> SIG_ANOTHER_W

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl W<u32, Reg<u32, _PIGEON_5_0>>

pub fn en(&mut self) -> EN_W

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&mut self) -> POL_W

Bit 1 - Polarity of signal output

pub fn inc_sel(&mut self) -> INC_SEL_W

Bits 2:3 - Event to incrment local counter

pub fn offset(&mut self) -> OFFSET_W

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&mut self) -> MASK_CNT_SEL_W

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&mut self) -> MASK_CNT_W

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&mut self) -> STATE_MASK_W

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl W<u32, Reg<u32, _PIGEON_5_1>>

pub fn set_cnt(&mut self) -> SET_CNT_W

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&mut self) -> CLR_CNT_W

Bits 16:31 - Deassert signal output when counter match this value

impl W<u32, Reg<u32, _PIGEON_5_2>>

pub fn sig_logic(&mut self) -> SIG_LOGIC_W

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&mut self) -> SIG_ANOTHER_W

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl W<u32, Reg<u32, _PIGEON_6_0>>

pub fn en(&mut self) -> EN_W

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&mut self) -> POL_W

Bit 1 - Polarity of signal output

pub fn inc_sel(&mut self) -> INC_SEL_W

Bits 2:3 - Event to incrment local counter

pub fn offset(&mut self) -> OFFSET_W

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&mut self) -> MASK_CNT_SEL_W

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&mut self) -> MASK_CNT_W

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&mut self) -> STATE_MASK_W

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl W<u32, Reg<u32, _PIGEON_6_1>>

pub fn set_cnt(&mut self) -> SET_CNT_W

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&mut self) -> CLR_CNT_W

Bits 16:31 - Deassert signal output when counter match this value

impl W<u32, Reg<u32, _PIGEON_6_2>>

pub fn sig_logic(&mut self) -> SIG_LOGIC_W

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&mut self) -> SIG_ANOTHER_W

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl W<u32, Reg<u32, _PIGEON_7_0>>

pub fn en(&mut self) -> EN_W

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&mut self) -> POL_W

Bit 1 - Polarity of signal output

pub fn inc_sel(&mut self) -> INC_SEL_W

Bits 2:3 - Event to incrment local counter

pub fn offset(&mut self) -> OFFSET_W

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&mut self) -> MASK_CNT_SEL_W

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&mut self) -> MASK_CNT_W

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&mut self) -> STATE_MASK_W

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl W<u32, Reg<u32, _PIGEON_7_1>>

pub fn set_cnt(&mut self) -> SET_CNT_W

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&mut self) -> CLR_CNT_W

Bits 16:31 - Deassert signal output when counter match this value

impl W<u32, Reg<u32, _PIGEON_7_2>>

pub fn sig_logic(&mut self) -> SIG_LOGIC_W

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&mut self) -> SIG_ANOTHER_W

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl W<u32, Reg<u32, _PIGEON_8_0>>

pub fn en(&mut self) -> EN_W

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&mut self) -> POL_W

Bit 1 - Polarity of signal output

pub fn inc_sel(&mut self) -> INC_SEL_W

Bits 2:3 - Event to incrment local counter

pub fn offset(&mut self) -> OFFSET_W

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&mut self) -> MASK_CNT_SEL_W

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&mut self) -> MASK_CNT_W

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&mut self) -> STATE_MASK_W

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl W<u32, Reg<u32, _PIGEON_8_1>>

pub fn set_cnt(&mut self) -> SET_CNT_W

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&mut self) -> CLR_CNT_W

Bits 16:31 - Deassert signal output when counter match this value

impl W<u32, Reg<u32, _PIGEON_8_2>>

pub fn sig_logic(&mut self) -> SIG_LOGIC_W

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&mut self) -> SIG_ANOTHER_W

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl W<u32, Reg<u32, _PIGEON_9_0>>

pub fn en(&mut self) -> EN_W

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&mut self) -> POL_W

Bit 1 - Polarity of signal output

pub fn inc_sel(&mut self) -> INC_SEL_W

Bits 2:3 - Event to incrment local counter

pub fn offset(&mut self) -> OFFSET_W

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&mut self) -> MASK_CNT_SEL_W

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&mut self) -> MASK_CNT_W

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&mut self) -> STATE_MASK_W

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl W<u32, Reg<u32, _PIGEON_9_1>>

pub fn set_cnt(&mut self) -> SET_CNT_W

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&mut self) -> CLR_CNT_W

Bits 16:31 - Deassert signal output when counter match this value

impl W<u32, Reg<u32, _PIGEON_9_2>>

pub fn sig_logic(&mut self) -> SIG_LOGIC_W

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&mut self) -> SIG_ANOTHER_W

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl W<u32, Reg<u32, _PIGEON_10_0>>

pub fn en(&mut self) -> EN_W

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&mut self) -> POL_W

Bit 1 - Polarity of signal output

pub fn inc_sel(&mut self) -> INC_SEL_W

Bits 2:3 - Event to incrment local counter

pub fn offset(&mut self) -> OFFSET_W

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&mut self) -> MASK_CNT_SEL_W

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&mut self) -> MASK_CNT_W

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&mut self) -> STATE_MASK_W

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl W<u32, Reg<u32, _PIGEON_10_1>>

pub fn set_cnt(&mut self) -> SET_CNT_W

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&mut self) -> CLR_CNT_W

Bits 16:31 - Deassert signal output when counter match this value

impl W<u32, Reg<u32, _PIGEON_10_2>>

pub fn sig_logic(&mut self) -> SIG_LOGIC_W

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&mut self) -> SIG_ANOTHER_W

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl W<u32, Reg<u32, _PIGEON_11_0>>

pub fn en(&mut self) -> EN_W

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&mut self) -> POL_W

Bit 1 - Polarity of signal output

pub fn inc_sel(&mut self) -> INC_SEL_W

Bits 2:3 - Event to incrment local counter

pub fn offset(&mut self) -> OFFSET_W

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&mut self) -> MASK_CNT_SEL_W

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&mut self) -> MASK_CNT_W

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&mut self) -> STATE_MASK_W

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl W<u32, Reg<u32, _PIGEON_11_1>>

pub fn set_cnt(&mut self) -> SET_CNT_W

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&mut self) -> CLR_CNT_W

Bits 16:31 - Deassert signal output when counter match this value

impl W<u32, Reg<u32, _PIGEON_11_2>>

pub fn sig_logic(&mut self) -> SIG_LOGIC_W

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&mut self) -> SIG_ANOTHER_W

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl W<u32, Reg<u32, _LUT_CTRL>>

pub fn lut_bypass(&mut self) -> LUT_BYPASS_W

Bit 0 - Setting this bit will bypass the LUT memory resource completely

impl W<u32, Reg<u32, _LUT0_ADDR>>

pub fn addr(&mut self) -> ADDR_W

Bits 0:7 - LUT indexed address pointer

impl W<u32, Reg<u32, _LUT0_DATA>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Writing this field will load 4 bytes, aligned to four byte boundaries, of data indexed by the ADDR field of the REG_LUT_CTRL register

impl W<u32, Reg<u32, _LUT1_ADDR>>

pub fn addr(&mut self) -> ADDR_W

Bits 0:7 - LUT indexed address pointer

impl W<u32, Reg<u32, _LUT1_DATA>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Writing this field will load 4 bytes, aligned to four byte boundaries, of data indexed by the ADDR field of the REG_LUT_CTRL register