Struct imxrt1062_lcdif::R

pub struct R<U, T> { /* fields omitted */ }

Register/field reader

Result of the read method of a register. Also it can be used in the modify method

Methods

impl<U, T> R<U, T> where
    U: Copy, 

pub fn bits(&self) -> U

Read raw bits from register/field

impl<FI> R<bool, FI>

pub fn bit(&self) -> bool

Value of the field as raw bits

pub fn bit_is_clear(&self) -> bool

Returns true if the bit is clear (0)

pub fn bit_is_set(&self) -> bool

Returns true if the bit is set (1)

impl R<bool, DATA_FORMAT_24_BIT_A>

pub fn variant(&self) -> DATA_FORMAT_24_BIT_A

Get enumerated values variant

pub fn is_all_24_bits_valid(&self) -> bool

Checks if the value of the field is ALL_24_BITS_VALID

pub fn is_drop_upper_2_bits_per_byte(&self) -> bool

Checks if the value of the field is DROP_UPPER_2_BITS_PER_BYTE

impl R<bool, DATA_FORMAT_18_BIT_A>

pub fn variant(&self) -> DATA_FORMAT_18_BIT_A

Get enumerated values variant

pub fn is_lower_18_bits_valid(&self) -> bool

Checks if the value of the field is LOWER_18_BITS_VALID

pub fn is_upper_18_bits_valid(&self) -> bool

Checks if the value of the field is UPPER_18_BITS_VALID

impl R<u8, WORD_LENGTH_A>

pub fn variant(&self) -> WORD_LENGTH_A

Get enumerated values variant

pub fn is_16_bit(&self) -> bool

Checks if the value of the field is _16_BIT

pub fn is_8_bit(&self) -> bool

Checks if the value of the field is _8_BIT

pub fn is_18_bit(&self) -> bool

Checks if the value of the field is _18_BIT

pub fn is_24_bit(&self) -> bool

Checks if the value of the field is _24_BIT

impl R<u8, LCD_DATABUS_WIDTH_A>

pub fn variant(&self) -> LCD_DATABUS_WIDTH_A

Get enumerated values variant

pub fn is_16_bit(&self) -> bool

Checks if the value of the field is _16_BIT

pub fn is_8_bit(&self) -> bool

Checks if the value of the field is _8_BIT

pub fn is_18_bit(&self) -> bool

Checks if the value of the field is _18_BIT

pub fn is_24_bit(&self) -> bool

Checks if the value of the field is _24_BIT

impl R<u8, CSC_DATA_SWIZZLE_A>

pub fn variant(&self) -> CSC_DATA_SWIZZLE_A

Get enumerated values variant

pub fn is_no_swap(&self) -> bool

Checks if the value of the field is NO_SWAP

pub fn is_big_endian_swap(&self) -> bool

Checks if the value of the field is BIG_ENDIAN_SWAP

pub fn is_hwd_swap(&self) -> bool

Checks if the value of the field is HWD_SWAP

pub fn is_hwd_byte_swap(&self) -> bool

Checks if the value of the field is HWD_BYTE_SWAP

impl R<u8, INPUT_DATA_SWIZZLE_A>

pub fn variant(&self) -> INPUT_DATA_SWIZZLE_A

Get enumerated values variant

pub fn is_no_swap(&self) -> bool

Checks if the value of the field is NO_SWAP

pub fn is_big_endian_swap(&self) -> bool

Checks if the value of the field is BIG_ENDIAN_SWAP

pub fn is_hwd_swap(&self) -> bool

Checks if the value of the field is HWD_SWAP

pub fn is_hwd_byte_swap(&self) -> bool

Checks if the value of the field is HWD_BYTE_SWAP

impl R<bool, DATA_SHIFT_DIR_A>

pub fn variant(&self) -> DATA_SHIFT_DIR_A

Get enumerated values variant

pub fn is_txdata_shift_left(&self) -> bool

Checks if the value of the field is TXDATA_SHIFT_LEFT

pub fn is_txdata_shift_right(&self) -> bool

Checks if the value of the field is TXDATA_SHIFT_RIGHT

impl R<u32, Reg<u32, _CTRL>>

pub fn run(&self) -> RUN_R

Bit 0 - When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display

pub fn data_format_24_bit(&self) -> DATA_FORMAT_24_BIT_R

Bit 1 - Used only when WORD_LENGTH = 3, i

pub fn data_format_18_bit(&self) -> DATA_FORMAT_18_BIT_R

Bit 2 - Used only when WORD_LENGTH = 2, i.e. 18-bit.

pub fn data_format_16_bit(&self) -> DATA_FORMAT_16_BIT_R

Bit 3 - When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format

pub fn master(&self) -> MASTER_R

Bit 5 - Set this bit to make the LCDIF act as a bus master

pub fn enable_pxp_handshake(&self) -> ENABLE_PXP_HANDSHAKE_R

Bit 6 - If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on

pub fn word_length(&self) -> WORD_LENGTH_R

Bits 8:9 - Input data format.

pub fn lcd_databus_width(&self) -> LCD_DATABUS_WIDTH_R

Bits 10:11 - LCD Data bus transfer width.

pub fn csc_data_swizzle(&self) -> CSC_DATA_SWIZZLE_R

Bits 12:13 - This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus

pub fn input_data_swizzle(&self) -> INPUT_DATA_SWIZZLE_R

Bits 14:15 - This field specifies how to swap the bytes fetched by the bus master interface

pub fn dotclk_mode(&self) -> DOTCLK_MODE_R

Bit 17 - Set this bit to 1 to make the hardware go into the DOTCLK mode, i

pub fn bypass_count(&self) -> BYPASS_COUNT_R

Bit 19 - When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out

pub fn shift_num_bits(&self) -> SHIFT_NUM_BITS_R

Bits 21:25 - The data to be transmitted is shifted left or right by this number of bits.

pub fn data_shift_dir(&self) -> DATA_SHIFT_DIR_R

Bit 26 - Use this bit to determine the direction of shift of transmit data.

pub fn clkgate(&self) -> CLKGATE_R

Bit 30 - This bit must be set to zero for normal operation

pub fn sftrst(&self) -> SFTRST_R

Bit 31 - This bit must be set to zero to enable normal operation of the LCDIF

impl R<bool, DATA_FORMAT_24_BIT_A>

pub fn variant(&self) -> DATA_FORMAT_24_BIT_A

Get enumerated values variant

pub fn is_all_24_bits_valid(&self) -> bool

Checks if the value of the field is ALL_24_BITS_VALID

pub fn is_drop_upper_2_bits_per_byte(&self) -> bool

Checks if the value of the field is DROP_UPPER_2_BITS_PER_BYTE

impl R<bool, DATA_FORMAT_18_BIT_A>

pub fn variant(&self) -> DATA_FORMAT_18_BIT_A

Get enumerated values variant

pub fn is_lower_18_bits_valid(&self) -> bool

Checks if the value of the field is LOWER_18_BITS_VALID

pub fn is_upper_18_bits_valid(&self) -> bool

Checks if the value of the field is UPPER_18_BITS_VALID

impl R<u8, WORD_LENGTH_A>

pub fn variant(&self) -> WORD_LENGTH_A

Get enumerated values variant

pub fn is_16_bit(&self) -> bool

Checks if the value of the field is _16_BIT

pub fn is_8_bit(&self) -> bool

Checks if the value of the field is _8_BIT

pub fn is_18_bit(&self) -> bool

Checks if the value of the field is _18_BIT

pub fn is_24_bit(&self) -> bool

Checks if the value of the field is _24_BIT

impl R<u8, LCD_DATABUS_WIDTH_A>

pub fn variant(&self) -> LCD_DATABUS_WIDTH_A

Get enumerated values variant

pub fn is_16_bit(&self) -> bool

Checks if the value of the field is _16_BIT

pub fn is_8_bit(&self) -> bool

Checks if the value of the field is _8_BIT

pub fn is_18_bit(&self) -> bool

Checks if the value of the field is _18_BIT

pub fn is_24_bit(&self) -> bool

Checks if the value of the field is _24_BIT

impl R<u8, CSC_DATA_SWIZZLE_A>

pub fn variant(&self) -> CSC_DATA_SWIZZLE_A

Get enumerated values variant

pub fn is_no_swap(&self) -> bool

Checks if the value of the field is NO_SWAP

pub fn is_big_endian_swap(&self) -> bool

Checks if the value of the field is BIG_ENDIAN_SWAP

pub fn is_hwd_swap(&self) -> bool

Checks if the value of the field is HWD_SWAP

pub fn is_hwd_byte_swap(&self) -> bool

Checks if the value of the field is HWD_BYTE_SWAP

impl R<u8, INPUT_DATA_SWIZZLE_A>

pub fn variant(&self) -> INPUT_DATA_SWIZZLE_A

Get enumerated values variant

pub fn is_no_swap(&self) -> bool

Checks if the value of the field is NO_SWAP

pub fn is_big_endian_swap(&self) -> bool

Checks if the value of the field is BIG_ENDIAN_SWAP

pub fn is_hwd_swap(&self) -> bool

Checks if the value of the field is HWD_SWAP

pub fn is_hwd_byte_swap(&self) -> bool

Checks if the value of the field is HWD_BYTE_SWAP

impl R<bool, DATA_SHIFT_DIR_A>

pub fn variant(&self) -> DATA_SHIFT_DIR_A

Get enumerated values variant

pub fn is_txdata_shift_left(&self) -> bool

Checks if the value of the field is TXDATA_SHIFT_LEFT

pub fn is_txdata_shift_right(&self) -> bool

Checks if the value of the field is TXDATA_SHIFT_RIGHT

impl R<u32, Reg<u32, _CTRL_SET>>

pub fn run(&self) -> RUN_R

Bit 0 - When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display

pub fn data_format_24_bit(&self) -> DATA_FORMAT_24_BIT_R

Bit 1 - Used only when WORD_LENGTH = 3, i

pub fn data_format_18_bit(&self) -> DATA_FORMAT_18_BIT_R

Bit 2 - Used only when WORD_LENGTH = 2, i.e. 18-bit.

pub fn data_format_16_bit(&self) -> DATA_FORMAT_16_BIT_R

Bit 3 - When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format

pub fn master(&self) -> MASTER_R

Bit 5 - Set this bit to make the LCDIF act as a bus master

pub fn enable_pxp_handshake(&self) -> ENABLE_PXP_HANDSHAKE_R

Bit 6 - If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on

pub fn word_length(&self) -> WORD_LENGTH_R

Bits 8:9 - Input data format.

pub fn lcd_databus_width(&self) -> LCD_DATABUS_WIDTH_R

Bits 10:11 - LCD Data bus transfer width.

pub fn csc_data_swizzle(&self) -> CSC_DATA_SWIZZLE_R

Bits 12:13 - This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus

pub fn input_data_swizzle(&self) -> INPUT_DATA_SWIZZLE_R

Bits 14:15 - This field specifies how to swap the bytes fetched by the bus master interface

pub fn dotclk_mode(&self) -> DOTCLK_MODE_R

Bit 17 - Set this bit to 1 to make the hardware go into the DOTCLK mode, i

pub fn bypass_count(&self) -> BYPASS_COUNT_R

Bit 19 - When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out

pub fn shift_num_bits(&self) -> SHIFT_NUM_BITS_R

Bits 21:25 - The data to be transmitted is shifted left or right by this number of bits.

pub fn data_shift_dir(&self) -> DATA_SHIFT_DIR_R

Bit 26 - Use this bit to determine the direction of shift of transmit data.

pub fn clkgate(&self) -> CLKGATE_R

Bit 30 - This bit must be set to zero for normal operation

pub fn sftrst(&self) -> SFTRST_R

Bit 31 - This bit must be set to zero to enable normal operation of the LCDIF

impl R<bool, DATA_FORMAT_24_BIT_A>

pub fn variant(&self) -> DATA_FORMAT_24_BIT_A

Get enumerated values variant

pub fn is_all_24_bits_valid(&self) -> bool

Checks if the value of the field is ALL_24_BITS_VALID

pub fn is_drop_upper_2_bits_per_byte(&self) -> bool

Checks if the value of the field is DROP_UPPER_2_BITS_PER_BYTE

impl R<bool, DATA_FORMAT_18_BIT_A>

pub fn variant(&self) -> DATA_FORMAT_18_BIT_A

Get enumerated values variant

pub fn is_lower_18_bits_valid(&self) -> bool

Checks if the value of the field is LOWER_18_BITS_VALID

pub fn is_upper_18_bits_valid(&self) -> bool

Checks if the value of the field is UPPER_18_BITS_VALID

impl R<u8, WORD_LENGTH_A>

pub fn variant(&self) -> WORD_LENGTH_A

Get enumerated values variant

pub fn is_16_bit(&self) -> bool

Checks if the value of the field is _16_BIT

pub fn is_8_bit(&self) -> bool

Checks if the value of the field is _8_BIT

pub fn is_18_bit(&self) -> bool

Checks if the value of the field is _18_BIT

pub fn is_24_bit(&self) -> bool

Checks if the value of the field is _24_BIT

impl R<u8, LCD_DATABUS_WIDTH_A>

pub fn variant(&self) -> LCD_DATABUS_WIDTH_A

Get enumerated values variant

pub fn is_16_bit(&self) -> bool

Checks if the value of the field is _16_BIT

pub fn is_8_bit(&self) -> bool

Checks if the value of the field is _8_BIT

pub fn is_18_bit(&self) -> bool

Checks if the value of the field is _18_BIT

pub fn is_24_bit(&self) -> bool

Checks if the value of the field is _24_BIT

impl R<u8, CSC_DATA_SWIZZLE_A>

pub fn variant(&self) -> CSC_DATA_SWIZZLE_A

Get enumerated values variant

pub fn is_no_swap(&self) -> bool

Checks if the value of the field is NO_SWAP

pub fn is_big_endian_swap(&self) -> bool

Checks if the value of the field is BIG_ENDIAN_SWAP

pub fn is_hwd_swap(&self) -> bool

Checks if the value of the field is HWD_SWAP

pub fn is_hwd_byte_swap(&self) -> bool

Checks if the value of the field is HWD_BYTE_SWAP

impl R<u8, INPUT_DATA_SWIZZLE_A>

pub fn variant(&self) -> INPUT_DATA_SWIZZLE_A

Get enumerated values variant

pub fn is_no_swap(&self) -> bool

Checks if the value of the field is NO_SWAP

pub fn is_big_endian_swap(&self) -> bool

Checks if the value of the field is BIG_ENDIAN_SWAP

pub fn is_hwd_swap(&self) -> bool

Checks if the value of the field is HWD_SWAP

pub fn is_hwd_byte_swap(&self) -> bool

Checks if the value of the field is HWD_BYTE_SWAP

impl R<bool, DATA_SHIFT_DIR_A>

pub fn variant(&self) -> DATA_SHIFT_DIR_A

Get enumerated values variant

pub fn is_txdata_shift_left(&self) -> bool

Checks if the value of the field is TXDATA_SHIFT_LEFT

pub fn is_txdata_shift_right(&self) -> bool

Checks if the value of the field is TXDATA_SHIFT_RIGHT

impl R<u32, Reg<u32, _CTRL_CLR>>

pub fn run(&self) -> RUN_R

Bit 0 - When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display

pub fn data_format_24_bit(&self) -> DATA_FORMAT_24_BIT_R

Bit 1 - Used only when WORD_LENGTH = 3, i

pub fn data_format_18_bit(&self) -> DATA_FORMAT_18_BIT_R

Bit 2 - Used only when WORD_LENGTH = 2, i.e. 18-bit.

pub fn data_format_16_bit(&self) -> DATA_FORMAT_16_BIT_R

Bit 3 - When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format

pub fn master(&self) -> MASTER_R

Bit 5 - Set this bit to make the LCDIF act as a bus master

pub fn enable_pxp_handshake(&self) -> ENABLE_PXP_HANDSHAKE_R

Bit 6 - If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on

pub fn word_length(&self) -> WORD_LENGTH_R

Bits 8:9 - Input data format.

pub fn lcd_databus_width(&self) -> LCD_DATABUS_WIDTH_R

Bits 10:11 - LCD Data bus transfer width.

pub fn csc_data_swizzle(&self) -> CSC_DATA_SWIZZLE_R

Bits 12:13 - This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus

pub fn input_data_swizzle(&self) -> INPUT_DATA_SWIZZLE_R

Bits 14:15 - This field specifies how to swap the bytes fetched by the bus master interface

pub fn dotclk_mode(&self) -> DOTCLK_MODE_R

Bit 17 - Set this bit to 1 to make the hardware go into the DOTCLK mode, i

pub fn bypass_count(&self) -> BYPASS_COUNT_R

Bit 19 - When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out

pub fn shift_num_bits(&self) -> SHIFT_NUM_BITS_R

Bits 21:25 - The data to be transmitted is shifted left or right by this number of bits.

pub fn data_shift_dir(&self) -> DATA_SHIFT_DIR_R

Bit 26 - Use this bit to determine the direction of shift of transmit data.

pub fn clkgate(&self) -> CLKGATE_R

Bit 30 - This bit must be set to zero for normal operation

pub fn sftrst(&self) -> SFTRST_R

Bit 31 - This bit must be set to zero to enable normal operation of the LCDIF

impl R<bool, DATA_FORMAT_24_BIT_A>

pub fn variant(&self) -> DATA_FORMAT_24_BIT_A

Get enumerated values variant

pub fn is_all_24_bits_valid(&self) -> bool

Checks if the value of the field is ALL_24_BITS_VALID

pub fn is_drop_upper_2_bits_per_byte(&self) -> bool

Checks if the value of the field is DROP_UPPER_2_BITS_PER_BYTE

impl R<bool, DATA_FORMAT_18_BIT_A>

pub fn variant(&self) -> DATA_FORMAT_18_BIT_A

Get enumerated values variant

pub fn is_lower_18_bits_valid(&self) -> bool

Checks if the value of the field is LOWER_18_BITS_VALID

pub fn is_upper_18_bits_valid(&self) -> bool

Checks if the value of the field is UPPER_18_BITS_VALID

impl R<u8, WORD_LENGTH_A>

pub fn variant(&self) -> WORD_LENGTH_A

Get enumerated values variant

pub fn is_16_bit(&self) -> bool

Checks if the value of the field is _16_BIT

pub fn is_8_bit(&self) -> bool

Checks if the value of the field is _8_BIT

pub fn is_18_bit(&self) -> bool

Checks if the value of the field is _18_BIT

pub fn is_24_bit(&self) -> bool

Checks if the value of the field is _24_BIT

impl R<u8, LCD_DATABUS_WIDTH_A>

pub fn variant(&self) -> LCD_DATABUS_WIDTH_A

Get enumerated values variant

pub fn is_16_bit(&self) -> bool

Checks if the value of the field is _16_BIT

pub fn is_8_bit(&self) -> bool

Checks if the value of the field is _8_BIT

pub fn is_18_bit(&self) -> bool

Checks if the value of the field is _18_BIT

pub fn is_24_bit(&self) -> bool

Checks if the value of the field is _24_BIT

impl R<u8, CSC_DATA_SWIZZLE_A>

pub fn variant(&self) -> CSC_DATA_SWIZZLE_A

Get enumerated values variant

pub fn is_no_swap(&self) -> bool

Checks if the value of the field is NO_SWAP

pub fn is_big_endian_swap(&self) -> bool

Checks if the value of the field is BIG_ENDIAN_SWAP

pub fn is_hwd_swap(&self) -> bool

Checks if the value of the field is HWD_SWAP

pub fn is_hwd_byte_swap(&self) -> bool

Checks if the value of the field is HWD_BYTE_SWAP

impl R<u8, INPUT_DATA_SWIZZLE_A>

pub fn variant(&self) -> INPUT_DATA_SWIZZLE_A

Get enumerated values variant

pub fn is_no_swap(&self) -> bool

Checks if the value of the field is NO_SWAP

pub fn is_big_endian_swap(&self) -> bool

Checks if the value of the field is BIG_ENDIAN_SWAP

pub fn is_hwd_swap(&self) -> bool

Checks if the value of the field is HWD_SWAP

pub fn is_hwd_byte_swap(&self) -> bool

Checks if the value of the field is HWD_BYTE_SWAP

impl R<bool, DATA_SHIFT_DIR_A>

pub fn variant(&self) -> DATA_SHIFT_DIR_A

Get enumerated values variant

pub fn is_txdata_shift_left(&self) -> bool

Checks if the value of the field is TXDATA_SHIFT_LEFT

pub fn is_txdata_shift_right(&self) -> bool

Checks if the value of the field is TXDATA_SHIFT_RIGHT

impl R<u32, Reg<u32, _CTRL_TOG>>

pub fn run(&self) -> RUN_R

Bit 0 - When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display

pub fn data_format_24_bit(&self) -> DATA_FORMAT_24_BIT_R

Bit 1 - Used only when WORD_LENGTH = 3, i

pub fn data_format_18_bit(&self) -> DATA_FORMAT_18_BIT_R

Bit 2 - Used only when WORD_LENGTH = 2, i.e. 18-bit.

pub fn data_format_16_bit(&self) -> DATA_FORMAT_16_BIT_R

Bit 3 - When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format

pub fn master(&self) -> MASTER_R

Bit 5 - Set this bit to make the LCDIF act as a bus master

pub fn enable_pxp_handshake(&self) -> ENABLE_PXP_HANDSHAKE_R

Bit 6 - If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on

pub fn word_length(&self) -> WORD_LENGTH_R

Bits 8:9 - Input data format.

pub fn lcd_databus_width(&self) -> LCD_DATABUS_WIDTH_R

Bits 10:11 - LCD Data bus transfer width.

pub fn csc_data_swizzle(&self) -> CSC_DATA_SWIZZLE_R

Bits 12:13 - This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus

pub fn input_data_swizzle(&self) -> INPUT_DATA_SWIZZLE_R

Bits 14:15 - This field specifies how to swap the bytes fetched by the bus master interface

pub fn dotclk_mode(&self) -> DOTCLK_MODE_R

Bit 17 - Set this bit to 1 to make the hardware go into the DOTCLK mode, i

pub fn bypass_count(&self) -> BYPASS_COUNT_R

Bit 19 - When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out

pub fn shift_num_bits(&self) -> SHIFT_NUM_BITS_R

Bits 21:25 - The data to be transmitted is shifted left or right by this number of bits.

pub fn data_shift_dir(&self) -> DATA_SHIFT_DIR_R

Bit 26 - Use this bit to determine the direction of shift of transmit data.

pub fn clkgate(&self) -> CLKGATE_R

Bit 30 - This bit must be set to zero for normal operation

pub fn sftrst(&self) -> SFTRST_R

Bit 31 - This bit must be set to zero to enable normal operation of the LCDIF

impl R<bool, VSYNC_EDGE_IRQ_A>

pub fn variant(&self) -> VSYNC_EDGE_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, CUR_FRAME_DONE_IRQ_A>

pub fn variant(&self) -> CUR_FRAME_DONE_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, UNDERFLOW_IRQ_A>

pub fn variant(&self) -> UNDERFLOW_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, OVERFLOW_IRQ_A>

pub fn variant(&self) -> OVERFLOW_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, BM_ERROR_IRQ_A>

pub fn variant(&self) -> BM_ERROR_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<u32, Reg<u32, _CTRL1>>

pub fn vsync_edge_irq(&self) -> VSYNC_EDGE_IRQ_R

Bit 8 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn cur_frame_done_irq(&self) -> CUR_FRAME_DONE_IRQ_R

Bit 9 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn underflow_irq(&self) -> UNDERFLOW_IRQ_R

Bit 10 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn overflow_irq(&self) -> OVERFLOW_IRQ_R

Bit 11 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn vsync_edge_irq_en(&self) -> VSYNC_EDGE_IRQ_EN_R

Bit 12 - This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode

pub fn cur_frame_done_irq_en(&self) -> CUR_FRAME_DONE_IRQ_EN_R

Bit 13 - This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state

pub fn underflow_irq_en(&self) -> UNDERFLOW_IRQ_EN_R

Bit 14 - This bit is set to enable an underflow interrupt in the TXFIFO in the write mode.

pub fn overflow_irq_en(&self) -> OVERFLOW_IRQ_EN_R

Bit 15 - This bit is set to enable an overflow interrupt in the TXFIFO in the write mode.

pub fn byte_packing_format(&self) -> BYTE_PACKING_FORMAT_R

Bits 16:19 - This bitfield is used to show which data bytes in a 32-bit word are valid

pub fn irq_on_alternate_fields(&self) -> IRQ_ON_ALTERNATE_FIELDS_R

Bit 20 - If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field

pub fn fifo_clear(&self) -> FIFO_CLEAR_R

Bit 21 - Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO.

pub fn start_interlace_from_second_field(
    &self
) -> START_INTERLACE_FROM_SECOND_FIELD_R

Bit 22 - The default is to grab the odd lines first and then the even lines

pub fn interlace_fields(&self) -> INTERLACE_FIELDS_R

Bit 23 - Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field

pub fn recover_on_underflow(&self) -> RECOVER_ON_UNDERFLOW_R

Bit 24 - Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame

pub fn bm_error_irq(&self) -> BM_ERROR_IRQ_R

Bit 25 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn bm_error_irq_en(&self) -> BM_ERROR_IRQ_EN_R

Bit 26 - This bit is set to enable bus master error interrupt in the LCDIF master mode.

pub fn cs_out_select(&self) -> CS_OUT_SELECT_R

Bit 30 - This bit is CS0/CS1 valid select signals

pub fn image_data_select(&self) -> IMAGE_DATA_SELECT_R

Bit 31 - Command Mode MIPI image data select bit

impl R<bool, VSYNC_EDGE_IRQ_A>

pub fn variant(&self) -> VSYNC_EDGE_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, CUR_FRAME_DONE_IRQ_A>

pub fn variant(&self) -> CUR_FRAME_DONE_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, UNDERFLOW_IRQ_A>

pub fn variant(&self) -> UNDERFLOW_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, OVERFLOW_IRQ_A>

pub fn variant(&self) -> OVERFLOW_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, BM_ERROR_IRQ_A>

pub fn variant(&self) -> BM_ERROR_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<u32, Reg<u32, _CTRL1_SET>>

pub fn vsync_edge_irq(&self) -> VSYNC_EDGE_IRQ_R

Bit 8 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn cur_frame_done_irq(&self) -> CUR_FRAME_DONE_IRQ_R

Bit 9 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn underflow_irq(&self) -> UNDERFLOW_IRQ_R

Bit 10 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn overflow_irq(&self) -> OVERFLOW_IRQ_R

Bit 11 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn vsync_edge_irq_en(&self) -> VSYNC_EDGE_IRQ_EN_R

Bit 12 - This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode

pub fn cur_frame_done_irq_en(&self) -> CUR_FRAME_DONE_IRQ_EN_R

Bit 13 - This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state

pub fn underflow_irq_en(&self) -> UNDERFLOW_IRQ_EN_R

Bit 14 - This bit is set to enable an underflow interrupt in the TXFIFO in the write mode.

pub fn overflow_irq_en(&self) -> OVERFLOW_IRQ_EN_R

Bit 15 - This bit is set to enable an overflow interrupt in the TXFIFO in the write mode.

pub fn byte_packing_format(&self) -> BYTE_PACKING_FORMAT_R

Bits 16:19 - This bitfield is used to show which data bytes in a 32-bit word are valid

pub fn irq_on_alternate_fields(&self) -> IRQ_ON_ALTERNATE_FIELDS_R

Bit 20 - If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field

pub fn fifo_clear(&self) -> FIFO_CLEAR_R

Bit 21 - Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO.

pub fn start_interlace_from_second_field(
    &self
) -> START_INTERLACE_FROM_SECOND_FIELD_R

Bit 22 - The default is to grab the odd lines first and then the even lines

pub fn interlace_fields(&self) -> INTERLACE_FIELDS_R

Bit 23 - Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field

pub fn recover_on_underflow(&self) -> RECOVER_ON_UNDERFLOW_R

Bit 24 - Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame

pub fn bm_error_irq(&self) -> BM_ERROR_IRQ_R

Bit 25 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn bm_error_irq_en(&self) -> BM_ERROR_IRQ_EN_R

Bit 26 - This bit is set to enable bus master error interrupt in the LCDIF master mode.

pub fn cs_out_select(&self) -> CS_OUT_SELECT_R

Bit 30 - This bit is CS0/CS1 valid select signals

pub fn image_data_select(&self) -> IMAGE_DATA_SELECT_R

Bit 31 - Command Mode MIPI image data select bit

impl R<bool, VSYNC_EDGE_IRQ_A>

pub fn variant(&self) -> VSYNC_EDGE_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, CUR_FRAME_DONE_IRQ_A>

pub fn variant(&self) -> CUR_FRAME_DONE_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, UNDERFLOW_IRQ_A>

pub fn variant(&self) -> UNDERFLOW_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, OVERFLOW_IRQ_A>

pub fn variant(&self) -> OVERFLOW_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, BM_ERROR_IRQ_A>

pub fn variant(&self) -> BM_ERROR_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<u32, Reg<u32, _CTRL1_CLR>>

pub fn vsync_edge_irq(&self) -> VSYNC_EDGE_IRQ_R

Bit 8 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn cur_frame_done_irq(&self) -> CUR_FRAME_DONE_IRQ_R

Bit 9 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn underflow_irq(&self) -> UNDERFLOW_IRQ_R

Bit 10 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn overflow_irq(&self) -> OVERFLOW_IRQ_R

Bit 11 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn vsync_edge_irq_en(&self) -> VSYNC_EDGE_IRQ_EN_R

Bit 12 - This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode

pub fn cur_frame_done_irq_en(&self) -> CUR_FRAME_DONE_IRQ_EN_R

Bit 13 - This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state

pub fn underflow_irq_en(&self) -> UNDERFLOW_IRQ_EN_R

Bit 14 - This bit is set to enable an underflow interrupt in the TXFIFO in the write mode.

pub fn overflow_irq_en(&self) -> OVERFLOW_IRQ_EN_R

Bit 15 - This bit is set to enable an overflow interrupt in the TXFIFO in the write mode.

pub fn byte_packing_format(&self) -> BYTE_PACKING_FORMAT_R

Bits 16:19 - This bitfield is used to show which data bytes in a 32-bit word are valid

pub fn irq_on_alternate_fields(&self) -> IRQ_ON_ALTERNATE_FIELDS_R

Bit 20 - If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field

pub fn fifo_clear(&self) -> FIFO_CLEAR_R

Bit 21 - Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO.

pub fn start_interlace_from_second_field(
    &self
) -> START_INTERLACE_FROM_SECOND_FIELD_R

Bit 22 - The default is to grab the odd lines first and then the even lines

pub fn interlace_fields(&self) -> INTERLACE_FIELDS_R

Bit 23 - Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field

pub fn recover_on_underflow(&self) -> RECOVER_ON_UNDERFLOW_R

Bit 24 - Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame

pub fn bm_error_irq(&self) -> BM_ERROR_IRQ_R

Bit 25 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn bm_error_irq_en(&self) -> BM_ERROR_IRQ_EN_R

Bit 26 - This bit is set to enable bus master error interrupt in the LCDIF master mode.

pub fn cs_out_select(&self) -> CS_OUT_SELECT_R

Bit 30 - This bit is CS0/CS1 valid select signals

pub fn image_data_select(&self) -> IMAGE_DATA_SELECT_R

Bit 31 - Command Mode MIPI image data select bit

impl R<bool, VSYNC_EDGE_IRQ_A>

pub fn variant(&self) -> VSYNC_EDGE_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, CUR_FRAME_DONE_IRQ_A>

pub fn variant(&self) -> CUR_FRAME_DONE_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, UNDERFLOW_IRQ_A>

pub fn variant(&self) -> UNDERFLOW_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, OVERFLOW_IRQ_A>

pub fn variant(&self) -> OVERFLOW_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<bool, BM_ERROR_IRQ_A>

pub fn variant(&self) -> BM_ERROR_IRQ_A

Get enumerated values variant

pub fn is_no_request(&self) -> bool

Checks if the value of the field is NO_REQUEST

pub fn is_request(&self) -> bool

Checks if the value of the field is REQUEST

impl R<u32, Reg<u32, _CTRL1_TOG>>

pub fn vsync_edge_irq(&self) -> VSYNC_EDGE_IRQ_R

Bit 8 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn cur_frame_done_irq(&self) -> CUR_FRAME_DONE_IRQ_R

Bit 9 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn underflow_irq(&self) -> UNDERFLOW_IRQ_R

Bit 10 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn overflow_irq(&self) -> OVERFLOW_IRQ_R

Bit 11 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn vsync_edge_irq_en(&self) -> VSYNC_EDGE_IRQ_EN_R

Bit 12 - This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode

pub fn cur_frame_done_irq_en(&self) -> CUR_FRAME_DONE_IRQ_EN_R

Bit 13 - This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state

pub fn underflow_irq_en(&self) -> UNDERFLOW_IRQ_EN_R

Bit 14 - This bit is set to enable an underflow interrupt in the TXFIFO in the write mode.

pub fn overflow_irq_en(&self) -> OVERFLOW_IRQ_EN_R

Bit 15 - This bit is set to enable an overflow interrupt in the TXFIFO in the write mode.

pub fn byte_packing_format(&self) -> BYTE_PACKING_FORMAT_R

Bits 16:19 - This bitfield is used to show which data bytes in a 32-bit word are valid

pub fn irq_on_alternate_fields(&self) -> IRQ_ON_ALTERNATE_FIELDS_R

Bit 20 - If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field

pub fn fifo_clear(&self) -> FIFO_CLEAR_R

Bit 21 - Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO.

pub fn start_interlace_from_second_field(
    &self
) -> START_INTERLACE_FROM_SECOND_FIELD_R

Bit 22 - The default is to grab the odd lines first and then the even lines

pub fn interlace_fields(&self) -> INTERLACE_FIELDS_R

Bit 23 - Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field

pub fn recover_on_underflow(&self) -> RECOVER_ON_UNDERFLOW_R

Bit 24 - Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame

pub fn bm_error_irq(&self) -> BM_ERROR_IRQ_R

Bit 25 - This bit is set to indicate that an interrupt is requested by the LCDIF block

pub fn bm_error_irq_en(&self) -> BM_ERROR_IRQ_EN_R

Bit 26 - This bit is set to enable bus master error interrupt in the LCDIF master mode.

pub fn cs_out_select(&self) -> CS_OUT_SELECT_R

Bit 30 - This bit is CS0/CS1 valid select signals

pub fn image_data_select(&self) -> IMAGE_DATA_SELECT_R

Bit 31 - Command Mode MIPI image data select bit

impl R<u8, EVEN_LINE_PATTERN_A>

pub fn variant(&self) -> Variant<u8, EVEN_LINE_PATTERN_A>

Get enumerated values variant

pub fn is_rgb(&self) -> bool

Checks if the value of the field is RGB

pub fn is_rbg(&self) -> bool

Checks if the value of the field is RBG

pub fn is_gbr(&self) -> bool

Checks if the value of the field is GBR

pub fn is_grb(&self) -> bool

Checks if the value of the field is GRB

pub fn is_brg(&self) -> bool

Checks if the value of the field is BRG

pub fn is_bgr(&self) -> bool

Checks if the value of the field is BGR

impl R<u8, ODD_LINE_PATTERN_A>

pub fn variant(&self) -> Variant<u8, ODD_LINE_PATTERN_A>

Get enumerated values variant

pub fn is_rgb(&self) -> bool

Checks if the value of the field is RGB

pub fn is_rbg(&self) -> bool

Checks if the value of the field is RBG

pub fn is_gbr(&self) -> bool

Checks if the value of the field is GBR

pub fn is_grb(&self) -> bool

Checks if the value of the field is GRB

pub fn is_brg(&self) -> bool

Checks if the value of the field is BRG

pub fn is_bgr(&self) -> bool

Checks if the value of the field is BGR

impl R<u8, OUTSTANDING_REQS_A>

pub fn variant(&self) -> Variant<u8, OUTSTANDING_REQS_A>

Get enumerated values variant

pub fn is_req_1(&self) -> bool

Checks if the value of the field is REQ_1

pub fn is_req_2(&self) -> bool

Checks if the value of the field is REQ_2

pub fn is_req_4(&self) -> bool

Checks if the value of the field is REQ_4

pub fn is_req_8(&self) -> bool

Checks if the value of the field is REQ_8

pub fn is_req_16(&self) -> bool

Checks if the value of the field is REQ_16

impl R<u32, Reg<u32, _CTRL2>>

pub fn even_line_pattern(&self) -> EVEN_LINE_PATTERN_R

Bits 12:14 - This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,

pub fn odd_line_pattern(&self) -> ODD_LINE_PATTERN_R

Bits 16:18 - This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,

pub fn burst_len_8(&self) -> BURST_LEN_8_R

Bit 20 - By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)

pub fn outstanding_reqs(&self) -> OUTSTANDING_REQS_R

Bits 21:23 - This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master

impl R<u8, EVEN_LINE_PATTERN_A>

pub fn variant(&self) -> Variant<u8, EVEN_LINE_PATTERN_A>

Get enumerated values variant

pub fn is_rgb(&self) -> bool

Checks if the value of the field is RGB

pub fn is_rbg(&self) -> bool

Checks if the value of the field is RBG

pub fn is_gbr(&self) -> bool

Checks if the value of the field is GBR

pub fn is_grb(&self) -> bool

Checks if the value of the field is GRB

pub fn is_brg(&self) -> bool

Checks if the value of the field is BRG

pub fn is_bgr(&self) -> bool

Checks if the value of the field is BGR

impl R<u8, ODD_LINE_PATTERN_A>

pub fn variant(&self) -> Variant<u8, ODD_LINE_PATTERN_A>

Get enumerated values variant

pub fn is_rgb(&self) -> bool

Checks if the value of the field is RGB

pub fn is_rbg(&self) -> bool

Checks if the value of the field is RBG

pub fn is_gbr(&self) -> bool

Checks if the value of the field is GBR

pub fn is_grb(&self) -> bool

Checks if the value of the field is GRB

pub fn is_brg(&self) -> bool

Checks if the value of the field is BRG

pub fn is_bgr(&self) -> bool

Checks if the value of the field is BGR

impl R<u8, OUTSTANDING_REQS_A>

pub fn variant(&self) -> Variant<u8, OUTSTANDING_REQS_A>

Get enumerated values variant

pub fn is_req_1(&self) -> bool

Checks if the value of the field is REQ_1

pub fn is_req_2(&self) -> bool

Checks if the value of the field is REQ_2

pub fn is_req_4(&self) -> bool

Checks if the value of the field is REQ_4

pub fn is_req_8(&self) -> bool

Checks if the value of the field is REQ_8

pub fn is_req_16(&self) -> bool

Checks if the value of the field is REQ_16

impl R<u32, Reg<u32, _CTRL2_SET>>

pub fn even_line_pattern(&self) -> EVEN_LINE_PATTERN_R

Bits 12:14 - This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,

pub fn odd_line_pattern(&self) -> ODD_LINE_PATTERN_R

Bits 16:18 - This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,

pub fn burst_len_8(&self) -> BURST_LEN_8_R

Bit 20 - By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)

pub fn outstanding_reqs(&self) -> OUTSTANDING_REQS_R

Bits 21:23 - This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master

impl R<u8, EVEN_LINE_PATTERN_A>

pub fn variant(&self) -> Variant<u8, EVEN_LINE_PATTERN_A>

Get enumerated values variant

pub fn is_rgb(&self) -> bool

Checks if the value of the field is RGB

pub fn is_rbg(&self) -> bool

Checks if the value of the field is RBG

pub fn is_gbr(&self) -> bool

Checks if the value of the field is GBR

pub fn is_grb(&self) -> bool

Checks if the value of the field is GRB

pub fn is_brg(&self) -> bool

Checks if the value of the field is BRG

pub fn is_bgr(&self) -> bool

Checks if the value of the field is BGR

impl R<u8, ODD_LINE_PATTERN_A>

pub fn variant(&self) -> Variant<u8, ODD_LINE_PATTERN_A>

Get enumerated values variant

pub fn is_rgb(&self) -> bool

Checks if the value of the field is RGB

pub fn is_rbg(&self) -> bool

Checks if the value of the field is RBG

pub fn is_gbr(&self) -> bool

Checks if the value of the field is GBR

pub fn is_grb(&self) -> bool

Checks if the value of the field is GRB

pub fn is_brg(&self) -> bool

Checks if the value of the field is BRG

pub fn is_bgr(&self) -> bool

Checks if the value of the field is BGR

impl R<u8, OUTSTANDING_REQS_A>

pub fn variant(&self) -> Variant<u8, OUTSTANDING_REQS_A>

Get enumerated values variant

pub fn is_req_1(&self) -> bool

Checks if the value of the field is REQ_1

pub fn is_req_2(&self) -> bool

Checks if the value of the field is REQ_2

pub fn is_req_4(&self) -> bool

Checks if the value of the field is REQ_4

pub fn is_req_8(&self) -> bool

Checks if the value of the field is REQ_8

pub fn is_req_16(&self) -> bool

Checks if the value of the field is REQ_16

impl R<u32, Reg<u32, _CTRL2_CLR>>

pub fn even_line_pattern(&self) -> EVEN_LINE_PATTERN_R

Bits 12:14 - This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,

pub fn odd_line_pattern(&self) -> ODD_LINE_PATTERN_R

Bits 16:18 - This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,

pub fn burst_len_8(&self) -> BURST_LEN_8_R

Bit 20 - By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)

pub fn outstanding_reqs(&self) -> OUTSTANDING_REQS_R

Bits 21:23 - This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master

impl R<u8, EVEN_LINE_PATTERN_A>

pub fn variant(&self) -> Variant<u8, EVEN_LINE_PATTERN_A>

Get enumerated values variant

pub fn is_rgb(&self) -> bool

Checks if the value of the field is RGB

pub fn is_rbg(&self) -> bool

Checks if the value of the field is RBG

pub fn is_gbr(&self) -> bool

Checks if the value of the field is GBR

pub fn is_grb(&self) -> bool

Checks if the value of the field is GRB

pub fn is_brg(&self) -> bool

Checks if the value of the field is BRG

pub fn is_bgr(&self) -> bool

Checks if the value of the field is BGR

impl R<u8, ODD_LINE_PATTERN_A>

pub fn variant(&self) -> Variant<u8, ODD_LINE_PATTERN_A>

Get enumerated values variant

pub fn is_rgb(&self) -> bool

Checks if the value of the field is RGB

pub fn is_rbg(&self) -> bool

Checks if the value of the field is RBG

pub fn is_gbr(&self) -> bool

Checks if the value of the field is GBR

pub fn is_grb(&self) -> bool

Checks if the value of the field is GRB

pub fn is_brg(&self) -> bool

Checks if the value of the field is BRG

pub fn is_bgr(&self) -> bool

Checks if the value of the field is BGR

impl R<u8, OUTSTANDING_REQS_A>

pub fn variant(&self) -> Variant<u8, OUTSTANDING_REQS_A>

Get enumerated values variant

pub fn is_req_1(&self) -> bool

Checks if the value of the field is REQ_1

pub fn is_req_2(&self) -> bool

Checks if the value of the field is REQ_2

pub fn is_req_4(&self) -> bool

Checks if the value of the field is REQ_4

pub fn is_req_8(&self) -> bool

Checks if the value of the field is REQ_8

pub fn is_req_16(&self) -> bool

Checks if the value of the field is REQ_16

impl R<u32, Reg<u32, _CTRL2_TOG>>

pub fn even_line_pattern(&self) -> EVEN_LINE_PATTERN_R

Bits 12:14 - This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,

pub fn odd_line_pattern(&self) -> ODD_LINE_PATTERN_R

Bits 16:18 - This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,

pub fn burst_len_8(&self) -> BURST_LEN_8_R

Bit 20 - By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)

pub fn outstanding_reqs(&self) -> OUTSTANDING_REQS_R

Bits 21:23 - This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master

impl R<u32, Reg<u32, _TRANSFER_COUNT>>

pub fn h_count(&self) -> H_COUNT_R

Bits 0:15 - Total valid data (pixels) in each horizontal line

pub fn v_count(&self) -> V_COUNT_R

Bits 16:31 - Number of horizontal lines per frame which contain valid data

impl R<u32, Reg<u32, _CUR_BUF>>

pub fn addr(&self) -> ADDR_R

Bits 0:31 - Address of the current frame being transmitted by LCDIF.

impl R<u32, Reg<u32, _NEXT_BUF>>

pub fn addr(&self) -> ADDR_R

Bits 0:31 - Address of the next frame that will be transmitted by LCDIF.

impl R<u32, Reg<u32, _VDCTRL0>>

pub fn vsync_pulse_width(&self) -> VSYNC_PULSE_WIDTH_R

Bits 0:17 - Number of units for which VSYNC signal is active

pub fn half_line_mode(&self) -> HALF_LINE_MODE_R

Bit 18 - When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line

pub fn half_line(&self) -> HALF_LINE_R

Bit 19 - Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i

pub fn vsync_pulse_width_unit(&self) -> VSYNC_PULSE_WIDTH_UNIT_R

Bit 20 - Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn vsync_period_unit(&self) -> VSYNC_PERIOD_UNIT_R

Bit 21 - Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn enable_pol(&self) -> ENABLE_POL_R

Bit 24 - Default 0 active low during valid data transfer on each horizontal line.

pub fn dotclk_pol(&self) -> DOTCLK_POL_R

Bit 25 - Default is data launched at negative edge of DOTCLK and captured at positive edge

pub fn hsync_pol(&self) -> HSYNC_POL_R

Bit 26 - Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period

pub fn vsync_pol(&self) -> VSYNC_POL_R

Bit 27 - Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period

pub fn enable_present(&self) -> ENABLE_PRESENT_R

Bit 28 - Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK

impl R<u32, Reg<u32, _VDCTRL0_SET>>

pub fn vsync_pulse_width(&self) -> VSYNC_PULSE_WIDTH_R

Bits 0:17 - Number of units for which VSYNC signal is active

pub fn half_line_mode(&self) -> HALF_LINE_MODE_R

Bit 18 - When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line

pub fn half_line(&self) -> HALF_LINE_R

Bit 19 - Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i

pub fn vsync_pulse_width_unit(&self) -> VSYNC_PULSE_WIDTH_UNIT_R

Bit 20 - Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn vsync_period_unit(&self) -> VSYNC_PERIOD_UNIT_R

Bit 21 - Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn enable_pol(&self) -> ENABLE_POL_R

Bit 24 - Default 0 active low during valid data transfer on each horizontal line.

pub fn dotclk_pol(&self) -> DOTCLK_POL_R

Bit 25 - Default is data launched at negative edge of DOTCLK and captured at positive edge

pub fn hsync_pol(&self) -> HSYNC_POL_R

Bit 26 - Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period

pub fn vsync_pol(&self) -> VSYNC_POL_R

Bit 27 - Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period

pub fn enable_present(&self) -> ENABLE_PRESENT_R

Bit 28 - Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK

impl R<u32, Reg<u32, _VDCTRL0_CLR>>

pub fn vsync_pulse_width(&self) -> VSYNC_PULSE_WIDTH_R

Bits 0:17 - Number of units for which VSYNC signal is active

pub fn half_line_mode(&self) -> HALF_LINE_MODE_R

Bit 18 - When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line

pub fn half_line(&self) -> HALF_LINE_R

Bit 19 - Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i

pub fn vsync_pulse_width_unit(&self) -> VSYNC_PULSE_WIDTH_UNIT_R

Bit 20 - Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn vsync_period_unit(&self) -> VSYNC_PERIOD_UNIT_R

Bit 21 - Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn enable_pol(&self) -> ENABLE_POL_R

Bit 24 - Default 0 active low during valid data transfer on each horizontal line.

pub fn dotclk_pol(&self) -> DOTCLK_POL_R

Bit 25 - Default is data launched at negative edge of DOTCLK and captured at positive edge

pub fn hsync_pol(&self) -> HSYNC_POL_R

Bit 26 - Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period

pub fn vsync_pol(&self) -> VSYNC_POL_R

Bit 27 - Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period

pub fn enable_present(&self) -> ENABLE_PRESENT_R

Bit 28 - Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK

impl R<u32, Reg<u32, _VDCTRL0_TOG>>

pub fn vsync_pulse_width(&self) -> VSYNC_PULSE_WIDTH_R

Bits 0:17 - Number of units for which VSYNC signal is active

pub fn half_line_mode(&self) -> HALF_LINE_MODE_R

Bit 18 - When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line

pub fn half_line(&self) -> HALF_LINE_R

Bit 19 - Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i

pub fn vsync_pulse_width_unit(&self) -> VSYNC_PULSE_WIDTH_UNIT_R

Bit 20 - Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn vsync_period_unit(&self) -> VSYNC_PERIOD_UNIT_R

Bit 21 - Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn enable_pol(&self) -> ENABLE_POL_R

Bit 24 - Default 0 active low during valid data transfer on each horizontal line.

pub fn dotclk_pol(&self) -> DOTCLK_POL_R

Bit 25 - Default is data launched at negative edge of DOTCLK and captured at positive edge

pub fn hsync_pol(&self) -> HSYNC_POL_R

Bit 26 - Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period

pub fn vsync_pol(&self) -> VSYNC_POL_R

Bit 27 - Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period

pub fn enable_present(&self) -> ENABLE_PRESENT_R

Bit 28 - Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK

impl R<u32, Reg<u32, _VDCTRL1>>

pub fn vsync_period(&self) -> VSYNC_PERIOD_R

Bits 0:31 - Total number of units between two positive or two negative edges of the VSYNC signal

impl R<u32, Reg<u32, _VDCTRL2>>

pub fn hsync_period(&self) -> HSYNC_PERIOD_R

Bits 0:17 - Total number of DISPLAY CLOCK (pix_clk) cycles between two positive or two negative edges of the HSYNC signal

pub fn hsync_pulse_width(&self) -> HSYNC_PULSE_WIDTH_R

Bits 18:31 - Number of DISPLAY CLOCK (pix_clk) cycles for which HSYNC signal is active.

impl R<u32, Reg<u32, _VDCTRL3>>

pub fn vertical_wait_cnt(&self) -> VERTICAL_WAIT_CNT_R

Bits 0:15 - In the VSYNC interface mode, wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set

pub fn horizontal_wait_cnt(&self) -> HORIZONTAL_WAIT_CNT_R

Bits 16:27 - In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins

pub fn vsync_only(&self) -> VSYNC_ONLY_R

Bit 28 - This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation.

pub fn mux_sync_signals(&self) -> MUX_SYNC_SIGNALS_R

Bit 29 - When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins

impl R<u32, Reg<u32, _VDCTRL4>>

pub fn dotclk_h_valid_data_cnt(&self) -> DOTCLK_H_VALID_DATA_CNT_R

Bits 0:17 - Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode

pub fn sync_signals_on(&self) -> SYNC_SIGNALS_ON_R

Bit 18 - Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end

pub fn dotclk_dly_sel(&self) -> DOTCLK_DLY_SEL_R

Bits 29:31 - This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin

impl R<u32, Reg<u32, _BM_ERROR_STAT>>

pub fn addr(&self) -> ADDR_R

Bits 0:31 - Virtual address at which bus master error occurred.

impl R<u32, Reg<u32, _CRC_STAT>>

pub fn crc_value(&self) -> CRC_VALUE_R

Bits 0:31 - Calculated CRC value.

impl R<u32, Reg<u32, _STAT>>

pub fn lfifo_count(&self) -> LFIFO_COUNT_R

Bits 0:8 - Read only view of the current count in Latency buffer (LFIFO).

pub fn txfifo_empty(&self) -> TXFIFO_EMPTY_R

Bit 26 - Read only view of the signals that indicates LCD TXFIFO is empty.

pub fn txfifo_full(&self) -> TXFIFO_FULL_R

Bit 27 - Read only view of the signals that indicates LCD TXFIFO is full.

pub fn lfifo_empty(&self) -> LFIFO_EMPTY_R

Bit 28 - Read only view of the signals that indicates LCD LFIFO is empty.

pub fn lfifo_full(&self) -> LFIFO_FULL_R

Bit 29 - Read only view of the signals that indicates LCD LFIFO is full.

pub fn dma_req(&self) -> DMA_REQ_R

Bit 30 - Reflects the current state of the DMA Request line for the LCDIF

pub fn present(&self) -> PRESENT_R

Bit 31 - 0: LCDIF not present on this product 1: LCDIF is present.

impl R<u32, Reg<u32, _PIGEONCTRL0>>

pub fn fd_period(&self) -> FD_PERIOD_R

Bits 0:11 - Period of line counter during FD phase

pub fn ld_period(&self) -> LD_PERIOD_R

Bits 16:27 - Period of pclk counter during LD phase

impl R<u32, Reg<u32, _PIGEONCTRL0_SET>>

pub fn fd_period(&self) -> FD_PERIOD_R

Bits 0:11 - Period of line counter during FD phase

pub fn ld_period(&self) -> LD_PERIOD_R

Bits 16:27 - Period of pclk counter during LD phase

impl R<u32, Reg<u32, _PIGEONCTRL0_CLR>>

pub fn fd_period(&self) -> FD_PERIOD_R

Bits 0:11 - Period of line counter during FD phase

pub fn ld_period(&self) -> LD_PERIOD_R

Bits 16:27 - Period of pclk counter during LD phase

impl R<u32, Reg<u32, _PIGEONCTRL0_TOG>>

pub fn fd_period(&self) -> FD_PERIOD_R

Bits 0:11 - Period of line counter during FD phase

pub fn ld_period(&self) -> LD_PERIOD_R

Bits 16:27 - Period of pclk counter during LD phase

impl R<u32, Reg<u32, _PIGEONCTRL1>>

pub fn frame_cnt_period(&self) -> FRAME_CNT_PERIOD_R

Bits 0:11 - Period of frame counter

pub fn frame_cnt_cycles(&self) -> FRAME_CNT_CYCLES_R

Bits 16:27 - Max cycles of frame counter

impl R<u32, Reg<u32, _PIGEONCTRL1_SET>>

pub fn frame_cnt_period(&self) -> FRAME_CNT_PERIOD_R

Bits 0:11 - Period of frame counter

pub fn frame_cnt_cycles(&self) -> FRAME_CNT_CYCLES_R

Bits 16:27 - Max cycles of frame counter

impl R<u32, Reg<u32, _PIGEONCTRL1_CLR>>

pub fn frame_cnt_period(&self) -> FRAME_CNT_PERIOD_R

Bits 0:11 - Period of frame counter

pub fn frame_cnt_cycles(&self) -> FRAME_CNT_CYCLES_R

Bits 16:27 - Max cycles of frame counter

impl R<u32, Reg<u32, _PIGEONCTRL1_TOG>>

pub fn frame_cnt_period(&self) -> FRAME_CNT_PERIOD_R

Bits 0:11 - Period of frame counter

pub fn frame_cnt_cycles(&self) -> FRAME_CNT_CYCLES_R

Bits 16:27 - Max cycles of frame counter

impl R<u32, Reg<u32, _PIGEONCTRL2>>

pub fn pigeon_data_en(&self) -> PIGEON_DATA_EN_R

Bit 0 - Pigeon mode data enable

pub fn pigeon_clk_gate(&self) -> PIGEON_CLK_GATE_R

Bit 1 - Pigeon mode dot clock gate enable

impl R<u32, Reg<u32, _PIGEONCTRL2_SET>>

pub fn pigeon_data_en(&self) -> PIGEON_DATA_EN_R

Bit 0 - Pigeon mode data enable

pub fn pigeon_clk_gate(&self) -> PIGEON_CLK_GATE_R

Bit 1 - Pigeon mode dot clock gate enable

impl R<u32, Reg<u32, _PIGEONCTRL2_CLR>>

pub fn pigeon_data_en(&self) -> PIGEON_DATA_EN_R

Bit 0 - Pigeon mode data enable

pub fn pigeon_clk_gate(&self) -> PIGEON_CLK_GATE_R

Bit 1 - Pigeon mode dot clock gate enable

impl R<u32, Reg<u32, _PIGEONCTRL2_TOG>>

pub fn pigeon_data_en(&self) -> PIGEON_DATA_EN_R

Bit 0 - Pigeon mode data enable

pub fn pigeon_clk_gate(&self) -> PIGEON_CLK_GATE_R

Bit 1 - Pigeon mode dot clock gate enable

impl R<bool, POL_A>

pub fn variant(&self) -> POL_A

Get enumerated values variant

pub fn is_active_high(&self) -> bool

Checks if the value of the field is ACTIVE_HIGH

pub fn is_active_low(&self) -> bool

Checks if the value of the field is ACTIVE_LOW

impl R<u8, INC_SEL_A>

pub fn variant(&self) -> INC_SEL_A

Get enumerated values variant

pub fn is_pclk(&self) -> bool

Checks if the value of the field is PCLK

pub fn is_line(&self) -> bool

Checks if the value of the field is LINE

pub fn is_frame(&self) -> bool

Checks if the value of the field is FRAME

pub fn is_sig_another(&self) -> bool

Checks if the value of the field is SIG_ANOTHER

impl R<u8, MASK_CNT_SEL_A>

pub fn variant(&self) -> Variant<u8, MASK_CNT_SEL_A>

Get enumerated values variant

pub fn is_hstate_cnt(&self) -> bool

Checks if the value of the field is HSTATE_CNT

pub fn is_hstate_cycle(&self) -> bool

Checks if the value of the field is HSTATE_CYCLE

pub fn is_vstate_cnt(&self) -> bool

Checks if the value of the field is VSTATE_CNT

pub fn is_vstate_cycle(&self) -> bool

Checks if the value of the field is VSTATE_CYCLE

pub fn is_frame_cnt(&self) -> bool

Checks if the value of the field is FRAME_CNT

pub fn is_frame_cycle(&self) -> bool

Checks if the value of the field is FRAME_CYCLE

pub fn is_hcnt(&self) -> bool

Checks if the value of the field is HCNT

pub fn is_vcnt(&self) -> bool

Checks if the value of the field is VCNT

impl R<u8, STATE_MASK_A>

pub fn variant(&self) -> Variant<u8, STATE_MASK_A>

Get enumerated values variant

pub fn is_fs(&self) -> bool

Checks if the value of the field is FS

pub fn is_fb(&self) -> bool

Checks if the value of the field is FB

pub fn is_fd(&self) -> bool

Checks if the value of the field is FD

pub fn is_fe(&self) -> bool

Checks if the value of the field is FE

pub fn is_ls(&self) -> bool

Checks if the value of the field is LS

pub fn is_lb(&self) -> bool

Checks if the value of the field is LB

pub fn is_ld(&self) -> bool

Checks if the value of the field is LD

pub fn is_le(&self) -> bool

Checks if the value of the field is LE

impl R<u32, Reg<u32, _PIGEON_0_0>>

pub fn en(&self) -> EN_R

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&self) -> POL_R

Bit 1 - Polarity of signal output

pub fn inc_sel(&self) -> INC_SEL_R

Bits 2:3 - Event to incrment local counter

pub fn offset(&self) -> OFFSET_R

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&self) -> MASK_CNT_SEL_R

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&self) -> MASK_CNT_R

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&self) -> STATE_MASK_R

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl R<u16, SET_CNT_A>

pub fn variant(&self) -> Variant<u16, SET_CNT_A>

Get enumerated values variant

pub fn is_start_active(&self) -> bool

Checks if the value of the field is START_ACTIVE

impl R<u16, CLR_CNT_A>

pub fn variant(&self) -> Variant<u16, CLR_CNT_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_0_1>>

pub fn set_cnt(&self) -> SET_CNT_R

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&self) -> CLR_CNT_R

Bits 16:31 - Deassert signal output when counter match this value

impl R<u8, SIG_LOGIC_A>

pub fn variant(&self) -> Variant<u8, SIG_LOGIC_A>

Get enumerated values variant

pub fn is_dis(&self) -> bool

Checks if the value of the field is DIS

pub fn is_and(&self) -> bool

Checks if the value of the field is AND

pub fn is_or(&self) -> bool

Checks if the value of the field is OR

pub fn is_mask(&self) -> bool

Checks if the value of the field is MASK

impl R<u8, SIG_ANOTHER_A>

pub fn variant(&self) -> Variant<u8, SIG_ANOTHER_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_0_2>>

pub fn sig_logic(&self) -> SIG_LOGIC_R

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&self) -> SIG_ANOTHER_R

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl R<bool, POL_A>

pub fn variant(&self) -> POL_A

Get enumerated values variant

pub fn is_active_high(&self) -> bool

Checks if the value of the field is ACTIVE_HIGH

pub fn is_active_low(&self) -> bool

Checks if the value of the field is ACTIVE_LOW

impl R<u8, INC_SEL_A>

pub fn variant(&self) -> INC_SEL_A

Get enumerated values variant

pub fn is_pclk(&self) -> bool

Checks if the value of the field is PCLK

pub fn is_line(&self) -> bool

Checks if the value of the field is LINE

pub fn is_frame(&self) -> bool

Checks if the value of the field is FRAME

pub fn is_sig_another(&self) -> bool

Checks if the value of the field is SIG_ANOTHER

impl R<u8, MASK_CNT_SEL_A>

pub fn variant(&self) -> Variant<u8, MASK_CNT_SEL_A>

Get enumerated values variant

pub fn is_hstate_cnt(&self) -> bool

Checks if the value of the field is HSTATE_CNT

pub fn is_hstate_cycle(&self) -> bool

Checks if the value of the field is HSTATE_CYCLE

pub fn is_vstate_cnt(&self) -> bool

Checks if the value of the field is VSTATE_CNT

pub fn is_vstate_cycle(&self) -> bool

Checks if the value of the field is VSTATE_CYCLE

pub fn is_frame_cnt(&self) -> bool

Checks if the value of the field is FRAME_CNT

pub fn is_frame_cycle(&self) -> bool

Checks if the value of the field is FRAME_CYCLE

pub fn is_hcnt(&self) -> bool

Checks if the value of the field is HCNT

pub fn is_vcnt(&self) -> bool

Checks if the value of the field is VCNT

impl R<u8, STATE_MASK_A>

pub fn variant(&self) -> Variant<u8, STATE_MASK_A>

Get enumerated values variant

pub fn is_fs(&self) -> bool

Checks if the value of the field is FS

pub fn is_fb(&self) -> bool

Checks if the value of the field is FB

pub fn is_fd(&self) -> bool

Checks if the value of the field is FD

pub fn is_fe(&self) -> bool

Checks if the value of the field is FE

pub fn is_ls(&self) -> bool

Checks if the value of the field is LS

pub fn is_lb(&self) -> bool

Checks if the value of the field is LB

pub fn is_ld(&self) -> bool

Checks if the value of the field is LD

pub fn is_le(&self) -> bool

Checks if the value of the field is LE

impl R<u32, Reg<u32, _PIGEON_1_0>>

pub fn en(&self) -> EN_R

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&self) -> POL_R

Bit 1 - Polarity of signal output

pub fn inc_sel(&self) -> INC_SEL_R

Bits 2:3 - Event to incrment local counter

pub fn offset(&self) -> OFFSET_R

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&self) -> MASK_CNT_SEL_R

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&self) -> MASK_CNT_R

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&self) -> STATE_MASK_R

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl R<u16, SET_CNT_A>

pub fn variant(&self) -> Variant<u16, SET_CNT_A>

Get enumerated values variant

pub fn is_start_active(&self) -> bool

Checks if the value of the field is START_ACTIVE

impl R<u16, CLR_CNT_A>

pub fn variant(&self) -> Variant<u16, CLR_CNT_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_1_1>>

pub fn set_cnt(&self) -> SET_CNT_R

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&self) -> CLR_CNT_R

Bits 16:31 - Deassert signal output when counter match this value

impl R<u8, SIG_LOGIC_A>

pub fn variant(&self) -> Variant<u8, SIG_LOGIC_A>

Get enumerated values variant

pub fn is_dis(&self) -> bool

Checks if the value of the field is DIS

pub fn is_and(&self) -> bool

Checks if the value of the field is AND

pub fn is_or(&self) -> bool

Checks if the value of the field is OR

pub fn is_mask(&self) -> bool

Checks if the value of the field is MASK

impl R<u8, SIG_ANOTHER_A>

pub fn variant(&self) -> Variant<u8, SIG_ANOTHER_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_1_2>>

pub fn sig_logic(&self) -> SIG_LOGIC_R

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&self) -> SIG_ANOTHER_R

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl R<bool, POL_A>

pub fn variant(&self) -> POL_A

Get enumerated values variant

pub fn is_active_high(&self) -> bool

Checks if the value of the field is ACTIVE_HIGH

pub fn is_active_low(&self) -> bool

Checks if the value of the field is ACTIVE_LOW

impl R<u8, INC_SEL_A>

pub fn variant(&self) -> INC_SEL_A

Get enumerated values variant

pub fn is_pclk(&self) -> bool

Checks if the value of the field is PCLK

pub fn is_line(&self) -> bool

Checks if the value of the field is LINE

pub fn is_frame(&self) -> bool

Checks if the value of the field is FRAME

pub fn is_sig_another(&self) -> bool

Checks if the value of the field is SIG_ANOTHER

impl R<u8, MASK_CNT_SEL_A>

pub fn variant(&self) -> Variant<u8, MASK_CNT_SEL_A>

Get enumerated values variant

pub fn is_hstate_cnt(&self) -> bool

Checks if the value of the field is HSTATE_CNT

pub fn is_hstate_cycle(&self) -> bool

Checks if the value of the field is HSTATE_CYCLE

pub fn is_vstate_cnt(&self) -> bool

Checks if the value of the field is VSTATE_CNT

pub fn is_vstate_cycle(&self) -> bool

Checks if the value of the field is VSTATE_CYCLE

pub fn is_frame_cnt(&self) -> bool

Checks if the value of the field is FRAME_CNT

pub fn is_frame_cycle(&self) -> bool

Checks if the value of the field is FRAME_CYCLE

pub fn is_hcnt(&self) -> bool

Checks if the value of the field is HCNT

pub fn is_vcnt(&self) -> bool

Checks if the value of the field is VCNT

impl R<u8, STATE_MASK_A>

pub fn variant(&self) -> Variant<u8, STATE_MASK_A>

Get enumerated values variant

pub fn is_fs(&self) -> bool

Checks if the value of the field is FS

pub fn is_fb(&self) -> bool

Checks if the value of the field is FB

pub fn is_fd(&self) -> bool

Checks if the value of the field is FD

pub fn is_fe(&self) -> bool

Checks if the value of the field is FE

pub fn is_ls(&self) -> bool

Checks if the value of the field is LS

pub fn is_lb(&self) -> bool

Checks if the value of the field is LB

pub fn is_ld(&self) -> bool

Checks if the value of the field is LD

pub fn is_le(&self) -> bool

Checks if the value of the field is LE

impl R<u32, Reg<u32, _PIGEON_2_0>>

pub fn en(&self) -> EN_R

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&self) -> POL_R

Bit 1 - Polarity of signal output

pub fn inc_sel(&self) -> INC_SEL_R

Bits 2:3 - Event to incrment local counter

pub fn offset(&self) -> OFFSET_R

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&self) -> MASK_CNT_SEL_R

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&self) -> MASK_CNT_R

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&self) -> STATE_MASK_R

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl R<u16, SET_CNT_A>

pub fn variant(&self) -> Variant<u16, SET_CNT_A>

Get enumerated values variant

pub fn is_start_active(&self) -> bool

Checks if the value of the field is START_ACTIVE

impl R<u16, CLR_CNT_A>

pub fn variant(&self) -> Variant<u16, CLR_CNT_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_2_1>>

pub fn set_cnt(&self) -> SET_CNT_R

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&self) -> CLR_CNT_R

Bits 16:31 - Deassert signal output when counter match this value

impl R<u8, SIG_LOGIC_A>

pub fn variant(&self) -> Variant<u8, SIG_LOGIC_A>

Get enumerated values variant

pub fn is_dis(&self) -> bool

Checks if the value of the field is DIS

pub fn is_and(&self) -> bool

Checks if the value of the field is AND

pub fn is_or(&self) -> bool

Checks if the value of the field is OR

pub fn is_mask(&self) -> bool

Checks if the value of the field is MASK

impl R<u8, SIG_ANOTHER_A>

pub fn variant(&self) -> Variant<u8, SIG_ANOTHER_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_2_2>>

pub fn sig_logic(&self) -> SIG_LOGIC_R

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&self) -> SIG_ANOTHER_R

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl R<bool, POL_A>

pub fn variant(&self) -> POL_A

Get enumerated values variant

pub fn is_active_high(&self) -> bool

Checks if the value of the field is ACTIVE_HIGH

pub fn is_active_low(&self) -> bool

Checks if the value of the field is ACTIVE_LOW

impl R<u8, INC_SEL_A>

pub fn variant(&self) -> INC_SEL_A

Get enumerated values variant

pub fn is_pclk(&self) -> bool

Checks if the value of the field is PCLK

pub fn is_line(&self) -> bool

Checks if the value of the field is LINE

pub fn is_frame(&self) -> bool

Checks if the value of the field is FRAME

pub fn is_sig_another(&self) -> bool

Checks if the value of the field is SIG_ANOTHER

impl R<u8, MASK_CNT_SEL_A>

pub fn variant(&self) -> Variant<u8, MASK_CNT_SEL_A>

Get enumerated values variant

pub fn is_hstate_cnt(&self) -> bool

Checks if the value of the field is HSTATE_CNT

pub fn is_hstate_cycle(&self) -> bool

Checks if the value of the field is HSTATE_CYCLE

pub fn is_vstate_cnt(&self) -> bool

Checks if the value of the field is VSTATE_CNT

pub fn is_vstate_cycle(&self) -> bool

Checks if the value of the field is VSTATE_CYCLE

pub fn is_frame_cnt(&self) -> bool

Checks if the value of the field is FRAME_CNT

pub fn is_frame_cycle(&self) -> bool

Checks if the value of the field is FRAME_CYCLE

pub fn is_hcnt(&self) -> bool

Checks if the value of the field is HCNT

pub fn is_vcnt(&self) -> bool

Checks if the value of the field is VCNT

impl R<u8, STATE_MASK_A>

pub fn variant(&self) -> Variant<u8, STATE_MASK_A>

Get enumerated values variant

pub fn is_fs(&self) -> bool

Checks if the value of the field is FS

pub fn is_fb(&self) -> bool

Checks if the value of the field is FB

pub fn is_fd(&self) -> bool

Checks if the value of the field is FD

pub fn is_fe(&self) -> bool

Checks if the value of the field is FE

pub fn is_ls(&self) -> bool

Checks if the value of the field is LS

pub fn is_lb(&self) -> bool

Checks if the value of the field is LB

pub fn is_ld(&self) -> bool

Checks if the value of the field is LD

pub fn is_le(&self) -> bool

Checks if the value of the field is LE

impl R<u32, Reg<u32, _PIGEON_3_0>>

pub fn en(&self) -> EN_R

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&self) -> POL_R

Bit 1 - Polarity of signal output

pub fn inc_sel(&self) -> INC_SEL_R

Bits 2:3 - Event to incrment local counter

pub fn offset(&self) -> OFFSET_R

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&self) -> MASK_CNT_SEL_R

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&self) -> MASK_CNT_R

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&self) -> STATE_MASK_R

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl R<u16, SET_CNT_A>

pub fn variant(&self) -> Variant<u16, SET_CNT_A>

Get enumerated values variant

pub fn is_start_active(&self) -> bool

Checks if the value of the field is START_ACTIVE

impl R<u16, CLR_CNT_A>

pub fn variant(&self) -> Variant<u16, CLR_CNT_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_3_1>>

pub fn set_cnt(&self) -> SET_CNT_R

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&self) -> CLR_CNT_R

Bits 16:31 - Deassert signal output when counter match this value

impl R<u8, SIG_LOGIC_A>

pub fn variant(&self) -> Variant<u8, SIG_LOGIC_A>

Get enumerated values variant

pub fn is_dis(&self) -> bool

Checks if the value of the field is DIS

pub fn is_and(&self) -> bool

Checks if the value of the field is AND

pub fn is_or(&self) -> bool

Checks if the value of the field is OR

pub fn is_mask(&self) -> bool

Checks if the value of the field is MASK

impl R<u8, SIG_ANOTHER_A>

pub fn variant(&self) -> Variant<u8, SIG_ANOTHER_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_3_2>>

pub fn sig_logic(&self) -> SIG_LOGIC_R

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&self) -> SIG_ANOTHER_R

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl R<bool, POL_A>

pub fn variant(&self) -> POL_A

Get enumerated values variant

pub fn is_active_high(&self) -> bool

Checks if the value of the field is ACTIVE_HIGH

pub fn is_active_low(&self) -> bool

Checks if the value of the field is ACTIVE_LOW

impl R<u8, INC_SEL_A>

pub fn variant(&self) -> INC_SEL_A

Get enumerated values variant

pub fn is_pclk(&self) -> bool

Checks if the value of the field is PCLK

pub fn is_line(&self) -> bool

Checks if the value of the field is LINE

pub fn is_frame(&self) -> bool

Checks if the value of the field is FRAME

pub fn is_sig_another(&self) -> bool

Checks if the value of the field is SIG_ANOTHER

impl R<u8, MASK_CNT_SEL_A>

pub fn variant(&self) -> Variant<u8, MASK_CNT_SEL_A>

Get enumerated values variant

pub fn is_hstate_cnt(&self) -> bool

Checks if the value of the field is HSTATE_CNT

pub fn is_hstate_cycle(&self) -> bool

Checks if the value of the field is HSTATE_CYCLE

pub fn is_vstate_cnt(&self) -> bool

Checks if the value of the field is VSTATE_CNT

pub fn is_vstate_cycle(&self) -> bool

Checks if the value of the field is VSTATE_CYCLE

pub fn is_frame_cnt(&self) -> bool

Checks if the value of the field is FRAME_CNT

pub fn is_frame_cycle(&self) -> bool

Checks if the value of the field is FRAME_CYCLE

pub fn is_hcnt(&self) -> bool

Checks if the value of the field is HCNT

pub fn is_vcnt(&self) -> bool

Checks if the value of the field is VCNT

impl R<u8, STATE_MASK_A>

pub fn variant(&self) -> Variant<u8, STATE_MASK_A>

Get enumerated values variant

pub fn is_fs(&self) -> bool

Checks if the value of the field is FS

pub fn is_fb(&self) -> bool

Checks if the value of the field is FB

pub fn is_fd(&self) -> bool

Checks if the value of the field is FD

pub fn is_fe(&self) -> bool

Checks if the value of the field is FE

pub fn is_ls(&self) -> bool

Checks if the value of the field is LS

pub fn is_lb(&self) -> bool

Checks if the value of the field is LB

pub fn is_ld(&self) -> bool

Checks if the value of the field is LD

pub fn is_le(&self) -> bool

Checks if the value of the field is LE

impl R<u32, Reg<u32, _PIGEON_4_0>>

pub fn en(&self) -> EN_R

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&self) -> POL_R

Bit 1 - Polarity of signal output

pub fn inc_sel(&self) -> INC_SEL_R

Bits 2:3 - Event to incrment local counter

pub fn offset(&self) -> OFFSET_R

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&self) -> MASK_CNT_SEL_R

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&self) -> MASK_CNT_R

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&self) -> STATE_MASK_R

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl R<u16, SET_CNT_A>

pub fn variant(&self) -> Variant<u16, SET_CNT_A>

Get enumerated values variant

pub fn is_start_active(&self) -> bool

Checks if the value of the field is START_ACTIVE

impl R<u16, CLR_CNT_A>

pub fn variant(&self) -> Variant<u16, CLR_CNT_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_4_1>>

pub fn set_cnt(&self) -> SET_CNT_R

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&self) -> CLR_CNT_R

Bits 16:31 - Deassert signal output when counter match this value

impl R<u8, SIG_LOGIC_A>

pub fn variant(&self) -> Variant<u8, SIG_LOGIC_A>

Get enumerated values variant

pub fn is_dis(&self) -> bool

Checks if the value of the field is DIS

pub fn is_and(&self) -> bool

Checks if the value of the field is AND

pub fn is_or(&self) -> bool

Checks if the value of the field is OR

pub fn is_mask(&self) -> bool

Checks if the value of the field is MASK

impl R<u8, SIG_ANOTHER_A>

pub fn variant(&self) -> Variant<u8, SIG_ANOTHER_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_4_2>>

pub fn sig_logic(&self) -> SIG_LOGIC_R

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&self) -> SIG_ANOTHER_R

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl R<bool, POL_A>

pub fn variant(&self) -> POL_A

Get enumerated values variant

pub fn is_active_high(&self) -> bool

Checks if the value of the field is ACTIVE_HIGH

pub fn is_active_low(&self) -> bool

Checks if the value of the field is ACTIVE_LOW

impl R<u8, INC_SEL_A>

pub fn variant(&self) -> INC_SEL_A

Get enumerated values variant

pub fn is_pclk(&self) -> bool

Checks if the value of the field is PCLK

pub fn is_line(&self) -> bool

Checks if the value of the field is LINE

pub fn is_frame(&self) -> bool

Checks if the value of the field is FRAME

pub fn is_sig_another(&self) -> bool

Checks if the value of the field is SIG_ANOTHER

impl R<u8, MASK_CNT_SEL_A>

pub fn variant(&self) -> Variant<u8, MASK_CNT_SEL_A>

Get enumerated values variant

pub fn is_hstate_cnt(&self) -> bool

Checks if the value of the field is HSTATE_CNT

pub fn is_hstate_cycle(&self) -> bool

Checks if the value of the field is HSTATE_CYCLE

pub fn is_vstate_cnt(&self) -> bool

Checks if the value of the field is VSTATE_CNT

pub fn is_vstate_cycle(&self) -> bool

Checks if the value of the field is VSTATE_CYCLE

pub fn is_frame_cnt(&self) -> bool

Checks if the value of the field is FRAME_CNT

pub fn is_frame_cycle(&self) -> bool

Checks if the value of the field is FRAME_CYCLE

pub fn is_hcnt(&self) -> bool

Checks if the value of the field is HCNT

pub fn is_vcnt(&self) -> bool

Checks if the value of the field is VCNT

impl R<u8, STATE_MASK_A>

pub fn variant(&self) -> Variant<u8, STATE_MASK_A>

Get enumerated values variant

pub fn is_fs(&self) -> bool

Checks if the value of the field is FS

pub fn is_fb(&self) -> bool

Checks if the value of the field is FB

pub fn is_fd(&self) -> bool

Checks if the value of the field is FD

pub fn is_fe(&self) -> bool

Checks if the value of the field is FE

pub fn is_ls(&self) -> bool

Checks if the value of the field is LS

pub fn is_lb(&self) -> bool

Checks if the value of the field is LB

pub fn is_ld(&self) -> bool

Checks if the value of the field is LD

pub fn is_le(&self) -> bool

Checks if the value of the field is LE

impl R<u32, Reg<u32, _PIGEON_5_0>>

pub fn en(&self) -> EN_R

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&self) -> POL_R

Bit 1 - Polarity of signal output

pub fn inc_sel(&self) -> INC_SEL_R

Bits 2:3 - Event to incrment local counter

pub fn offset(&self) -> OFFSET_R

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&self) -> MASK_CNT_SEL_R

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&self) -> MASK_CNT_R

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&self) -> STATE_MASK_R

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl R<u16, SET_CNT_A>

pub fn variant(&self) -> Variant<u16, SET_CNT_A>

Get enumerated values variant

pub fn is_start_active(&self) -> bool

Checks if the value of the field is START_ACTIVE

impl R<u16, CLR_CNT_A>

pub fn variant(&self) -> Variant<u16, CLR_CNT_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_5_1>>

pub fn set_cnt(&self) -> SET_CNT_R

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&self) -> CLR_CNT_R

Bits 16:31 - Deassert signal output when counter match this value

impl R<u8, SIG_LOGIC_A>

pub fn variant(&self) -> Variant<u8, SIG_LOGIC_A>

Get enumerated values variant

pub fn is_dis(&self) -> bool

Checks if the value of the field is DIS

pub fn is_and(&self) -> bool

Checks if the value of the field is AND

pub fn is_or(&self) -> bool

Checks if the value of the field is OR

pub fn is_mask(&self) -> bool

Checks if the value of the field is MASK

impl R<u8, SIG_ANOTHER_A>

pub fn variant(&self) -> Variant<u8, SIG_ANOTHER_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_5_2>>

pub fn sig_logic(&self) -> SIG_LOGIC_R

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&self) -> SIG_ANOTHER_R

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl R<bool, POL_A>

pub fn variant(&self) -> POL_A

Get enumerated values variant

pub fn is_active_high(&self) -> bool

Checks if the value of the field is ACTIVE_HIGH

pub fn is_active_low(&self) -> bool

Checks if the value of the field is ACTIVE_LOW

impl R<u8, INC_SEL_A>

pub fn variant(&self) -> INC_SEL_A

Get enumerated values variant

pub fn is_pclk(&self) -> bool

Checks if the value of the field is PCLK

pub fn is_line(&self) -> bool

Checks if the value of the field is LINE

pub fn is_frame(&self) -> bool

Checks if the value of the field is FRAME

pub fn is_sig_another(&self) -> bool

Checks if the value of the field is SIG_ANOTHER

impl R<u8, MASK_CNT_SEL_A>

pub fn variant(&self) -> Variant<u8, MASK_CNT_SEL_A>

Get enumerated values variant

pub fn is_hstate_cnt(&self) -> bool

Checks if the value of the field is HSTATE_CNT

pub fn is_hstate_cycle(&self) -> bool

Checks if the value of the field is HSTATE_CYCLE

pub fn is_vstate_cnt(&self) -> bool

Checks if the value of the field is VSTATE_CNT

pub fn is_vstate_cycle(&self) -> bool

Checks if the value of the field is VSTATE_CYCLE

pub fn is_frame_cnt(&self) -> bool

Checks if the value of the field is FRAME_CNT

pub fn is_frame_cycle(&self) -> bool

Checks if the value of the field is FRAME_CYCLE

pub fn is_hcnt(&self) -> bool

Checks if the value of the field is HCNT

pub fn is_vcnt(&self) -> bool

Checks if the value of the field is VCNT

impl R<u8, STATE_MASK_A>

pub fn variant(&self) -> Variant<u8, STATE_MASK_A>

Get enumerated values variant

pub fn is_fs(&self) -> bool

Checks if the value of the field is FS

pub fn is_fb(&self) -> bool

Checks if the value of the field is FB

pub fn is_fd(&self) -> bool

Checks if the value of the field is FD

pub fn is_fe(&self) -> bool

Checks if the value of the field is FE

pub fn is_ls(&self) -> bool

Checks if the value of the field is LS

pub fn is_lb(&self) -> bool

Checks if the value of the field is LB

pub fn is_ld(&self) -> bool

Checks if the value of the field is LD

pub fn is_le(&self) -> bool

Checks if the value of the field is LE

impl R<u32, Reg<u32, _PIGEON_6_0>>

pub fn en(&self) -> EN_R

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&self) -> POL_R

Bit 1 - Polarity of signal output

pub fn inc_sel(&self) -> INC_SEL_R

Bits 2:3 - Event to incrment local counter

pub fn offset(&self) -> OFFSET_R

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&self) -> MASK_CNT_SEL_R

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&self) -> MASK_CNT_R

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&self) -> STATE_MASK_R

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl R<u16, SET_CNT_A>

pub fn variant(&self) -> Variant<u16, SET_CNT_A>

Get enumerated values variant

pub fn is_start_active(&self) -> bool

Checks if the value of the field is START_ACTIVE

impl R<u16, CLR_CNT_A>

pub fn variant(&self) -> Variant<u16, CLR_CNT_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_6_1>>

pub fn set_cnt(&self) -> SET_CNT_R

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&self) -> CLR_CNT_R

Bits 16:31 - Deassert signal output when counter match this value

impl R<u8, SIG_LOGIC_A>

pub fn variant(&self) -> Variant<u8, SIG_LOGIC_A>

Get enumerated values variant

pub fn is_dis(&self) -> bool

Checks if the value of the field is DIS

pub fn is_and(&self) -> bool

Checks if the value of the field is AND

pub fn is_or(&self) -> bool

Checks if the value of the field is OR

pub fn is_mask(&self) -> bool

Checks if the value of the field is MASK

impl R<u8, SIG_ANOTHER_A>

pub fn variant(&self) -> Variant<u8, SIG_ANOTHER_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_6_2>>

pub fn sig_logic(&self) -> SIG_LOGIC_R

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&self) -> SIG_ANOTHER_R

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl R<bool, POL_A>

pub fn variant(&self) -> POL_A

Get enumerated values variant

pub fn is_active_high(&self) -> bool

Checks if the value of the field is ACTIVE_HIGH

pub fn is_active_low(&self) -> bool

Checks if the value of the field is ACTIVE_LOW

impl R<u8, INC_SEL_A>

pub fn variant(&self) -> INC_SEL_A

Get enumerated values variant

pub fn is_pclk(&self) -> bool

Checks if the value of the field is PCLK

pub fn is_line(&self) -> bool

Checks if the value of the field is LINE

pub fn is_frame(&self) -> bool

Checks if the value of the field is FRAME

pub fn is_sig_another(&self) -> bool

Checks if the value of the field is SIG_ANOTHER

impl R<u8, MASK_CNT_SEL_A>

pub fn variant(&self) -> Variant<u8, MASK_CNT_SEL_A>

Get enumerated values variant

pub fn is_hstate_cnt(&self) -> bool

Checks if the value of the field is HSTATE_CNT

pub fn is_hstate_cycle(&self) -> bool

Checks if the value of the field is HSTATE_CYCLE

pub fn is_vstate_cnt(&self) -> bool

Checks if the value of the field is VSTATE_CNT

pub fn is_vstate_cycle(&self) -> bool

Checks if the value of the field is VSTATE_CYCLE

pub fn is_frame_cnt(&self) -> bool

Checks if the value of the field is FRAME_CNT

pub fn is_frame_cycle(&self) -> bool

Checks if the value of the field is FRAME_CYCLE

pub fn is_hcnt(&self) -> bool

Checks if the value of the field is HCNT

pub fn is_vcnt(&self) -> bool

Checks if the value of the field is VCNT

impl R<u8, STATE_MASK_A>

pub fn variant(&self) -> Variant<u8, STATE_MASK_A>

Get enumerated values variant

pub fn is_fs(&self) -> bool

Checks if the value of the field is FS

pub fn is_fb(&self) -> bool

Checks if the value of the field is FB

pub fn is_fd(&self) -> bool

Checks if the value of the field is FD

pub fn is_fe(&self) -> bool

Checks if the value of the field is FE

pub fn is_ls(&self) -> bool

Checks if the value of the field is LS

pub fn is_lb(&self) -> bool

Checks if the value of the field is LB

pub fn is_ld(&self) -> bool

Checks if the value of the field is LD

pub fn is_le(&self) -> bool

Checks if the value of the field is LE

impl R<u32, Reg<u32, _PIGEON_7_0>>

pub fn en(&self) -> EN_R

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&self) -> POL_R

Bit 1 - Polarity of signal output

pub fn inc_sel(&self) -> INC_SEL_R

Bits 2:3 - Event to incrment local counter

pub fn offset(&self) -> OFFSET_R

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&self) -> MASK_CNT_SEL_R

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&self) -> MASK_CNT_R

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&self) -> STATE_MASK_R

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl R<u16, SET_CNT_A>

pub fn variant(&self) -> Variant<u16, SET_CNT_A>

Get enumerated values variant

pub fn is_start_active(&self) -> bool

Checks if the value of the field is START_ACTIVE

impl R<u16, CLR_CNT_A>

pub fn variant(&self) -> Variant<u16, CLR_CNT_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_7_1>>

pub fn set_cnt(&self) -> SET_CNT_R

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&self) -> CLR_CNT_R

Bits 16:31 - Deassert signal output when counter match this value

impl R<u8, SIG_LOGIC_A>

pub fn variant(&self) -> Variant<u8, SIG_LOGIC_A>

Get enumerated values variant

pub fn is_dis(&self) -> bool

Checks if the value of the field is DIS

pub fn is_and(&self) -> bool

Checks if the value of the field is AND

pub fn is_or(&self) -> bool

Checks if the value of the field is OR

pub fn is_mask(&self) -> bool

Checks if the value of the field is MASK

impl R<u8, SIG_ANOTHER_A>

pub fn variant(&self) -> Variant<u8, SIG_ANOTHER_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_7_2>>

pub fn sig_logic(&self) -> SIG_LOGIC_R

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&self) -> SIG_ANOTHER_R

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl R<bool, POL_A>

pub fn variant(&self) -> POL_A

Get enumerated values variant

pub fn is_active_high(&self) -> bool

Checks if the value of the field is ACTIVE_HIGH

pub fn is_active_low(&self) -> bool

Checks if the value of the field is ACTIVE_LOW

impl R<u8, INC_SEL_A>

pub fn variant(&self) -> INC_SEL_A

Get enumerated values variant

pub fn is_pclk(&self) -> bool

Checks if the value of the field is PCLK

pub fn is_line(&self) -> bool

Checks if the value of the field is LINE

pub fn is_frame(&self) -> bool

Checks if the value of the field is FRAME

pub fn is_sig_another(&self) -> bool

Checks if the value of the field is SIG_ANOTHER

impl R<u8, MASK_CNT_SEL_A>

pub fn variant(&self) -> Variant<u8, MASK_CNT_SEL_A>

Get enumerated values variant

pub fn is_hstate_cnt(&self) -> bool

Checks if the value of the field is HSTATE_CNT

pub fn is_hstate_cycle(&self) -> bool

Checks if the value of the field is HSTATE_CYCLE

pub fn is_vstate_cnt(&self) -> bool

Checks if the value of the field is VSTATE_CNT

pub fn is_vstate_cycle(&self) -> bool

Checks if the value of the field is VSTATE_CYCLE

pub fn is_frame_cnt(&self) -> bool

Checks if the value of the field is FRAME_CNT

pub fn is_frame_cycle(&self) -> bool

Checks if the value of the field is FRAME_CYCLE

pub fn is_hcnt(&self) -> bool

Checks if the value of the field is HCNT

pub fn is_vcnt(&self) -> bool

Checks if the value of the field is VCNT

impl R<u8, STATE_MASK_A>

pub fn variant(&self) -> Variant<u8, STATE_MASK_A>

Get enumerated values variant

pub fn is_fs(&self) -> bool

Checks if the value of the field is FS

pub fn is_fb(&self) -> bool

Checks if the value of the field is FB

pub fn is_fd(&self) -> bool

Checks if the value of the field is FD

pub fn is_fe(&self) -> bool

Checks if the value of the field is FE

pub fn is_ls(&self) -> bool

Checks if the value of the field is LS

pub fn is_lb(&self) -> bool

Checks if the value of the field is LB

pub fn is_ld(&self) -> bool

Checks if the value of the field is LD

pub fn is_le(&self) -> bool

Checks if the value of the field is LE

impl R<u32, Reg<u32, _PIGEON_8_0>>

pub fn en(&self) -> EN_R

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&self) -> POL_R

Bit 1 - Polarity of signal output

pub fn inc_sel(&self) -> INC_SEL_R

Bits 2:3 - Event to incrment local counter

pub fn offset(&self) -> OFFSET_R

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&self) -> MASK_CNT_SEL_R

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&self) -> MASK_CNT_R

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&self) -> STATE_MASK_R

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl R<u16, SET_CNT_A>

pub fn variant(&self) -> Variant<u16, SET_CNT_A>

Get enumerated values variant

pub fn is_start_active(&self) -> bool

Checks if the value of the field is START_ACTIVE

impl R<u16, CLR_CNT_A>

pub fn variant(&self) -> Variant<u16, CLR_CNT_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_8_1>>

pub fn set_cnt(&self) -> SET_CNT_R

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&self) -> CLR_CNT_R

Bits 16:31 - Deassert signal output when counter match this value

impl R<u8, SIG_LOGIC_A>

pub fn variant(&self) -> Variant<u8, SIG_LOGIC_A>

Get enumerated values variant

pub fn is_dis(&self) -> bool

Checks if the value of the field is DIS

pub fn is_and(&self) -> bool

Checks if the value of the field is AND

pub fn is_or(&self) -> bool

Checks if the value of the field is OR

pub fn is_mask(&self) -> bool

Checks if the value of the field is MASK

impl R<u8, SIG_ANOTHER_A>

pub fn variant(&self) -> Variant<u8, SIG_ANOTHER_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_8_2>>

pub fn sig_logic(&self) -> SIG_LOGIC_R

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&self) -> SIG_ANOTHER_R

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl R<bool, POL_A>

pub fn variant(&self) -> POL_A

Get enumerated values variant

pub fn is_active_high(&self) -> bool

Checks if the value of the field is ACTIVE_HIGH

pub fn is_active_low(&self) -> bool

Checks if the value of the field is ACTIVE_LOW

impl R<u8, INC_SEL_A>

pub fn variant(&self) -> INC_SEL_A

Get enumerated values variant

pub fn is_pclk(&self) -> bool

Checks if the value of the field is PCLK

pub fn is_line(&self) -> bool

Checks if the value of the field is LINE

pub fn is_frame(&self) -> bool

Checks if the value of the field is FRAME

pub fn is_sig_another(&self) -> bool

Checks if the value of the field is SIG_ANOTHER

impl R<u8, MASK_CNT_SEL_A>

pub fn variant(&self) -> Variant<u8, MASK_CNT_SEL_A>

Get enumerated values variant

pub fn is_hstate_cnt(&self) -> bool

Checks if the value of the field is HSTATE_CNT

pub fn is_hstate_cycle(&self) -> bool

Checks if the value of the field is HSTATE_CYCLE

pub fn is_vstate_cnt(&self) -> bool

Checks if the value of the field is VSTATE_CNT

pub fn is_vstate_cycle(&self) -> bool

Checks if the value of the field is VSTATE_CYCLE

pub fn is_frame_cnt(&self) -> bool

Checks if the value of the field is FRAME_CNT

pub fn is_frame_cycle(&self) -> bool

Checks if the value of the field is FRAME_CYCLE

pub fn is_hcnt(&self) -> bool

Checks if the value of the field is HCNT

pub fn is_vcnt(&self) -> bool

Checks if the value of the field is VCNT

impl R<u8, STATE_MASK_A>

pub fn variant(&self) -> Variant<u8, STATE_MASK_A>

Get enumerated values variant

pub fn is_fs(&self) -> bool

Checks if the value of the field is FS

pub fn is_fb(&self) -> bool

Checks if the value of the field is FB

pub fn is_fd(&self) -> bool

Checks if the value of the field is FD

pub fn is_fe(&self) -> bool

Checks if the value of the field is FE

pub fn is_ls(&self) -> bool

Checks if the value of the field is LS

pub fn is_lb(&self) -> bool

Checks if the value of the field is LB

pub fn is_ld(&self) -> bool

Checks if the value of the field is LD

pub fn is_le(&self) -> bool

Checks if the value of the field is LE

impl R<u32, Reg<u32, _PIGEON_9_0>>

pub fn en(&self) -> EN_R

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&self) -> POL_R

Bit 1 - Polarity of signal output

pub fn inc_sel(&self) -> INC_SEL_R

Bits 2:3 - Event to incrment local counter

pub fn offset(&self) -> OFFSET_R

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&self) -> MASK_CNT_SEL_R

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&self) -> MASK_CNT_R

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&self) -> STATE_MASK_R

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl R<u16, SET_CNT_A>

pub fn variant(&self) -> Variant<u16, SET_CNT_A>

Get enumerated values variant

pub fn is_start_active(&self) -> bool

Checks if the value of the field is START_ACTIVE

impl R<u16, CLR_CNT_A>

pub fn variant(&self) -> Variant<u16, CLR_CNT_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_9_1>>

pub fn set_cnt(&self) -> SET_CNT_R

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&self) -> CLR_CNT_R

Bits 16:31 - Deassert signal output when counter match this value

impl R<u8, SIG_LOGIC_A>

pub fn variant(&self) -> Variant<u8, SIG_LOGIC_A>

Get enumerated values variant

pub fn is_dis(&self) -> bool

Checks if the value of the field is DIS

pub fn is_and(&self) -> bool

Checks if the value of the field is AND

pub fn is_or(&self) -> bool

Checks if the value of the field is OR

pub fn is_mask(&self) -> bool

Checks if the value of the field is MASK

impl R<u8, SIG_ANOTHER_A>

pub fn variant(&self) -> Variant<u8, SIG_ANOTHER_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_9_2>>

pub fn sig_logic(&self) -> SIG_LOGIC_R

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&self) -> SIG_ANOTHER_R

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl R<bool, POL_A>

pub fn variant(&self) -> POL_A

Get enumerated values variant

pub fn is_active_high(&self) -> bool

Checks if the value of the field is ACTIVE_HIGH

pub fn is_active_low(&self) -> bool

Checks if the value of the field is ACTIVE_LOW

impl R<u8, INC_SEL_A>

pub fn variant(&self) -> INC_SEL_A

Get enumerated values variant

pub fn is_pclk(&self) -> bool

Checks if the value of the field is PCLK

pub fn is_line(&self) -> bool

Checks if the value of the field is LINE

pub fn is_frame(&self) -> bool

Checks if the value of the field is FRAME

pub fn is_sig_another(&self) -> bool

Checks if the value of the field is SIG_ANOTHER

impl R<u8, MASK_CNT_SEL_A>

pub fn variant(&self) -> Variant<u8, MASK_CNT_SEL_A>

Get enumerated values variant

pub fn is_hstate_cnt(&self) -> bool

Checks if the value of the field is HSTATE_CNT

pub fn is_hstate_cycle(&self) -> bool

Checks if the value of the field is HSTATE_CYCLE

pub fn is_vstate_cnt(&self) -> bool

Checks if the value of the field is VSTATE_CNT

pub fn is_vstate_cycle(&self) -> bool

Checks if the value of the field is VSTATE_CYCLE

pub fn is_frame_cnt(&self) -> bool

Checks if the value of the field is FRAME_CNT

pub fn is_frame_cycle(&self) -> bool

Checks if the value of the field is FRAME_CYCLE

pub fn is_hcnt(&self) -> bool

Checks if the value of the field is HCNT

pub fn is_vcnt(&self) -> bool

Checks if the value of the field is VCNT

impl R<u8, STATE_MASK_A>

pub fn variant(&self) -> Variant<u8, STATE_MASK_A>

Get enumerated values variant

pub fn is_fs(&self) -> bool

Checks if the value of the field is FS

pub fn is_fb(&self) -> bool

Checks if the value of the field is FB

pub fn is_fd(&self) -> bool

Checks if the value of the field is FD

pub fn is_fe(&self) -> bool

Checks if the value of the field is FE

pub fn is_ls(&self) -> bool

Checks if the value of the field is LS

pub fn is_lb(&self) -> bool

Checks if the value of the field is LB

pub fn is_ld(&self) -> bool

Checks if the value of the field is LD

pub fn is_le(&self) -> bool

Checks if the value of the field is LE

impl R<u32, Reg<u32, _PIGEON_10_0>>

pub fn en(&self) -> EN_R

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&self) -> POL_R

Bit 1 - Polarity of signal output

pub fn inc_sel(&self) -> INC_SEL_R

Bits 2:3 - Event to incrment local counter

pub fn offset(&self) -> OFFSET_R

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&self) -> MASK_CNT_SEL_R

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&self) -> MASK_CNT_R

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&self) -> STATE_MASK_R

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl R<u16, SET_CNT_A>

pub fn variant(&self) -> Variant<u16, SET_CNT_A>

Get enumerated values variant

pub fn is_start_active(&self) -> bool

Checks if the value of the field is START_ACTIVE

impl R<u16, CLR_CNT_A>

pub fn variant(&self) -> Variant<u16, CLR_CNT_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_10_1>>

pub fn set_cnt(&self) -> SET_CNT_R

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&self) -> CLR_CNT_R

Bits 16:31 - Deassert signal output when counter match this value

impl R<u8, SIG_LOGIC_A>

pub fn variant(&self) -> Variant<u8, SIG_LOGIC_A>

Get enumerated values variant

pub fn is_dis(&self) -> bool

Checks if the value of the field is DIS

pub fn is_and(&self) -> bool

Checks if the value of the field is AND

pub fn is_or(&self) -> bool

Checks if the value of the field is OR

pub fn is_mask(&self) -> bool

Checks if the value of the field is MASK

impl R<u8, SIG_ANOTHER_A>

pub fn variant(&self) -> Variant<u8, SIG_ANOTHER_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_10_2>>

pub fn sig_logic(&self) -> SIG_LOGIC_R

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&self) -> SIG_ANOTHER_R

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl R<bool, POL_A>

pub fn variant(&self) -> POL_A

Get enumerated values variant

pub fn is_active_high(&self) -> bool

Checks if the value of the field is ACTIVE_HIGH

pub fn is_active_low(&self) -> bool

Checks if the value of the field is ACTIVE_LOW

impl R<u8, INC_SEL_A>

pub fn variant(&self) -> INC_SEL_A

Get enumerated values variant

pub fn is_pclk(&self) -> bool

Checks if the value of the field is PCLK

pub fn is_line(&self) -> bool

Checks if the value of the field is LINE

pub fn is_frame(&self) -> bool

Checks if the value of the field is FRAME

pub fn is_sig_another(&self) -> bool

Checks if the value of the field is SIG_ANOTHER

impl R<u8, MASK_CNT_SEL_A>

pub fn variant(&self) -> Variant<u8, MASK_CNT_SEL_A>

Get enumerated values variant

pub fn is_hstate_cnt(&self) -> bool

Checks if the value of the field is HSTATE_CNT

pub fn is_hstate_cycle(&self) -> bool

Checks if the value of the field is HSTATE_CYCLE

pub fn is_vstate_cnt(&self) -> bool

Checks if the value of the field is VSTATE_CNT

pub fn is_vstate_cycle(&self) -> bool

Checks if the value of the field is VSTATE_CYCLE

pub fn is_frame_cnt(&self) -> bool

Checks if the value of the field is FRAME_CNT

pub fn is_frame_cycle(&self) -> bool

Checks if the value of the field is FRAME_CYCLE

pub fn is_hcnt(&self) -> bool

Checks if the value of the field is HCNT

pub fn is_vcnt(&self) -> bool

Checks if the value of the field is VCNT

impl R<u8, STATE_MASK_A>

pub fn variant(&self) -> Variant<u8, STATE_MASK_A>

Get enumerated values variant

pub fn is_fs(&self) -> bool

Checks if the value of the field is FS

pub fn is_fb(&self) -> bool

Checks if the value of the field is FB

pub fn is_fd(&self) -> bool

Checks if the value of the field is FD

pub fn is_fe(&self) -> bool

Checks if the value of the field is FE

pub fn is_ls(&self) -> bool

Checks if the value of the field is LS

pub fn is_lb(&self) -> bool

Checks if the value of the field is LB

pub fn is_ld(&self) -> bool

Checks if the value of the field is LD

pub fn is_le(&self) -> bool

Checks if the value of the field is LE

impl R<u32, Reg<u32, _PIGEON_11_0>>

pub fn en(&self) -> EN_R

Bit 0 - Enable pigeon Mode on this signal

pub fn pol(&self) -> POL_R

Bit 1 - Polarity of signal output

pub fn inc_sel(&self) -> INC_SEL_R

Bits 2:3 - Event to incrment local counter

pub fn offset(&self) -> OFFSET_R

Bits 4:7 - offset on pclk unit

pub fn mask_cnt_sel(&self) -> MASK_CNT_SEL_R

Bits 8:11 - select global counters as mask condition, use together with MASK_CNT

pub fn mask_cnt(&self) -> MASK_CNT_R

Bits 12:23 - When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking

pub fn state_mask(&self) -> STATE_MASK_R

Bits 24:31 - state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking

impl R<u16, SET_CNT_A>

pub fn variant(&self) -> Variant<u16, SET_CNT_A>

Get enumerated values variant

pub fn is_start_active(&self) -> bool

Checks if the value of the field is START_ACTIVE

impl R<u16, CLR_CNT_A>

pub fn variant(&self) -> Variant<u16, CLR_CNT_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_11_1>>

pub fn set_cnt(&self) -> SET_CNT_R

Bits 0:15 - Assert signal output when counter match this value

pub fn clr_cnt(&self) -> CLR_CNT_R

Bits 16:31 - Deassert signal output when counter match this value

impl R<u8, SIG_LOGIC_A>

pub fn variant(&self) -> Variant<u8, SIG_LOGIC_A>

Get enumerated values variant

pub fn is_dis(&self) -> bool

Checks if the value of the field is DIS

pub fn is_and(&self) -> bool

Checks if the value of the field is AND

pub fn is_or(&self) -> bool

Checks if the value of the field is OR

pub fn is_mask(&self) -> bool

Checks if the value of the field is MASK

impl R<u8, SIG_ANOTHER_A>

pub fn variant(&self) -> Variant<u8, SIG_ANOTHER_A>

Get enumerated values variant

pub fn is_clear_using_mask(&self) -> bool

Checks if the value of the field is CLEAR_USING_MASK

impl R<u32, Reg<u32, _PIGEON_11_2>>

pub fn sig_logic(&self) -> SIG_LOGIC_R

Bits 0:3 - Logic operation with another signal: DIS/AND/OR/COND

pub fn sig_another(&self) -> SIG_ANOTHER_R

Bits 4:8 - Select another signal for logic operation or as mask or counter tick event

impl R<u32, Reg<u32, _LUT_CTRL>>

pub fn lut_bypass(&self) -> LUT_BYPASS_R

Bit 0 - Setting this bit will bypass the LUT memory resource completely

impl R<u32, Reg<u32, _LUT0_ADDR>>

pub fn addr(&self) -> ADDR_R

Bits 0:7 - LUT indexed address pointer

impl R<u32, Reg<u32, _LUT0_DATA>>

pub fn data(&self) -> DATA_R

Bits 0:31 - Writing this field will load 4 bytes, aligned to four byte boundaries, of data indexed by the ADDR field of the REG_LUT_CTRL register

impl R<u32, Reg<u32, _LUT1_ADDR>>

pub fn addr(&self) -> ADDR_R

Bits 0:7 - LUT indexed address pointer

impl R<u32, Reg<u32, _LUT1_DATA>>

pub fn data(&self) -> DATA_R

Bits 0:31 - Writing this field will load 4 bytes, aligned to four byte boundaries, of data indexed by the ADDR field of the REG_LUT_CTRL register

Trait Implementations

impl<U, T, FI> PartialEq<FI> for R<U, T> where
    U: PartialEq,
    FI: Copy + Into<U>, 

fn eq(&self, other: &FI) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]fn ne(&self, other: &Rhs) -> bool

This method tests for !=.