Struct imxrt1062_gpt1::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _CR>>

pub fn en(&mut self) -> EN_W

Bit 0 - GPT Enable

pub fn enmod(&mut self) -> ENMOD_W

Bit 1 - GPT Enable mode

pub fn dbgen(&mut self) -> DBGEN_W

Bit 2 - GPT debug mode enable

pub fn waiten(&mut self) -> WAITEN_W

Bit 3 - GPT Wait Mode enable

pub fn dozeen(&mut self) -> DOZEEN_W

Bit 4 - GPT Doze Mode Enable

pub fn stopen(&mut self) -> STOPEN_W

Bit 5 - GPT Stop Mode enable

pub fn clksrc(&mut self) -> CLKSRC_W

Bits 6:8 - Clock Source select

pub fn frr(&mut self) -> FRR_W

Bit 9 - Free-Run or Restart mode

pub fn en_24m(&mut self) -> EN_24M_W

Bit 10 - Enable 24 MHz clock input from crystal

pub fn swr(&mut self) -> SWR_W

Bit 15 - Software reset

pub fn im1(&mut self) -> IM1_W

Bits 16:17 - See IM2

pub fn im2(&mut self) -> IM2_W

Bits 18:19 - IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event

pub fn om1(&mut self) -> OM1_W

Bits 20:22 - See OM3

pub fn om2(&mut self) -> OM2_W

Bits 23:25 - See OM3

pub fn om3(&mut self) -> OM3_W

Bits 26:28 - OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode

pub fn fo1(&mut self) -> FO1_W

Bit 29 - See F03

pub fn fo2(&mut self) -> FO2_W

Bit 30 - See F03

pub fn fo3(&mut self) -> FO3_W

Bit 31 - FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register)

impl W<u32, Reg<u32, _PR>>

pub fn prescaler(&mut self) -> PRESCALER_W

Bits 0:11 - Prescaler bits

pub fn prescaler24m(&mut self) -> PRESCALER24M_W

Bits 12:15 - Prescaler bits

impl W<u32, Reg<u32, _SR>>

pub fn of1(&mut self) -> OF1_W

Bit 0 - See OF3

pub fn of2(&mut self) -> OF2_W

Bit 1 - See OF3

pub fn of3(&mut self) -> OF3_W

Bit 2 - OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OFn bit indicates that a compare event has occurred on Output Compare channel n

pub fn if1(&mut self) -> IF1_W

Bit 3 - See IF2

pub fn if2(&mut self) -> IF2_W

Bit 4 - IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn bit indicates that a capture event has occurred on Input Capture channel n

pub fn rov(&mut self) -> ROV_W

Bit 5 - Rollover Flag

impl W<u32, Reg<u32, _IR>>

pub fn of1ie(&mut self) -> OF1IE_W

Bit 0 - See OF3IE

pub fn of2ie(&mut self) -> OF2IE_W

Bit 1 - See OF3IE

pub fn of3ie(&mut self) -> OF3IE_W

Bit 2 - OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt

pub fn if1ie(&mut self) -> IF1IE_W

Bit 3 - See IF2IE

pub fn if2ie(&mut self) -> IF2IE_W

Bit 4 - IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable

pub fn rovie(&mut self) -> ROVIE_W

Bit 5 - Rollover Interrupt Enable. The ROVIE bit controls the Rollover interrupt.

impl W<u32, Reg<u32, _OCR1>>

pub fn comp(&mut self) -> COMP_W

Bits 0:31 - Compare Value

impl W<u32, Reg<u32, _OCR2>>

pub fn comp(&mut self) -> COMP_W

Bits 0:31 - Compare Value

impl W<u32, Reg<u32, _OCR3>>

pub fn comp(&mut self) -> COMP_W

Bits 0:31 - Compare Value