Struct imxrt1062_flexspi::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _MCR0>>

pub fn swreset(&mut self) -> SWRESET_W

Bit 0 - Software Reset

pub fn mdis(&mut self) -> MDIS_W

Bit 1 - Module Disable

pub fn rxclksrc(&mut self) -> RXCLKSRC_W

Bits 4:5 - Sample Clock source selection for Flash Reading

pub fn ardfen(&mut self) -> ARDFEN_W

Bit 6 - Enable AHB bus Read Access to IP RX FIFO.

pub fn atdfen(&mut self) -> ATDFEN_W

Bit 7 - Enable AHB bus Write Access to IP TX FIFO.

pub fn hsen(&mut self) -> HSEN_W

Bit 11 - Half Speed Serial Flash access Enable.

pub fn dozeen(&mut self) -> DOZEEN_W

Bit 12 - Doze mode enable bit

pub fn combinationen(&mut self) -> COMBINATIONEN_W

Bit 13 - This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]).

pub fn sckfreerunen(&mut self) -> SCKFREERUNEN_W

Bit 14 - This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2).

pub fn ipgrantwait(&mut self) -> IPGRANTWAIT_W

Bits 16:23 - Time out wait cycle for IP command grant.

pub fn ahbgrantwait(&mut self) -> AHBGRANTWAIT_W

Bits 24:31 - Timeout wait cycle for AHB command grant.

impl W<u32, Reg<u32, _MCR1>>

pub fn ahbbuswait(&mut self) -> AHBBUSWAIT_W

Bits 0:15 - AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmited after AHBBUSWAIT * 1024 ahb clock cycles, AHB Bus will get an error response

pub fn seqwait(&mut self) -> SEQWAIT_W

Bits 16:31 - Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles

impl W<u32, Reg<u32, _MCR2>>

pub fn clrahbbufopt(&mut self) -> CLRAHBBUFOPT_W

Bit 11 - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.

pub fn clrlearnphase(&mut self) -> CLRLEARNPHASE_W

Bit 14 - The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately.

pub fn samedeviceen(&mut self) -> SAMEDEVICEEN_W

Bit 15 - All external devices are same devices (both in types and size) for A1/A2/B1/B2.

pub fn sckbdiffopt(&mut self) -> SCKBDIFFOPT_W

Bit 19 - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. After change the value of this feild, MCR0[SWRESET] should be set.

pub fn resumewait(&mut self) -> RESUMEWAIT_W

Bits 24:31 - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.

impl W<u32, Reg<u32, _AHBCR>>

pub fn aparen(&mut self) -> APAREN_W

Bit 0 - Parallel mode enabled for AHB triggered Command (both read and write) .

pub fn cachableen(&mut self) -> CACHABLEEN_W

Bit 3 - Enable AHB bus cachable read access support.

pub fn bufferableen(&mut self) -> BUFFERABLEEN_W

Bit 4 - Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write.

pub fn prefetchen(&mut self) -> PREFETCHEN_W

Bit 5 - AHB Read Prefetch Enable.

pub fn readaddropt(&mut self) -> READADDROPT_W

Bit 6 - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.

impl W<u32, Reg<u32, _INTEN>>

pub fn ipcmddoneen(&mut self) -> IPCMDDONEEN_W

Bit 0 - IP triggered Command Sequences Execution finished interrupt enable.

pub fn ipcmdgeen(&mut self) -> IPCMDGEEN_W

Bit 1 - IP triggered Command Sequences Grant Timeout interrupt enable.

pub fn ahbcmdgeen(&mut self) -> AHBCMDGEEN_W

Bit 2 - AHB triggered Command Sequences Grant Timeout interrupt enable.

pub fn ipcmderren(&mut self) -> IPCMDERREN_W

Bit 3 - IP triggered Command Sequences Error Detected interrupt enable.

pub fn ahbcmderren(&mut self) -> AHBCMDERREN_W

Bit 4 - AHB triggered Command Sequences Error Detected interrupt enable.

pub fn iprxwaen(&mut self) -> IPRXWAEN_W

Bit 5 - IP RX FIFO WaterMark available interrupt enable.

pub fn iptxween(&mut self) -> IPTXWEEN_W

Bit 6 - IP TX FIFO WaterMark empty interrupt enable.

pub fn sckstopbyrden(&mut self) -> SCKSTOPBYRDEN_W

Bit 8 - SCK is stopped during command sequence because Async RX FIFO full interrupt enable.

pub fn sckstopbywren(&mut self) -> SCKSTOPBYWREN_W

Bit 9 - SCK is stopped during command sequence because Async TX FIFO empty interrupt enable.

pub fn ahbbustimeouten(&mut self) -> AHBBUSTIMEOUTEN_W

Bit 10 - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.

pub fn seqtimeouten(&mut self) -> SEQTIMEOUTEN_W

Bit 11 - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.

impl W<u32, Reg<u32, _INTR>>

pub fn ipcmddone(&mut self) -> IPCMDDONE_W

Bit 0 - IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated.

pub fn ipcmdge(&mut self) -> IPCMDGE_W

Bit 1 - IP triggered Command Sequences Grant Timeout interrupt.

pub fn ahbcmdge(&mut self) -> AHBCMDGE_W

Bit 2 - AHB triggered Command Sequences Grant Timeout interrupt.

pub fn ipcmderr(&mut self) -> IPCMDERR_W

Bit 3 - IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all.

pub fn ahbcmderr(&mut self) -> AHBCMDERR_W

Bit 4 - AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all.

pub fn iprxwa(&mut self) -> IPRXWA_W

Bit 5 - IP RX FIFO watermark available interrupt.

pub fn iptxwe(&mut self) -> IPTXWE_W

Bit 6 - IP TX FIFO watermark empty interrupt.

pub fn sckstopbyrd(&mut self) -> SCKSTOPBYRD_W

Bit 8 - SCK is stopped during command sequence because Async RX FIFO full interrupt.

pub fn sckstopbywr(&mut self) -> SCKSTOPBYWR_W

Bit 9 - SCK is stopped during command sequence because Async TX FIFO empty interrupt.

pub fn ahbbustimeout(&mut self) -> AHBBUSTIMEOUT_W

Bit 10 - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.

pub fn seqtimeout(&mut self) -> SEQTIMEOUT_W

Bit 11 - Sequence execution timeout interrupt.

impl W<u32, Reg<u32, _LUTKEY>>

pub fn key(&mut self) -> KEY_W

Bits 0:31 - The Key to lock or unlock LUT.

impl W<u32, Reg<u32, _LUTCR>>

pub fn lock(&mut self) -> LOCK_W

Bit 0 - Lock LUT

pub fn unlock(&mut self) -> UNLOCK_W

Bit 1 - Unlock LUT

impl W<u32, Reg<u32, _AHBRXBUF0CR0>>

pub fn bufsz(&mut self) -> BUFSZ_W

Bits 0:7 - AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details.

pub fn mstrid(&mut self) -> MSTRID_W

Bits 16:19 - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation.

pub fn priority(&mut self) -> PRIORITY_W

Bits 24:25 - This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details.

pub fn prefetchen(&mut self) -> PREFETCHEN_W

Bit 31 - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.

impl W<u32, Reg<u32, _AHBRXBUF1CR0>>

pub fn bufsz(&mut self) -> BUFSZ_W

Bits 0:7 - AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details.

pub fn mstrid(&mut self) -> MSTRID_W

Bits 16:19 - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation.

pub fn priority(&mut self) -> PRIORITY_W

Bits 24:25 - This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details.

pub fn prefetchen(&mut self) -> PREFETCHEN_W

Bit 31 - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.

impl W<u32, Reg<u32, _AHBRXBUF2CR0>>

pub fn bufsz(&mut self) -> BUFSZ_W

Bits 0:7 - AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details.

pub fn mstrid(&mut self) -> MSTRID_W

Bits 16:19 - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation.

pub fn priority(&mut self) -> PRIORITY_W

Bits 24:25 - This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details.

pub fn prefetchen(&mut self) -> PREFETCHEN_W

Bit 31 - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.

impl W<u32, Reg<u32, _AHBRXBUF3CR0>>

pub fn bufsz(&mut self) -> BUFSZ_W

Bits 0:7 - AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details.

pub fn mstrid(&mut self) -> MSTRID_W

Bits 16:19 - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation.

pub fn priority(&mut self) -> PRIORITY_W

Bits 24:25 - This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details.

pub fn prefetchen(&mut self) -> PREFETCHEN_W

Bit 31 - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.

impl W<u32, Reg<u32, _FLSHA1CR0>>

pub fn flshsz(&mut self) -> FLSHSZ_W

Bits 0:22 - Flash Size in KByte.

impl W<u32, Reg<u32, _FLSHA2CR0>>

pub fn flshsz(&mut self) -> FLSHSZ_W

Bits 0:22 - Flash Size in KByte.

impl W<u32, Reg<u32, _FLSHB1CR0>>

pub fn flshsz(&mut self) -> FLSHSZ_W

Bits 0:22 - Flash Size in KByte.

impl W<u32, Reg<u32, _FLSHB2CR0>>

pub fn flshsz(&mut self) -> FLSHSZ_W

Bits 0:22 - Flash Size in KByte.

impl W<u32, Reg<u32, _FLSHCR1>>

pub fn tcss(&mut self) -> TCSS_W

Bits 0:4 - Serial Flash CS setup time.

pub fn tcsh(&mut self) -> TCSH_W

Bits 5:9 - Serial Flash CS Hold time.

pub fn wa(&mut self) -> WA_W

Bit 10 - Word Addressable.

pub fn cas(&mut self) -> CAS_W

Bits 11:14 - Column Address Size.

pub fn csintervalunit(&mut self) -> CSINTERVALUNIT_W

Bit 15 - CS interval unit

pub fn csinterval(&mut self) -> CSINTERVAL_W

Bits 16:31 - This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0.

impl W<u32, Reg<u32, _FLSHCR2>>

pub fn ardseqid(&mut self) -> ARDSEQID_W

Bits 0:3 - Sequence Index for AHB Read triggered Command in LUT.

pub fn ardseqnum(&mut self) -> ARDSEQNUM_W

Bits 5:7 - Sequence Number for AHB Read triggered Command in LUT.

pub fn awrseqid(&mut self) -> AWRSEQID_W

Bits 8:11 - Sequence Index for AHB Write triggered Command.

pub fn awrseqnum(&mut self) -> AWRSEQNUM_W

Bits 13:15 - Sequence Number for AHB Write triggered Command.

pub fn awrwait(&mut self) -> AWRWAIT_W

Bits 16:27 - For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface

pub fn awrwaitunit(&mut self) -> AWRWAITUNIT_W

Bits 28:30 - AWRWAIT unit

pub fn clrinstrptr(&mut self) -> CLRINSTRPTR_W

Bit 31 - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details.

impl W<u32, Reg<u32, _FLSHCR4>>

pub fn wmopt1(&mut self) -> WMOPT1_W

Bit 0 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.

pub fn wmena(&mut self) -> WMENA_W

Bit 2 - Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set.

pub fn wmenb(&mut self) -> WMENB_W

Bit 3 - Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set.

impl W<u32, Reg<u32, _IPCR0>>

pub fn sfar(&mut self) -> SFAR_W

Bits 0:31 - Serial Flash Address for IP command.

impl W<u32, Reg<u32, _IPCR1>>

pub fn idatsz(&mut self) -> IDATSZ_W

Bits 0:15 - Flash Read/Program Data Size (in Bytes) for IP command.

pub fn iseqid(&mut self) -> ISEQID_W

Bits 16:19 - Sequence Index in LUT for IP command.

pub fn iseqnum(&mut self) -> ISEQNUM_W

Bits 24:26 - Sequence Number for IP command: ISEQNUM+1.

pub fn iparen(&mut self) -> IPAREN_W

Bit 31 - Parallel mode Enabled for IP command.

impl W<u32, Reg<u32, _IPCMD>>

pub fn trg(&mut self) -> TRG_W

Bit 0 - Setting this bit will trigger an IP Command.

impl W<u32, Reg<u32, _IPRXFCR>>

pub fn clriprxf(&mut self) -> CLRIPRXF_W

Bit 0 - Clear all valid data entries in IP RX FIFO.

pub fn rxdmaen(&mut self) -> RXDMAEN_W

Bit 1 - IP RX FIFO reading by DMA enabled.

pub fn rxwmrk(&mut self) -> RXWMRK_W

Bits 2:5 - Watermark level is (RXWMRK+1)*64 Bits.

impl W<u32, Reg<u32, _IPTXFCR>>

pub fn clriptxf(&mut self) -> CLRIPTXF_W

Bit 0 - Clear all valid data entries in IP TX FIFO.

pub fn txdmaen(&mut self) -> TXDMAEN_W

Bit 1 - IP TX FIFO filling by DMA enabled.

pub fn txwmrk(&mut self) -> TXWMRK_W

Bits 2:5 - Watermark level is (TXWMRK+1)*64 Bits.

impl W<u32, Reg<u32, _DLLCR>>

pub fn dllen(&mut self) -> DLLEN_W

Bit 0 - DLL calibration enable.

pub fn dllreset(&mut self) -> DLLRESET_W

Bit 1 - Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation).

pub fn slvdlytarget(&mut self) -> SLVDLYTARGET_W

Bits 3:6 - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial clock).

pub fn ovrden(&mut self) -> OVRDEN_W

Bit 8 - Slave clock delay line delay cell number selection override enable.

pub fn ovrdval(&mut self) -> OVRDVAL_W

Bits 9:14 - Slave clock delay line delay cell number selection override value.

impl W<u32, Reg<u32, _TFDR>>

pub fn txdata(&mut self) -> TXDATA_W

Bits 0:31 - TX Data

impl W<u32, Reg<u32, _LUT>>

pub fn operand0(&mut self) -> OPERAND0_W

Bits 0:7 - OPERAND0

pub fn num_pads0(&mut self) -> NUM_PADS0_W

Bits 8:9 - NUM_PADS0

pub fn opcode0(&mut self) -> OPCODE0_W

Bits 10:15 - OPCODE

pub fn operand1(&mut self) -> OPERAND1_W

Bits 16:23 - OPERAND1

pub fn num_pads1(&mut self) -> NUM_PADS1_W

Bits 24:25 - NUM_PADS1

pub fn opcode1(&mut self) -> OPCODE1_W

Bits 26:31 - OPCODE1