Struct imxrt1062_enet::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _EIR>>

pub fn ts_timer(&mut self) -> TS_TIMER_W

Bit 15 - Timestamp Timer

pub fn ts_avail(&mut self) -> TS_AVAIL_W

Bit 16 - Transmit Timestamp Available

pub fn wakeup(&mut self) -> WAKEUP_W

Bit 17 - Node Wakeup Request Indication

pub fn plr(&mut self) -> PLR_W

Bit 18 - Payload Receive Error

pub fn un(&mut self) -> UN_W

Bit 19 - Transmit FIFO Underrun

pub fn rl(&mut self) -> RL_W

Bit 20 - Collision Retry Limit

pub fn lc(&mut self) -> LC_W

Bit 21 - Late Collision

pub fn eberr(&mut self) -> EBERR_W

Bit 22 - Ethernet Bus Error

pub fn mii(&mut self) -> MII_W

Bit 23 - MII Interrupt.

pub fn rxb(&mut self) -> RXB_W

Bit 24 - Receive Buffer Interrupt

pub fn rxf(&mut self) -> RXF_W

Bit 25 - Receive Frame Interrupt

pub fn txb(&mut self) -> TXB_W

Bit 26 - Transmit Buffer Interrupt

pub fn txf(&mut self) -> TXF_W

Bit 27 - Transmit Frame Interrupt

pub fn gra(&mut self) -> GRA_W

Bit 28 - Graceful Stop Complete

pub fn babt(&mut self) -> BABT_W

Bit 29 - Babbling Transmit Error

pub fn babr(&mut self) -> BABR_W

Bit 30 - Babbling Receive Error

impl W<u32, Reg<u32, _EIMR>>

pub fn ts_timer(&mut self) -> TS_TIMER_W

Bit 15 - TS_TIMER Interrupt Mask

pub fn ts_avail(&mut self) -> TS_AVAIL_W

Bit 16 - TS_AVAIL Interrupt Mask

pub fn wakeup(&mut self) -> WAKEUP_W

Bit 17 - WAKEUP Interrupt Mask

pub fn plr(&mut self) -> PLR_W

Bit 18 - PLR Interrupt Mask

pub fn un(&mut self) -> UN_W

Bit 19 - UN Interrupt Mask

pub fn rl(&mut self) -> RL_W

Bit 20 - RL Interrupt Mask

pub fn lc(&mut self) -> LC_W

Bit 21 - LC Interrupt Mask

pub fn eberr(&mut self) -> EBERR_W

Bit 22 - EBERR Interrupt Mask

pub fn mii(&mut self) -> MII_W

Bit 23 - MII Interrupt Mask

pub fn rxb(&mut self) -> RXB_W

Bit 24 - RXB Interrupt Mask

pub fn rxf(&mut self) -> RXF_W

Bit 25 - RXF Interrupt Mask

pub fn txb(&mut self) -> TXB_W

Bit 26 - TXB Interrupt Mask

pub fn txf(&mut self) -> TXF_W

Bit 27 - TXF Interrupt Mask

pub fn gra(&mut self) -> GRA_W

Bit 28 - GRA Interrupt Mask

pub fn babt(&mut self) -> BABT_W

Bit 29 - BABT Interrupt Mask

pub fn babr(&mut self) -> BABR_W

Bit 30 - BABR Interrupt Mask

impl W<u32, Reg<u32, _RDAR>>

pub fn rdar(&mut self) -> RDAR_W

Bit 24 - Receive Descriptor Active

impl W<u32, Reg<u32, _TDAR>>

pub fn tdar(&mut self) -> TDAR_W

Bit 24 - Transmit Descriptor Active

impl W<u32, Reg<u32, _ECR>>

pub fn reset(&mut self) -> RESET_W

Bit 0 - Ethernet MAC Reset

pub fn etheren(&mut self) -> ETHEREN_W

Bit 1 - Ethernet Enable

pub fn magicen(&mut self) -> MAGICEN_W

Bit 2 - Magic Packet Detection Enable

pub fn sleep(&mut self) -> SLEEP_W

Bit 3 - Sleep Mode Enable

pub fn en1588(&mut self) -> EN1588_W

Bit 4 - EN1588 Enable

pub fn dbgen(&mut self) -> DBGEN_W

Bit 6 - Debug Enable

pub fn dbswp(&mut self) -> DBSWP_W

Bit 8 - Descriptor Byte Swapping Enable

impl W<u32, Reg<u32, _MMFR>>

pub fn data(&mut self) -> DATA_W

Bits 0:15 - Management Frame Data

pub fn ta(&mut self) -> TA_W

Bits 16:17 - Turn Around

pub fn ra(&mut self) -> RA_W

Bits 18:22 - Register Address

pub fn pa(&mut self) -> PA_W

Bits 23:27 - PHY Address

pub fn op(&mut self) -> OP_W

Bits 28:29 - Operation Code

pub fn st(&mut self) -> ST_W

Bits 30:31 - Start Of Frame Delimiter

impl W<u32, Reg<u32, _MSCR>>

pub fn mii_speed(&mut self) -> MII_SPEED_W

Bits 1:6 - MII Speed

pub fn dis_pre(&mut self) -> DIS_PRE_W

Bit 7 - Disable Preamble

pub fn holdtime(&mut self) -> HOLDTIME_W

Bits 8:10 - Hold time On MDIO Output

impl W<u32, Reg<u32, _MIBC>>

pub fn mib_clear(&mut self) -> MIB_CLEAR_W

Bit 29 - MIB Clear

pub fn mib_dis(&mut self) -> MIB_DIS_W

Bit 31 - Disable MIB Logic

impl W<u32, Reg<u32, _RCR>>

pub fn loop_(&mut self) -> LOOP_W

Bit 0 - Internal Loopback

pub fn drt(&mut self) -> DRT_W

Bit 1 - Disable Receive On Transmit

pub fn mii_mode(&mut self) -> MII_MODE_W

Bit 2 - Media Independent Interface Mode

pub fn prom(&mut self) -> PROM_W

Bit 3 - Promiscuous Mode

pub fn bc_rej(&mut self) -> BC_REJ_W

Bit 4 - Broadcast Frame Reject

pub fn fce(&mut self) -> FCE_W

Bit 5 - Flow Control Enable

pub fn rmii_mode(&mut self) -> RMII_MODE_W

Bit 8 - RMII Mode Enable

pub fn rmii_10t(&mut self) -> RMII_10T_W

Bit 9 - Enables 10-Mbit/s mode of the RMII .

pub fn paden(&mut self) -> PADEN_W

Bit 12 - Enable Frame Padding Remove On Receive

pub fn paufwd(&mut self) -> PAUFWD_W

Bit 13 - Terminate/Forward Pause Frames

pub fn crcfwd(&mut self) -> CRCFWD_W

Bit 14 - Terminate/Forward Received CRC

pub fn cfen(&mut self) -> CFEN_W

Bit 15 - MAC Control Frame Enable

pub fn max_fl(&mut self) -> MAX_FL_W

Bits 16:29 - Maximum Frame Length

pub fn nlc(&mut self) -> NLC_W

Bit 30 - Payload Length Check Disable

impl W<u32, Reg<u32, _TCR>>

pub fn gts(&mut self) -> GTS_W

Bit 0 - Graceful Transmit Stop

pub fn fden(&mut self) -> FDEN_W

Bit 2 - Full-Duplex Enable

pub fn tfc_pause(&mut self) -> TFC_PAUSE_W

Bit 3 - Transmit Frame Control Pause

pub fn addsel(&mut self) -> ADDSEL_W

Bits 5:7 - Source MAC Address Select On Transmit

pub fn addins(&mut self) -> ADDINS_W

Bit 8 - Set MAC Address On Transmit

pub fn crcfwd(&mut self) -> CRCFWD_W

Bit 9 - Forward Frame From Application With CRC

impl W<u32, Reg<u32, _PALR>>

pub fn paddr1(&mut self) -> PADDR1_W

Bits 0:31 - Pause Address

impl W<u32, Reg<u32, _PAUR>>

pub fn paddr2(&mut self) -> PADDR2_W

Bits 16:31 - Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in PAUSE frames

impl W<u32, Reg<u32, _OPD>>

pub fn pause_dur(&mut self) -> PAUSE_DUR_W

Bits 0:15 - Pause Duration

impl W<u32, Reg<u32, _TXIC>>

pub fn ictt(&mut self) -> ICTT_W

Bits 0:15 - Interrupt coalescing timer threshold

pub fn icft(&mut self) -> ICFT_W

Bits 20:27 - Interrupt coalescing frame count threshold

pub fn iccs(&mut self) -> ICCS_W

Bit 30 - Interrupt Coalescing Timer Clock Source Select

pub fn icen(&mut self) -> ICEN_W

Bit 31 - Interrupt Coalescing Enable

impl W<u32, Reg<u32, _RXIC>>

pub fn ictt(&mut self) -> ICTT_W

Bits 0:15 - Interrupt coalescing timer threshold

pub fn icft(&mut self) -> ICFT_W

Bits 20:27 - Interrupt coalescing frame count threshold

pub fn iccs(&mut self) -> ICCS_W

Bit 30 - Interrupt Coalescing Timer Clock Source Select

pub fn icen(&mut self) -> ICEN_W

Bit 31 - Interrupt Coalescing Enable

impl W<u32, Reg<u32, _IAUR>>

pub fn iaddr1(&mut self) -> IADDR1_W

Bits 0:31 - Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address

impl W<u32, Reg<u32, _IALR>>

pub fn iaddr2(&mut self) -> IADDR2_W

Bits 0:31 - Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address

impl W<u32, Reg<u32, _GAUR>>

pub fn gaddr1(&mut self) -> GADDR1_W

Bits 0:31 - Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address

impl W<u32, Reg<u32, _GALR>>

pub fn gaddr2(&mut self) -> GADDR2_W

Bits 0:31 - Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address

impl W<u32, Reg<u32, _TFWR>>

pub fn tfwr(&mut self) -> TFWR_W

Bits 0:5 - Transmit FIFO Write

pub fn strfwd(&mut self) -> STRFWD_W

Bit 8 - Store And Forward Enable

impl W<u32, Reg<u32, _RDSR>>

pub fn r_des_start(&mut self) -> R_DES_START_W

Bits 3:31 - Pointer to the beginning of the receive buffer descriptor queue.

impl W<u32, Reg<u32, _TDSR>>

pub fn x_des_start(&mut self) -> X_DES_START_W

Bits 3:31 - Pointer to the beginning of the transmit buffer descriptor queue.

impl W<u32, Reg<u32, _MRBR>>

pub fn r_buf_size(&mut self) -> R_BUF_SIZE_W

Bits 4:13 - Receive buffer size in bytes

impl W<u32, Reg<u32, _RSFL>>

pub fn rx_section_full(&mut self) -> RX_SECTION_FULL_W

Bits 0:7 - Value Of Receive FIFO Section Full Threshold

impl W<u32, Reg<u32, _RSEM>>

pub fn rx_section_empty(&mut self) -> RX_SECTION_EMPTY_W

Bits 0:7 - Value Of The Receive FIFO Section Empty Threshold

pub fn stat_section_empty(&mut self) -> STAT_SECTION_EMPTY_W

Bits 16:20 - RX Status FIFO Section Empty Threshold

impl W<u32, Reg<u32, _RAEM>>

pub fn rx_almost_empty(&mut self) -> RX_ALMOST_EMPTY_W

Bits 0:7 - Value Of The Receive FIFO Almost Empty Threshold

impl W<u32, Reg<u32, _RAFL>>

pub fn rx_almost_full(&mut self) -> RX_ALMOST_FULL_W

Bits 0:7 - Value Of The Receive FIFO Almost Full Threshold

impl W<u32, Reg<u32, _TSEM>>

pub fn tx_section_empty(&mut self) -> TX_SECTION_EMPTY_W

Bits 0:7 - Value Of The Transmit FIFO Section Empty Threshold

impl W<u32, Reg<u32, _TAEM>>

pub fn tx_almost_empty(&mut self) -> TX_ALMOST_EMPTY_W

Bits 0:7 - Value of Transmit FIFO Almost Empty Threshold

impl W<u32, Reg<u32, _TAFL>>

pub fn tx_almost_full(&mut self) -> TX_ALMOST_FULL_W

Bits 0:7 - Value Of The Transmit FIFO Almost Full Threshold

impl W<u32, Reg<u32, _TIPG>>

pub fn ipg(&mut self) -> IPG_W

Bits 0:4 - Transmit Inter-Packet Gap

impl W<u32, Reg<u32, _FTRL>>

pub fn trunc_fl(&mut self) -> TRUNC_FL_W

Bits 0:13 - Frame Truncation Length

impl W<u32, Reg<u32, _TACC>>

pub fn shift16(&mut self) -> SHIFT16_W

Bit 0 - TX FIFO Shift-16

pub fn ipchk(&mut self) -> IPCHK_W

Bit 3 - Enables insertion of IP header checksum.

pub fn prochk(&mut self) -> PROCHK_W

Bit 4 - Enables insertion of protocol checksum.

impl W<u32, Reg<u32, _RACC>>

pub fn padrem(&mut self) -> PADREM_W

Bit 0 - Enable Padding Removal For Short IP Frames

pub fn ipdis(&mut self) -> IPDIS_W

Bit 1 - Enable Discard Of Frames With Wrong IPv4 Header Checksum

pub fn prodis(&mut self) -> PRODIS_W

Bit 2 - Enable Discard Of Frames With Wrong Protocol Checksum

pub fn linedis(&mut self) -> LINEDIS_W

Bit 6 - Enable Discard Of Frames With MAC Layer Errors

pub fn shift16(&mut self) -> SHIFT16_W

Bit 7 - RX FIFO Shift-16

impl W<u32, Reg<u32, _ATCR>>

pub fn en(&mut self) -> EN_W

Bit 0 - Enable Timer

pub fn offen(&mut self) -> OFFEN_W

Bit 2 - Enable One-Shot Offset Event

pub fn offrst(&mut self) -> OFFRST_W

Bit 3 - Reset Timer On Offset Event

pub fn peren(&mut self) -> PEREN_W

Bit 4 - Enable Periodical Event

pub fn pinper(&mut self) -> PINPER_W

Bit 7 - Enables event signal output assertion on period event

pub fn restart(&mut self) -> RESTART_W

Bit 9 - Reset Timer

pub fn capture(&mut self) -> CAPTURE_W

Bit 11 - Capture Timer Value

pub fn slave(&mut self) -> SLAVE_W

Bit 13 - Enable Timer Slave Mode

impl W<u32, Reg<u32, _ATVR>>

pub fn atime(&mut self) -> ATIME_W

Bits 0:31 - A write sets the timer

impl W<u32, Reg<u32, _ATOFF>>

pub fn offset(&mut self) -> OFFSET_W

Bits 0:31 - Offset value for one-shot event generation

impl W<u32, Reg<u32, _ATPER>>

pub fn period(&mut self) -> PERIOD_W

Bits 0:31 - Value for generating periodic events

impl W<u32, Reg<u32, _ATCOR>>

pub fn cor(&mut self) -> COR_W

Bits 0:30 - Correction Counter Wrap-Around Value

impl W<u32, Reg<u32, _ATINC>>

pub fn inc(&mut self) -> INC_W

Bits 0:6 - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds

pub fn inc_corr(&mut self) -> INC_CORR_W

Bits 8:14 - Correction Increment Value

impl W<u32, Reg<u32, _TGSR>>

pub fn tf0(&mut self) -> TF0_W

Bit 0 - Copy Of Timer Flag For Channel 0

pub fn tf1(&mut self) -> TF1_W

Bit 1 - Copy Of Timer Flag For Channel 1

pub fn tf2(&mut self) -> TF2_W

Bit 2 - Copy Of Timer Flag For Channel 2

pub fn tf3(&mut self) -> TF3_W

Bit 3 - Copy Of Timer Flag For Channel 3

impl W<u32, Reg<u32, _TCSR>>

pub fn tdre(&mut self) -> TDRE_W

Bit 0 - Timer DMA Request Enable

pub fn tmode(&mut self) -> TMODE_W

Bits 2:5 - Timer Mode

pub fn tie(&mut self) -> TIE_W

Bit 6 - Timer Interrupt Enable

pub fn tf(&mut self) -> TF_W

Bit 7 - Timer Flag

pub fn tpwc(&mut self) -> TPWC_W

Bits 11:15 - Timer PulseWidth Control

impl W<u32, Reg<u32, _TCCR>>

pub fn tcc(&mut self) -> TCC_W

Bits 0:31 - Timer Capture Compare