Struct imxrt1062_dcdc::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _REG0>>

pub fn pwd_zcd(&mut self) -> PWD_ZCD_W

Bit 0 - power down the zero cross detection function for discontinuous conductor mode

pub fn disable_auto_clk_switch(&mut self) -> DISABLE_AUTO_CLK_SWITCH_W

Bit 1 - Disable automatic clock switch from internal osc to xtal clock.

pub fn sel_clk(&mut self) -> SEL_CLK_W

Bit 2 - select 24 MHz Crystal clock for DCDC, when dcdc_disable_auto_clk_switch is set.

pub fn pwd_osc_int(&mut self) -> PWD_OSC_INT_W

Bit 3 - Power down internal osc. Only set this bit, when 24 MHz crystal osc is available

pub fn pwd_cur_sns_cmp(&mut self) -> PWD_CUR_SNS_CMP_W

Bit 4 - The power down signal of the current detector.

pub fn cur_sns_thrsh(&mut self) -> CUR_SNS_THRSH_W

Bits 5:7 - Set the threshold of current detector, if the peak current of the inductor exceeds the threshold, the current detector will assert

pub fn pwd_overcur_det(&mut self) -> PWD_OVERCUR_DET_W

Bit 8 - power down overcurrent detection comparator

pub fn overcur_trig_adj(&mut self) -> OVERCUR_TRIG_ADJ_W

Bits 9:10 - The threshold of over current detection in run mode and power save mode: run mode power save mode 0x0 1 A 0

pub fn pwd_cmp_batt_det(&mut self) -> PWD_CMP_BATT_DET_W

Bit 11 - set to "1" to power down the low voltage detection comparator

pub fn adj_poslimit_buck(&mut self) -> ADJ_POSLIMIT_BUCK_W

Bits 12:15 - adjust value to poslimit_buck register

pub fn en_lp_overload_sns(&mut self) -> EN_LP_OVERLOAD_SNS_W

Bit 16 - enable the overload detection in power save mode, if current is larger than the overloading threshold (typical value is 50 mA), DCDC will switch to the run mode automatically

pub fn pwd_high_volt_det(&mut self) -> PWD_HIGH_VOLT_DET_W

Bit 17 - power down overvoltage detection comparator

pub fn lp_overload_thrsh(&mut self) -> LP_OVERLOAD_THRSH_W

Bits 18:19 - the threshold of the counting number of charging times during the period that lp_overload_freq_sel sets in power save mode

pub fn lp_overload_freq_sel(&mut self) -> LP_OVERLOAD_FREQ_SEL_W

Bit 20 - the period of counting the charging times in power save mode 0: eight 32k cycle 1: sixteen 32k cycle

pub fn lp_high_hys(&mut self) -> LP_HIGH_HYS_W

Bit 21 - Adjust hysteretic value in low power from 12.5mV to 25mV

pub fn pwd_cmp_offset(&mut self) -> PWD_CMP_OFFSET_W

Bit 26 - power down output range comparator

pub fn xtalok_disable(&mut self) -> XTALOK_DISABLE_W

Bit 27 - 1'b1: Disable xtalok detection circuit 1'b0: Enable xtalok detection circuit

pub fn current_alert_reset(&mut self) -> CURRENT_ALERT_RESET_W

Bit 28 - reset current alert signal

pub fn xtal_24m_ok(&mut self) -> XTAL_24M_OK_W

Bit 29 - set to 1 to switch internal ring osc to xtal 24M

impl W<u32, Reg<u32, _REG1>>

pub fn reg_fbk_sel(&mut self) -> REG_FBK_SEL_W

Bits 7:8 - select the feedback point of the internal regulator

pub fn reg_rload_sw(&mut self) -> REG_RLOAD_SW_W

Bit 9 - control the load resistor of the internal regulator of DCDC, the load resistor is connected as default "1", and need set to "0" to disconnect the load resistor

pub fn lp_cmp_isrc_sel(&mut self) -> LP_CMP_ISRC_SEL_W

Bits 12:13 - set the current bias of low power comparator 0x0: 50 nA 0x1: 100 nA 0x2: 200 nA 0x3: 400 nA

pub fn loopctrl_hst_thresh(&mut self) -> LOOPCTRL_HST_THRESH_W

Bit 21 - increase the threshold detection for common mode analog comparator

pub fn loopctrl_en_hyst(&mut self) -> LOOPCTRL_EN_HYST_W

Bit 23 - Enable hysteresis in switching converter common mode analog comparators

pub fn vbg_trim(&mut self) -> VBG_TRIM_W

Bits 24:28 - trim bandgap voltage

impl W<u32, Reg<u32, _REG2>>

pub fn loopctrl_dc_c(&mut self) -> LOOPCTRL_DC_C_W

Bits 0:1 - Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter, and can be used to optimize efficiency and loop response

pub fn loopctrl_dc_r(&mut self) -> LOOPCTRL_DC_R_W

Bits 2:5 - Magnitude of proportional control parameter in the switching DC-DC converter control loop.

pub fn loopctrl_dc_ff(&mut self) -> LOOPCTRL_DC_FF_W

Bits 6:8 - Two's complement feed forward step in duty cycle in the switching DC-DC converter

pub fn loopctrl_en_rcscale(&mut self) -> LOOPCTRL_EN_RCSCALE_W

Bits 9:11 - Enable analog circuit of DC-DC converter to respond faster under transient load conditions.

pub fn loopctrl_rcscale_thrsh(&mut self) -> LOOPCTRL_RCSCALE_THRSH_W

Bit 12 - Increase the threshold detection for RC scale circuit.

pub fn loopctrl_hyst_sign(&mut self) -> LOOPCTRL_HYST_SIGN_W

Bit 13 - Invert the sign of the hysteresis in DC-DC analog comparators.

pub fn disable_pulse_skip(&mut self) -> DISABLE_PULSE_SKIP_W

Bit 27 - Set to "0" : stop charging if the duty cycle is lower than what set by dcdc_neglimit_in

pub fn dcm_set_ctrl(&mut self) -> DCM_SET_CTRL_W

Bit 28 - Set high to improve the transition from heavy load to light load

impl W<u32, Reg<u32, _REG3>>

pub fn trg(&mut self) -> TRG_W

Bits 0:4 - Target value of VDD_SOC, 25 mV each step 0x0: 0.8V 0xE: 1.15V 0x1F:1.575V

pub fn target_lp(&mut self) -> TARGET_LP_W

Bits 8:10 - Target value of standby (low power) mode 0x0: 0

pub fn minpwr_dc_halfclk(&mut self) -> MINPWR_DC_HALFCLK_W

Bit 24 - Set DCDC clock to half freqeuncy for continuous mode

pub fn misc_delay_timing(&mut self) -> MISC_DELAY_TIMING_W

Bit 27 - Ajust delay to reduce ground noise

pub fn misc_disablefet_logic(&mut self) -> MISC_DISABLEFET_LOGIC_W

Bit 28 - Reserved

pub fn disable_step(&mut self) -> DISABLE_STEP_W

Bit 30 - Disable stepping for the output VDD_SOC of DCDC