Struct imxrt1062_csi::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _CSICR1>>

pub fn pixel_bit(&mut self) -> PIXEL_BIT_W

Bit 0 - Pixel Bit

pub fn redge(&mut self) -> REDGE_W

Bit 1 - Valid Pixel Clock Edge Select

pub fn inv_pclk(&mut self) -> INV_PCLK_W

Bit 2 - Invert Pixel Clock Input

pub fn inv_data(&mut self) -> INV_DATA_W

Bit 3 - Invert Data Input. This bit enables or disables internal inverters on the data lines.

pub fn gclk_mode(&mut self) -> GCLK_MODE_W

Bit 4 - Gated Clock Mode Enable

pub fn clr_rxfifo(&mut self) -> CLR_RXFIFO_W

Bit 5 - Asynchronous RXFIFO Clear

pub fn clr_statfifo(&mut self) -> CLR_STATFIFO_W

Bit 6 - Asynchronous STATFIFO Clear

pub fn pack_dir(&mut self) -> PACK_DIR_W

Bit 7 - Data Packing Direction

pub fn fcc(&mut self) -> FCC_W

Bit 8 - FIFO Clear Control

pub fn ccir_en(&mut self) -> CCIR_EN_W

Bit 10 - CCIR656 Interface Enable

pub fn hsync_pol(&mut self) -> HSYNC_POL_W

Bit 11 - HSYNC Polarity Select

pub fn sof_inten(&mut self) -> SOF_INTEN_W

Bit 16 - Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt.

pub fn sof_pol(&mut self) -> SOF_POL_W

Bit 17 - SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt.

pub fn rxff_inten(&mut self) -> RXFF_INTEN_W

Bit 18 - RxFIFO Full Interrupt Enable. This bit enables the RxFIFO full interrupt.

pub fn fb1_dma_done_inten(&mut self) -> FB1_DMA_DONE_INTEN_W

Bit 19 - Frame Buffer1 DMA Transfer Done Interrupt Enable

pub fn fb2_dma_done_inten(&mut self) -> FB2_DMA_DONE_INTEN_W

Bit 20 - Frame Buffer2 DMA Transfer Done Interrupt Enable

pub fn statff_inten(&mut self) -> STATFF_INTEN_W

Bit 21 - STATFIFO Full Interrupt Enable. This bit enables the STAT FIFO interrupt.

pub fn sff_dma_done_inten(&mut self) -> SFF_DMA_DONE_INTEN_W

Bit 22 - STATFIFO DMA Transfer Done Interrupt Enable

pub fn rf_or_inten(&mut self) -> RF_OR_INTEN_W

Bit 24 - RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt.

pub fn sf_or_inten(&mut self) -> SF_OR_INTEN_W

Bit 25 - STAT FIFO Overrun Interrupt Enable. This bit enables the STATFIFO overrun interrupt.

pub fn cof_int_en(&mut self) -> COF_INT_EN_W

Bit 26 - Change Of Image Field (COF) Interrupt Enable

pub fn ccir_mode(&mut self) -> CCIR_MODE_W

Bit 27 - CCIR Mode Select

pub fn pr_p_if_en(&mut self) -> PRP_IF_EN_W

Bit 28 - CSI-PrP Interface Enable

pub fn eof_int_en(&mut self) -> EOF_INT_EN_W

Bit 29 - End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt.

pub fn ext_vsync(&mut self) -> EXT_VSYNC_W

Bit 30 - External VSYNC Enable

pub fn swap16_en(&mut self) -> SWAP16_EN_W

Bit 31 - SWAP 16-Bit Enable

impl W<u32, Reg<u32, _CSICR2>>

pub fn hsc(&mut self) -> HSC_W

Bits 0:7 - Horizontal Skip Count

pub fn vsc(&mut self) -> VSC_W

Bits 8:15 - Vertical Skip Count. Contains the number of rows to skip. SCE must be 1, otherwise VSC is ignored.

pub fn lvrm(&mut self) -> LVRM_W

Bits 16:18 - Live View Resolution Mode. Selects the grid size used for live view resolution.

pub fn bts(&mut self) -> BTS_W

Bits 19:20 - Bayer Tile Start. Controls the Bayer pattern starting point.

pub fn sce(&mut self) -> SCE_W

Bit 23 - Skip Count Enable. Enables or disables the skip count feature.

pub fn afs(&mut self) -> AFS_W

Bits 24:25 - Auto Focus Spread. Selects which green pixels are used for auto-focus.

pub fn drm(&mut self) -> DRM_W

Bit 26 - Double Resolution Mode. Controls size of statistics grid.

pub fn dma_burst_type_sff(&mut self) -> DMA_BURST_TYPE_SFF_W

Bits 28:29 - Burst Type of DMA Transfer from STATFIFO. Selects the burst type of DMA transfer from STATFIFO.

pub fn dma_burst_type_rff(&mut self) -> DMA_BURST_TYPE_RFF_W

Bits 30:31 - Burst Type of DMA Transfer from RxFIFO. Selects the burst type of DMA transfer from RxFIFO.

impl W<u32, Reg<u32, _CSICR3>>

pub fn ecc_auto_en(&mut self) -> ECC_AUTO_EN_W

Bit 0 - Automatic Error Correction Enable

pub fn ecc_int_en(&mut self) -> ECC_INT_EN_W

Bit 1 - Error Detection Interrupt Enable

pub fn zero_pack_en(&mut self) -> ZERO_PACK_EN_W

Bit 2 - Dummy Zero Packing Enable

pub fn two_8bit_sensor(&mut self) -> TWO_8BIT_SENSOR_W

Bit 3 - Two 8-bit Sensor Mode

pub fn rx_ff_level(&mut self) -> RXFF_LEVEL_W

Bits 4:6 - RxFIFO Full Level

pub fn hresp_err_en(&mut self) -> HRESP_ERR_EN_W

Bit 7 - Hresponse Error Enable. This bit enables the hresponse error interrupt.

pub fn statff_level(&mut self) -> STATFF_LEVEL_W

Bits 8:10 - STATFIFO Full Level

pub fn dma_req_en_sff(&mut self) -> DMA_REQ_EN_SFF_W

Bit 11 - DMA Request Enable for STATFIFO

pub fn dma_req_en_rff(&mut self) -> DMA_REQ_EN_RFF_W

Bit 12 - DMA Request Enable for RxFIFO

pub fn dma_reflash_sff(&mut self) -> DMA_REFLASH_SFF_W

Bit 13 - Reflash DMA Controller for STATFIFO

pub fn dma_reflash_rff(&mut self) -> DMA_REFLASH_RFF_W

Bit 14 - Reflash DMA Controller for RxFIFO

pub fn frmcnt_rst(&mut self) -> FRMCNT_RST_W

Bit 15 - Frame Count Reset. Resets the Frame Counter. (Cleared automatically after reset is done)

pub fn frmcnt(&mut self) -> FRMCNT_W

Bits 16:31 - Frame Counter

impl W<u32, Reg<u32, _CSIRXCNT>>

pub fn rxcnt(&mut self) -> RXCNT_W

Bits 0:21 - RxFIFO Count

impl W<u32, Reg<u32, _CSISR>>

pub fn drdy(&mut self) -> DRDY_W

Bit 0 - RXFIFO Data Ready

pub fn ecc_int(&mut self) -> ECC_INT_W

Bit 1 - CCIR Error Interrupt

pub fn hresp_err_int(&mut self) -> HRESP_ERR_INT_W

Bit 7 - Hresponse Error Interrupt Status

pub fn cof_int(&mut self) -> COF_INT_W

Bit 13 - Change Of Field Interrupt Status

pub fn f1_int(&mut self) -> F1_INT_W

Bit 14 - CCIR Field 1 Interrupt Status

pub fn f2_int(&mut self) -> F2_INT_W

Bit 15 - CCIR Field 2 Interrupt Status

pub fn sof_int(&mut self) -> SOF_INT_W

Bit 16 - Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1)

pub fn eof_int(&mut self) -> EOF_INT_W

Bit 17 - End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1)

pub fn rx_ff_int(&mut self) -> RXFF_INT_W

Bit 18 - RXFIFO Full Interrupt Status

pub fn dma_tsf_done_fb1(&mut self) -> DMA_TSF_DONE_FB1_W

Bit 19 - DMA Transfer Done in Frame Buffer1

pub fn dma_tsf_done_fb2(&mut self) -> DMA_TSF_DONE_FB2_W

Bit 20 - DMA Transfer Done in Frame Buffer2

pub fn statff_int(&mut self) -> STATFF_INT_W

Bit 21 - STATFIFO Full Interrupt Status

pub fn dma_tsf_done_sff(&mut self) -> DMA_TSF_DONE_SFF_W

Bit 22 - DMA Transfer Done from StatFIFO

pub fn rf_or_int(&mut self) -> RF_OR_INT_W

Bit 24 - RxFIFO Overrun Interrupt Status

pub fn sf_or_int(&mut self) -> SF_OR_INT_W

Bit 25 - STATFIFO Overrun Interrupt Status

pub fn dma_field1_done(&mut self) -> DMA_FIELD1_DONE_W

Bit 26 - When DMA field 0 is complete, this bit will be set to 1(clear by writing 1).

pub fn dma_field0_done(&mut self) -> DMA_FIELD0_DONE_W

Bit 27 - When DMA field 0 is complete, this bit will be set to 1(clear by writing 1).

pub fn baseaddr_chhange_error(&mut self) -> BASEADDR_CHHANGE_ERROR_W

Bit 28 - When using base address switching enable, this bit will be 1 when switching occur before DMA complete

impl W<u32, Reg<u32, _CSIDMASA_STATFIFO>>

pub fn dma_start_addr_sff(&mut self) -> DMA_START_ADDR_SFF_W

Bits 2:31 - DMA Start Address for STATFIFO

impl W<u32, Reg<u32, _CSIDMATS_STATFIFO>>

pub fn dma_tsf_size_sff(&mut self) -> DMA_TSF_SIZE_SFF_W

Bits 0:31 - DMA Transfer Size for STATFIFO

impl W<u32, Reg<u32, _CSIDMASA_FB1>>

pub fn dma_start_addr_fb1(&mut self) -> DMA_START_ADDR_FB1_W

Bits 2:31 - DMA Start Address in Frame Buffer1

impl W<u32, Reg<u32, _CSIDMASA_FB2>>

pub fn dma_start_addr_fb2(&mut self) -> DMA_START_ADDR_FB2_W

Bits 2:31 - DMA Start Address in Frame Buffer2

impl W<u32, Reg<u32, _CSIFBUF_PARA>>

pub fn fbuf_stride(&mut self) -> FBUF_STRIDE_W

Bits 0:15 - Frame Buffer Parameter

pub fn deinterlace_stride(&mut self) -> DEINTERLACE_STRIDE_W

Bits 16:31 - DEINTERLACE_STRIDE is only used in the deinterlace mode

impl W<u32, Reg<u32, _CSIIMAG_PARA>>

pub fn image_height(&mut self) -> IMAGE_HEIGHT_W

Bits 0:15 - Image Height. Indicates how many pixels in a column of the image from the sensor.

pub fn image_width(&mut self) -> IMAGE_WIDTH_W

Bits 16:31 - Image Width

impl W<u32, Reg<u32, _CSICR18>>

pub fn deinterlace_en(&mut self) -> DEINTERLACE_EN_W

Bit 2 - This bit is used to select the output method When input is standard CCIR656 video.

pub fn parallel24_en(&mut self) -> PARALLEL24_EN_W

Bit 3 - When input is parallel rgb888/yuv444 24bit, this bit can be enabled.

pub fn baseaddr_switch_en(&mut self) -> BASEADDR_SWITCH_EN_W

Bit 4 - When this bit is enabled, CSI DMA will switch the base address according to BASEADDR_SWITCH_SEL rather than atomically by DMA completed

pub fn baseaddr_switch_sel(&mut self) -> BASEADDR_SWITCH_SEL_W

Bit 5 - CSI 2 base addresses switching method. When using this bit, BASEADDR_SWITCH_EN is 1.

pub fn field0_done_ie(&mut self) -> FIELD0_DONE_IE_W

Bit 6 - In interlace mode, fileld 0 means interrupt enabled.

pub fn dma_field1_done_ie(&mut self) -> DMA_FIELD1_DONE_IE_W

Bit 7 - When in interlace mode, field 1 done interrupt enable.

pub fn last_dma_req_sel(&mut self) -> LAST_DMA_REQ_SEL_W

Bit 8 - Choosing the last DMA request condition.

pub fn baseaddr_change_error_ie(&mut self) -> BASEADDR_CHANGE_ERROR_IE_W

Bit 9 - Base address change error interrupt enable signal.

pub fn rgb888a_format_sel(&mut self) -> RGB888A_FORMAT_SEL_W

Bit 10 - Output is 32-bit format.

pub fn ahb_hprot(&mut self) -> AHB_HPROT_W

Bits 12:15 - Hprot value in AHB bus protocol.

pub fn mask_option(&mut self) -> MASK_OPTION_W

Bits 18:19 - These bits used to choose the method to mask the CSI input.

pub fn csi_enable(&mut self) -> CSI_ENABLE_W

Bit 31 - CSI global enable signal

impl W<u32, Reg<u32, _CSICR19>>

pub fn dma_rfifo_highest_fifo_level(&mut self) -> DMA_RFIFO_HIGHEST_FIFO_LEVEL_W

Bits 0:7 - This byte stores the highest FIFO level achieved by CSI FIFO timely and will be clear by writing 8'ff to it