Enum imxrt1062_ccm::ccsr::PLL3_SW_CLK_SEL_A

pub enum PLL3_SW_CLK_SEL_A {
    PLL3_SW_CLK_SEL_0,
    PLL3_SW_CLK_SEL_1,
}

Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes.

Value on reset: 0

Variants

PLL3_SW_CLK_SEL_0

0: pll3_main_clk

PLL3_SW_CLK_SEL_1

1: pll3 bypass clock

Trait Implementations

impl Clone for PLL3_SW_CLK_SEL_A

fn clone(&self) -> PLL3_SW_CLK_SEL_A

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for PLL3_SW_CLK_SEL_A

impl Debug for PLL3_SW_CLK_SEL_A

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.

impl From<PLL3_SW_CLK_SEL_A> for bool

fn from(variant: PLL3_SW_CLK_SEL_A) -> Self

Performs the conversion.

impl PartialEq<PLL3_SW_CLK_SEL_A> for PLL3_SW_CLK_SEL_A

fn eq(&self, other: &PLL3_SW_CLK_SEL_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl StructuralPartialEq for PLL3_SW_CLK_SEL_A