Type Definition imxrt1062_ccm::ccgr0::W

type W = W<u32, CCGR0>;

Writer for register CCGR0

Methods

impl W

pub fn cg0(&mut self) -> CG0_W

Bits 0:1 - aips_tz1 clocks (aips_tz1_clk_enable)

pub fn cg1(&mut self) -> CG1_W

Bits 2:3 - aips_tz2 clocks (aips_tz2_clk_enable)

pub fn cg2(&mut self) -> CG2_W

Bits 4:5 - mqs clock ( mqs_hmclk_clock_enable)

pub fn cg3(&mut self) -> CG3_W

Bits 6:7 - flexspi_exsc clock (flexspi_exsc_clk_enable)

pub fn cg4(&mut self) -> CG4_W

Bits 8:9 - sim_m or sim_main register access clock (sim_m_mainclk_r_enable)

pub fn cg5(&mut self) -> CG5_W

Bits 10:11 - dcp clock (dcp_clk_enable)

pub fn cg6(&mut self) -> CG6_W

Bits 12:13 - lpuart3 clock (lpuart3_clk_enable)

pub fn cg7(&mut self) -> CG7_W

Bits 14:15 - can1 clock (can1_clk_enable)

pub fn cg8(&mut self) -> CG8_W

Bits 16:17 - can1_serial clock (can1_serial_clk_enable)

pub fn cg9(&mut self) -> CG9_W

Bits 18:19 - can2 clock (can2_clk_enable)

pub fn cg10(&mut self) -> CG10_W

Bits 20:21 - can2_serial clock (can2_serial_clk_enable)

pub fn cg11(&mut self) -> CG11_W

Bits 22:23 - trace clock (trace_clk_enable)

pub fn cg12(&mut self) -> CG12_W

Bits 24:25 - gpt2 bus clocks (gpt2_bus_clk_enable)

pub fn cg13(&mut self) -> CG13_W

Bits 26:27 - gpt2 serial clocks (gpt2_serial_clk_enable)

pub fn cg14(&mut self) -> CG14_W

Bits 28:29 - lpuart2 clock (lpuart2_clk_enable)

pub fn cg15(&mut self) -> CG15_W

Bits 30:31 - gpio2_clocks (gpio2_clk_enable)