[−][src]Module imxrt1062_ccm::cscdr1
CCM Serial Clock Divider Register 1
Structs
TRACE_PODF_W | Write proxy for field |
UART_CLK_PODF_W | Write proxy for field |
UART_CLK_SEL_W | Write proxy for field |
USDHC1_PODF_W | Write proxy for field |
USDHC2_PODF_W | Write proxy for field |
Enums
TRACE_PODF_A | Divider for trace clock. Divider should be updated when output clock is gated. |
UART_CLK_PODF_A | Divider for uart clock podf. |
UART_CLK_SEL_A | Selector for the UART clock multiplexor |
USDHC1_PODF_A | Divider for usdhc1 clock podf. Divider should be updated when output clock is gated. |
USDHC2_PODF_A | Divider for usdhc2 clock. Divider should be updated when output clock is gated. |
Type Definitions
R | Reader of register CSCDR1 |
TRACE_PODF_R | Reader of field |
UART_CLK_PODF_R | Reader of field |
UART_CLK_SEL_R | Reader of field |
USDHC1_PODF_R | Reader of field |
USDHC2_PODF_R | Reader of field |
W | Writer for register CSCDR1 |