Module imxrt_hal::lpspi

Low-power serial peripheral interface.

Lpspi implements select embedded HAL SPI traits for coordinating SPI I/O. When using the trait implementations, make sure that set_bit_order is correct for your device. These settings apply when the driver internally defines the transaction.

This driver also exposes the peripheral’s lower-level, hardware-dependent transaction interface. Create a Transaction, then enqueue_transaction before sending data with enqueue_data. When using the transaction interface, you’re responsible for serializing your data into u32 SPI words.

Chip selects (CS) for SPI peripherals

The iMXRT SPI peripherals have one or more peripheral-controlled chip selects (CS). Using the peripheral-controlled CS means that you do not need a GPIO to coordinate SPI operations. Blocking full-duplex transfers and writes will observe an asserted chip select while data frames are exchanged / written.

This driver generally assumes that you’re using the peripheral-controlled chip select. If you instead want to manage chip select in software, you should be able to multiplex your own pins, then construct the driver without_pins.

Example

Initialize an LPSPI with a 1MHz SCK. To understand how to configure the LPSPI peripheral clock, see the ccm::lpspi_clk documentation.

use imxrt_hal as hal;
use imxrt_ral as ral;
use embedded_hal::blocking::spi::Transfer;
use hal::lpspi::{Lpspi, Pins, SamplePoint};
use ral::lpspi::LPSPI4;

let mut pads = // Handle to all processor pads...

let spi_pins = Pins {
    sdo: pads.gpio_b0.p02,
    sdi: pads.gpio_b0.p01,
    sck: pads.gpio_b0.p03,
    pcs0: pads.gpio_b0.p00,
};

let mut spi4 = unsafe { LPSPI4::instance() };
let mut spi = Lpspi::new(
    spi4,
    spi_pins,
);

spi.disabled(|spi| {
    spi.set_clock_hz(LPSPI_CLK_HZ, 1_000_000);
    spi.set_sample_point(SamplePoint::Edge);
});

let mut buffer: [u8; 3] = [1, 2, 3];
spi.transfer(&mut buffer).ok()?;

let (spi4, pins) = spi.release();

// Re-construct without pins:
let mut spi = Lpspi::without_pins(spi4);

Limitations

Due to a hardware defect, this driver does not yet support the EH02 SPI transaction API. An early iteration of this driver reproduced the issue discussed in that forum. This driver may be able to work around the defect in software, but it hasn’t been explored.

Transaction exposes the continuous / continuing flags, so you’re free to model advanced transactions. However, keep in mind that disabling the receiver during a continuous transaction may not work as expected.

Structs

• Disabled
  An LPSPI peripheral which is temporarily disabled.
• FifoStatus
  The number of words in each FIFO.
• Interrupts
  Interrupt flags.
• Lpspi
  An LPSPI driver.
• Mode
  SPI mode
• Pins
  Pins for a LPSPI device.
• Status
  Status flags for the LPSPI interface.
• Transaction
  An LPSPI transaction definition.

Enums

• BitOrder
  Bit order.
• Direction
  Data direction.
• LpspiError
  Possible errors when interfacing the LPSPI.
• Phase
  Clock phase
• Polarity
  Clock polarity
• SamplePoint
  Receive sample point behavior.

Constants

• MODE_0
  Helper for CPOL = 0, CPHA = 0
• MODE_1
  Helper for CPOL = 0, CPHA = 1
• MODE_2
  Helper for CPOL = 1, CPHA = 0
• MODE_3
  Helper for CPOL = 1, CPHA = 1