Struct iced_x86::OpCodeInfo [−][src]
pub struct OpCodeInfo { /* fields omitted */ }
Expand description
Opcode info, returned by Code::op_code()
and Instruction::op_code()
Implementations
Gets the code
Examples
use iced_x86::*; let op_code = Code::EVEX_Vmovapd_ymm_k1z_ymmm256.op_code(); assert_eq!(op_code.code(), Code::EVEX_Vmovapd_ymm_k1z_ymmm256);
Gets the mnemonic
Examples
use iced_x86::*; let op_code = Code::EVEX_Vmovapd_ymm_k1z_ymmm256.op_code(); assert_eq!(op_code.mnemonic(), Mnemonic::Vmovapd);
Gets the encoding
Examples
use iced_x86::*; let op_code = Code::EVEX_Vmovapd_ymm_k1z_ymmm256.op_code(); assert_eq!(op_code.encoding(), EncodingKind::EVEX);
true
if an FWAIT
(9B
) instruction is added before the instruction
(Legacy encoding) Gets the required operand size (16,32,64) or 0
(Legacy encoding) Gets the required address size (16,32,64) or 0
(VEX/XOP/EVEX) L
/ L'L
value or default value if is_lig()
is true
(VEX/XOP/EVEX) W
value or default value if is_wig()
or is_wig32()
is true
(VEX/XOP/EVEX) true
if the L
/ L'L
fields are ignored.
EVEX: if reg-only ops and {er}
(EVEX.b
is set), L'L
is the rounding control and not ignored.
(VEX/XOP/EVEX) true
if the W
field is ignored in 16/32/64-bit modes
(VEX/XOP/EVEX) true
if the W
field is ignored in 16/32-bit modes (but not 64-bit mode)
(EVEX) Gets the tuple type
If it has a memory operand, gets the MemorySize
(non-broadcast memory type)
If it has a memory operand, gets the MemorySize
(broadcast memory type)
(EVEX) true
if the instruction supports broadcasting (EVEX.b
bit) (if it has a memory operand)
(EVEX) true
if the instruction supports rounding control
(EVEX) true
if the instruction supports suppress all exceptions
(EVEX) true
if an opmask register can be used
(EVEX) true
if a non-zero opmask register must be used
(EVEX) true
if the instruction supports zeroing masking (if one of the opmask registers K1
-K7
is used and destination operand is not a memory operand)
true
if the LOCK
(F0
) prefix can be used
true
if the XACQUIRE
(F2
) prefix can be used
true
if the XRELEASE
(F3
) prefix can be used
true
if the REP
/ REPE
(F3
) prefixes can be used
true
if the REPNE
(F2
) prefix can be used
true
if the BND
(F2
) prefix can be used
true
if the HINT-TAKEN
(3E
) and HINT-NOT-TAKEN
(2E
) prefixes can be used
true
if the NOTRACK
(3E
) prefix can be used
true
if rounding control is ignored (#UD is not generated)
true
if the LOCK
prefix can be used as an extra register bit (bit 3) to access registers 8-15 without a REX
prefix (eg. in 32-bit mode)
true
if the default operand size is 64 in 64-bit mode. A 66
prefix can switch to 16-bit operand size.
true
if the operand size is always 64 in 64-bit mode. A 66
prefix is ignored.
true
if the Intel decoder forces 64-bit operand size. A 66
prefix is ignored.
true
if it can only be executed when CPL=0
true
if the instruction accesses the I/O address space (eg. IN
, OUT
, INS
, OUTS
)
true
if it’s one of the many nop instructions (does not include FPU nop instructions, eg. FNOP
)
true
if it’s one of the many reserved nop instructions (eg. 0F0D
, 0F18-0F1F
)
true
if it’s a serializing instruction (Intel CPUs)
true
if it’s a serializing instruction (AMD CPUs)
true
if the instruction requires either CPL=0 or CPL<=3 depending on some CPU option (eg. CR4.TSD
, CR4.PCE
, CR4.UMIP
)
true
if it’s a tracked JMP
/CALL
indirect instruction (CET)
true
if it’s a non-temporal hint memory access (eg. MOVNTDQ
)
true
if it’s a no-wait FPU instruction, eg. FNINIT
true
if the mod bits are ignored and it’s assumed modrm[7:6] == 11b
true
if the index reg’s reg-num (vsib op) (if any) and register ops’ reg-nums must be unique,
eg. MNEMONIC XMM1,YMM1,[RAX+ZMM1*2]
is invalid. Registers = XMM
/YMM
/ZMM
/TMM
.
true
if it’s a privileged instruction (all CPL=0 instructions (except VMCALL
) and IOPL instructions IN
, INS
, OUT
, OUTS
, CLI
, STI
)
true
if it reads/writes too many registers
true
if it’s an instruction that implicitly uses the stack register, eg. CALL
, POP
, etc
true
if the instruction doesn’t read the segment register if it uses a memory operand
true
if the opmask register is read and written (instead of just read). This also implies that it can’t be K0
.
true
if it can be executed in protected mode
true
if it can be executed in virtual 8086 mode
true
if it can be executed in compatibility mode
true
if it can be used outside SMM
true
if it can be used in SMM
true
if it can be used outside an enclave (SGX)
true
if it can be used inside an enclave (SGX1)
true
if it can be used inside an enclave (SGX2)
true
if it can be used outside VMX operation
true
if it can be used in VMX root operation
true
if it can be used in VMX non-root operation
true
if it can be used outside SEAM
true
if it can be used in SEAM
true
if #UD is generated in TDX non-root operation
true
if #VE is generated in TDX non-root operation
true
if an exception (eg. #GP(0), #VE) may be generated in TDX non-root operation
(Intel VMX) true
if it causes a VM exit in VMX non-root operation
(Intel VMX) true
if it may cause a VM exit in VMX non-root operation
(Intel VMX) true
if it causes an SMM VM exit in VMX root operation (if dual-monitor treatment is activated)
(AMD SVM) true
if it causes a #VMEXIT in guest mode
(AMD SVM) true
if it may cause a #VMEXIT in guest mode
true
if it causes a TSX abort inside a TSX transaction
true
if it causes a TSX abort inside a TSX transaction depending on the implementation
true
if it may cause a TSX abort inside a TSX transaction depending on some condition
true
if it’s decoded by iced’s 16-bit Intel decoder
true
if it’s decoded by iced’s 32-bit Intel decoder
true
if it’s decoded by iced’s 64-bit Intel decoder
true
if it’s decoded by iced’s 16-bit AMD decoder
true
if it’s decoded by iced’s 32-bit AMD decoder
true
if it’s decoded by iced’s 64-bit AMD decoder
Gets the decoder option that’s needed to decode the instruction or DecoderOptions::NONE
.
The return value is a DecoderOptions
value.
Gets the opcode table
Gets the mandatory prefix
Gets the opcode byte(s). The low byte(s) of this value is the opcode. The length is in op_code_len()
.
It doesn’t include the table value, see table()
.
Examples
use iced_x86::*; assert_eq!(Code::Ffreep_sti.op_code().op_code(), 0xDFC0); assert_eq!(Code::Vmrunw.op_code().op_code(), 0x01D8); assert_eq!(Code::Sub_r8_rm8.op_code().op_code(), 0x2A); assert_eq!(Code::Cvtpi2ps_xmm_mmm64.op_code().op_code(), 0x2A);
Gets the length of the opcode bytes (op_code()
). The low bytes is the opcode value.
Examples
use iced_x86::*; assert_eq!(Code::Ffreep_sti.op_code().op_code_len(), 2); assert_eq!(Code::Vmrunw.op_code().op_code_len(), 2); assert_eq!(Code::Sub_r8_rm8.op_code().op_code_len(), 1); assert_eq!(Code::Cvtpi2ps_xmm_mmm64.op_code().op_code_len(), 1);
Group index (0-7) or -1. If it’s 0-7, it’s stored in the reg
field of the modrm
byte.
true
if it’s part of a modrm.rm group
Group index (0-7) or -1. If it’s 0-7, it’s stored in the rm
field of the modrm
byte.
Gets operand #0’s opkind
Gets operand #1’s opkind
Gets operand #2’s opkind
Gets operand #3’s opkind
Gets operand #4’s opkind
👎 Deprecated since 1.11.0: This method can panic, use try_op_kind() instead
This method can panic, use try_op_kind() instead
Gets all operand kinds
Checks if the instruction is available in 16-bit mode, 32-bit mode or 64-bit mode
Arguments
bitness
: 16, 32 or 64
Gets the opcode string, eg. VEX.128.66.0F38.W0 78 /r
, see also instruction_string()
Examples
use iced_x86::*; let op_code = Code::EVEX_Vmovapd_ymm_k1z_ymmm256.op_code(); assert_eq!(op_code.op_code_string(), "EVEX.256.66.0F.W1 28 /r");
Gets the instruction string, eg. VPBROADCASTB xmm1, xmm2/m8
, see also op_code_string()
Examples
use iced_x86::*; let op_code = Code::EVEX_Vmovapd_ymm_k1z_ymmm256.op_code(); assert_eq!(op_code.instruction_string(), "VMOVAPD ymm1 {k1}{z}, ymm2/m256");
Trait Implementations
Auto Trait Implementations
impl RefUnwindSafe for OpCodeInfo
impl Send for OpCodeInfo
impl Sync for OpCodeInfo
impl Unpin for OpCodeInfo
impl UnwindSafe for OpCodeInfo
Blanket Implementations
Mutably borrows from an owned value. Read more