[−][src]Struct gdbstub::arch::riscv::reg::RiscvCoreRegs

pub struct RiscvCoreRegs<U> {
    pub x: [U; 32],
    pub pc: U,
}

RISC-V Integer registers.

The register width is set to u32 or u64 based on the <U> type.

Useful links:

Fields

x: [U; 32]

General purpose registers (x0-x31)

pc: U

Program counter

Trait Implementations

impl<U: Default> Default for RiscvCoreRegs<U>[src]

impl<U> Registers for RiscvCoreRegs<U> where
    U: PrimInt + LeBytes + Default, [src]

type RegId = RiscvRegId

Register identifier for addressing single registers. Read more

Auto Trait Implementations

impl<U> RefUnwindSafe for RiscvCoreRegs<U> where
    U: RefUnwindSafe, 

impl<U> Send for RiscvCoreRegs<U> where
    U: Send, 

impl<U> Sync for RiscvCoreRegs<U> where
    U: Sync, 

impl<U> Unpin for RiscvCoreRegs<U> where
    U: Unpin, 

impl<U> UnwindSafe for RiscvCoreRegs<U> where
    U: UnwindSafe, 

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.