1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169

#[doc = "Register `TG` writer"]
pub type W = crate::W<TgSpec>;
#[doc = "Port toggle bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Tg0w {
    #[doc = "1: Toggles the corresponding OCTLx bit"]
    Toggle = 1,
}
impl From<Tg0w> for bool {
    #[inline(always)]
    fn from(variant: Tg0w) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `TG0` writer - Port toggle bit 0"]
pub type Tg0W<'a, REG> = crate::BitWriter<'a, REG, Tg0w>;
impl<'a, REG> Tg0W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    #[doc = "Toggles the corresponding OCTLx bit"]
    #[inline(always)]
    pub fn toggle(self) -> &'a mut crate::W<REG> {
        self.variant(Tg0w::Toggle)
    }
}
#[doc = "Field `TG1` writer - Port toggle bit 1"]
pub use Tg0W as Tg1W;
#[doc = "Field `TG2` writer - Port toggle bit 2"]
pub use Tg0W as Tg2W;
#[doc = "Field `TG3` writer - Port toggle bit 3"]
pub use Tg0W as Tg3W;
#[doc = "Field `TG4` writer - Port toggle bit 4"]
pub use Tg0W as Tg4W;
#[doc = "Field `TG5` writer - Port toggle bit 5"]
pub use Tg0W as Tg5W;
#[doc = "Field `TG6` writer - Port toggle bit 6"]
pub use Tg0W as Tg6W;
#[doc = "Field `TG7` writer - Port toggle bit 7"]
pub use Tg0W as Tg7W;
#[doc = "Field `TG8` writer - Port toggle bit 8"]
pub use Tg0W as Tg8W;
#[doc = "Field `TG9` writer - Port toggle bit 9"]
pub use Tg0W as Tg9W;
#[doc = "Field `TG10` writer - Port toggle bit 10"]
pub use Tg0W as Tg10W;
#[doc = "Field `TG11` writer - Port toggle bit 11"]
pub use Tg0W as Tg11W;
#[doc = "Field `TG12` writer - Port toggle bit 12"]
pub use Tg0W as Tg12W;
#[doc = "Field `TG13` writer - Port toggle bit 13"]
pub use Tg0W as Tg13W;
#[doc = "Field `TG14` writer - Port toggle bit 14"]
pub use Tg0W as Tg14W;
#[doc = "Field `TG15` writer - Port toggle bit 15"]
pub use Tg0W as Tg15W;
impl W {
    #[doc = "Bit 0 - Port toggle bit 0"]
    #[inline(always)]
    #[must_use]
    pub fn tg0(&mut self) -> Tg0W<TgSpec> {
        Tg0W::new(self, 0)
    }
    #[doc = "Bit 1 - Port toggle bit 1"]
    #[inline(always)]
    #[must_use]
    pub fn tg1(&mut self) -> Tg1W<TgSpec> {
        Tg1W::new(self, 1)
    }
    #[doc = "Bit 2 - Port toggle bit 2"]
    #[inline(always)]
    #[must_use]
    pub fn tg2(&mut self) -> Tg2W<TgSpec> {
        Tg2W::new(self, 2)
    }
    #[doc = "Bit 3 - Port toggle bit 3"]
    #[inline(always)]
    #[must_use]
    pub fn tg3(&mut self) -> Tg3W<TgSpec> {
        Tg3W::new(self, 3)
    }
    #[doc = "Bit 4 - Port toggle bit 4"]
    #[inline(always)]
    #[must_use]
    pub fn tg4(&mut self) -> Tg4W<TgSpec> {
        Tg4W::new(self, 4)
    }
    #[doc = "Bit 5 - Port toggle bit 5"]
    #[inline(always)]
    #[must_use]
    pub fn tg5(&mut self) -> Tg5W<TgSpec> {
        Tg5W::new(self, 5)
    }
    #[doc = "Bit 6 - Port toggle bit 6"]
    #[inline(always)]
    #[must_use]
    pub fn tg6(&mut self) -> Tg6W<TgSpec> {
        Tg6W::new(self, 6)
    }
    #[doc = "Bit 7 - Port toggle bit 7"]
    #[inline(always)]
    #[must_use]
    pub fn tg7(&mut self) -> Tg7W<TgSpec> {
        Tg7W::new(self, 7)
    }
    #[doc = "Bit 8 - Port toggle bit 8"]
    #[inline(always)]
    #[must_use]
    pub fn tg8(&mut self) -> Tg8W<TgSpec> {
        Tg8W::new(self, 8)
    }
    #[doc = "Bit 9 - Port toggle bit 9"]
    #[inline(always)]
    #[must_use]
    pub fn tg9(&mut self) -> Tg9W<TgSpec> {
        Tg9W::new(self, 9)
    }
    #[doc = "Bit 10 - Port toggle bit 10"]
    #[inline(always)]
    #[must_use]
    pub fn tg10(&mut self) -> Tg10W<TgSpec> {
        Tg10W::new(self, 10)
    }
    #[doc = "Bit 11 - Port toggle bit 11"]
    #[inline(always)]
    #[must_use]
    pub fn tg11(&mut self) -> Tg11W<TgSpec> {
        Tg11W::new(self, 11)
    }
    #[doc = "Bit 12 - Port toggle bit 12"]
    #[inline(always)]
    #[must_use]
    pub fn tg12(&mut self) -> Tg12W<TgSpec> {
        Tg12W::new(self, 12)
    }
    #[doc = "Bit 13 - Port toggle bit 13"]
    #[inline(always)]
    #[must_use]
    pub fn tg13(&mut self) -> Tg13W<TgSpec> {
        Tg13W::new(self, 13)
    }
    #[doc = "Bit 14 - Port toggle bit 14"]
    #[inline(always)]
    #[must_use]
    pub fn tg14(&mut self) -> Tg14W<TgSpec> {
        Tg14W::new(self, 14)
    }
    #[doc = "Bit 15 - Port toggle bit 15"]
    #[inline(always)]
    #[must_use]
    pub fn tg15(&mut self) -> Tg15W<TgSpec> {
        Tg15W::new(self, 15)
    }
}
#[doc = "Port bit toggle register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tg::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TgSpec;
impl crate::RegisterSpec for TgSpec {
    type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`tg::W`](W) writer structure"]
impl crate::Writable for TgSpec {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TG to value 0"]
impl crate::Resettable for TgSpec {
    const RESET_VALUE: u32 = 0;
}