Type Alias gd32f1::gd32f190::rcu::cfg0::W

pub type W = W<Cfg0Spec>;

Register CFG0 writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn scs(&mut self) -> ScsW<'_, Cfg0Spec>

Bits 0:1 - System clock switch

pub fn ahbpsc(&mut self) -> AhbpscW<'_, Cfg0Spec>

Bits 4:7 - AHB prescaler selection

pub fn apb1psc(&mut self) -> Apb1pscW<'_, Cfg0Spec>

Bits 8:10 - APB1 prescaler selection

pub fn apb2psc(&mut self) -> Apb2pscW<'_, Cfg0Spec>

Bits 11:13 - APB2 prescaler selection

pub fn adcpsc(&mut self) -> AdcpscW<'_, Cfg0Spec>

Bits 14:15 - ADC clock prescaler selection

pub fn pllsel(&mut self) -> PllselW<'_, Cfg0Spec>

Bit 16 - PLL Clock Source Selection

pub fn pllpredv(&mut self) -> PllpredvW<'_, Cfg0Spec>

Bit 17 - HXTAL divider for PLL source clock selection.

pub fn pllmf(&mut self) -> PllmfW<'_, Cfg0Spec>

Bits 18:21 - PLL multiply factor

pub fn ckoutsel(&mut self) -> CkoutselW<'_, Cfg0Spec>

Bits 24:26 - CK_OUT Clock Source Selection

pub fn pllmf_msb(&mut self) -> PllmfMsbW<'_, Cfg0Spec>

Bit 27 - Bit 4 of PLLMF register

pub fn ckoutdiv(&mut self) -> CkoutdivW<'_, Cfg0Spec>

Bits 28:30 - The CK_OUT divider which the CK_OUT frequency can be reduced

pub fn plldv(&mut self) -> PlldvW<'_, Cfg0Spec>

Bit 31 - The CK_PLL divide by 1 or 2 for CK_OUT