Type Alias gd32f1::gd32f190::rcu::cfg0::R

pub type R = R<Cfg0Spec>;

Register CFG0 reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn scs(&self) -> ScsR

Bits 0:1 - System clock switch

pub fn scss(&self) -> ScssR

Bits 2:3 - System clock switch status

pub fn ahbpsc(&self) -> AhbpscR

Bits 4:7 - AHB prescaler selection

pub fn apb1psc(&self) -> Apb1pscR

Bits 8:10 - APB1 prescaler selection

pub fn apb2psc(&self) -> Apb2pscR

Bits 11:13 - APB2 prescaler selection

pub fn adcpsc(&self) -> AdcpscR

Bits 14:15 - ADC clock prescaler selection

pub fn pllsel(&self) -> PllselR

Bit 16 - PLL Clock Source Selection

pub fn pllpredv(&self) -> PllpredvR

Bit 17 - HXTAL divider for PLL source clock selection.

pub fn pllmf(&self) -> PllmfR

Bits 18:21 - PLL multiply factor

pub fn ckoutsel(&self) -> CkoutselR

Bits 24:26 - CK_OUT Clock Source Selection

pub fn pllmf_msb(&self) -> PllmfMsbR

Bit 27 - Bit 4 of PLLMF register

pub fn ckoutdiv(&self) -> CkoutdivR

Bits 28:30 - The CK_OUT divider which the CK_OUT frequency can be reduced

pub fn plldv(&self) -> PlldvR

Bit 31 - The CK_PLL divide by 1 or 2 for CK_OUT