Type Alias gd32f1::gd32f190::opa_ivref::ivref_ctl::VptW

pub type VptW<'a, REG> = FieldWriterSafe<'a, REG, 5, Vpt>;

Field VPT writer - Voltage precision tirm

Aliased Type

struct VptW<'a, REG> { /* private fields */ }

Implementations

impl<'a, REG> VptW<'a, REG>

where REG: Writable + RegisterSpec, REG::Ux: From<u8>,

pub fn minus6_4(self) -> &'a mut W<REG>

Trim -6.4%

pub fn minus6_0(self) -> &'a mut W<REG>

Trim -6.0%

pub fn minus5_6(self) -> &'a mut W<REG>

Trim -5.6%

pub fn minus5_2(self) -> &'a mut W<REG>

Trim -5.2%

pub fn minus4_8(self) -> &'a mut W<REG>

Trim -4.8%

pub fn minus4_4(self) -> &'a mut W<REG>

Trim -4.4%

pub fn minus4_0(self) -> &'a mut W<REG>

Trim -4.0%

pub fn minus3_6(self) -> &'a mut W<REG>

Trim -3.6%

pub fn minus3_2(self) -> &'a mut W<REG>

Trim -3.2%

pub fn minus2_8(self) -> &'a mut W<REG>

Trim -2.8%

pub fn minus2_4(self) -> &'a mut W<REG>

Trim -2.4%

pub fn minus2_0(self) -> &'a mut W<REG>

Trim -2.0%

pub fn minus1_6(self) -> &'a mut W<REG>

Trim -1.6%

pub fn minus1_2(self) -> &'a mut W<REG>

Trim -1.2%

pub fn minus0_8(self) -> &'a mut W<REG>

Trim -0.8%

pub fn minus0_4(self) -> &'a mut W<REG>

Trim -0.4%

pub fn zero(self) -> &'a mut W<REG>

Trim 0%

pub fn plus0_4(self) -> &'a mut W<REG>

Trim +0.4%

pub fn plus0_8(self) -> &'a mut W<REG>

Trim +0.8%

pub fn plus1_2(self) -> &'a mut W<REG>

Trim +1.2%

pub fn plus1_6(self) -> &'a mut W<REG>

Trim +1.6%

pub fn plus2_4(self) -> &'a mut W<REG>

Trim +2.4%

pub fn plus2_0(self) -> &'a mut W<REG>

Trim +2.0%

pub fn plus2_8(self) -> &'a mut W<REG>

Trim +2.8%

pub fn plus3_2(self) -> &'a mut W<REG>

Trim +3.2%

pub fn plus3_6(self) -> &'a mut W<REG>

Trim +3.6%

pub fn plus4_0(self) -> &'a mut W<REG>

Trim +4.0%

pub fn plus4_4(self) -> &'a mut W<REG>

Trim +4.4%

pub fn plus4_8(self) -> &'a mut W<REG>

Trim +4.8%

pub fn plus5_2(self) -> &'a mut W<REG>

Trim +5.2%

pub fn plus5_6(self) -> &'a mut W<REG>

Trim +5.6%

pub fn plus6_0(self) -> &'a mut W<REG>

Trim +6.0%