Type Alias gd32f1::gd32f190::dma::ch0ctl::W

pub type W = W<Ch0ctlSpec>;

Register CH0CTL writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn chen(&mut self) -> ChenW<'_, Ch0ctlSpec>

Bit 0 - Channel enable

pub fn ftfie(&mut self) -> FtfieW<'_, Ch0ctlSpec>

Bit 1 - Enable bit for full transfer finish interrupt

pub fn htfie(&mut self) -> HtfieW<'_, Ch0ctlSpec>

Bit 2 - Enable bit for half transfer finish interrupt

pub fn errie(&mut self) -> ErrieW<'_, Ch0ctlSpec>

Bit 3 - Enable bit for tranfer access error interrupt

pub fn dir(&mut self) -> DirW<'_, Ch0ctlSpec>

Bit 4 - Transfer mode

pub fn cmen(&mut self) -> CmenW<'_, Ch0ctlSpec>

Bit 5 - Circular mode enable

pub fn pnaga(&mut self) -> PnagaW<'_, Ch0ctlSpec>

Bit 6 - Next address generation algorithm of peripheral

pub fn mnaga(&mut self) -> MnagaW<'_, Ch0ctlSpec>

Bit 7 - Next address generation algorithm of memory

pub fn pwidth(&mut self) -> PwidthW<'_, Ch0ctlSpec>

Bits 8:9 - Transfer data size of peripheral

pub fn mwidth(&mut self) -> MwidthW<'_, Ch0ctlSpec>

Bits 10:11 - Transfer data size of memory

pub fn prio(&mut self) -> PrioW<'_, Ch0ctlSpec>

Bits 12:13 - Priority Level of this channel

pub fn m2m(&mut self) -> M2mW<'_, Ch0ctlSpec>

Bit 14 - Memory to memory mode