Type Alias gd32f1::gd32f130::timer0::chctl0_output::Ch0comctlW

pub type Ch0comctlW<'a, REG> = FieldWriterSafe<'a, REG, 3, Ch0comctl>;

Field CH0COMCTL writer - Channel 0 compare output control

Aliased Type

struct Ch0comctlW<'a, REG> { /* private fields */ }

Implementations

impl<'a, REG> Ch0comctlW<'a, REG>

where REG: Writable + RegisterSpec, REG::Ux: From<u8>,

pub fn frozen(self) -> &'a mut W<REG>

The comparison between the output compare register CHyCV and the counter CNT has no effect on the outputs

pub fn active_on_match(self) -> &'a mut W<REG>

Set channel to active level on match. OxCPRE signal is forced high when the counter matches the capture/compare register CHyCV

pub fn inactive_on_match(self) -> &'a mut W<REG>

Set channel to inactive level on match. OxCPRE signal is forced low when the counter matches the capture/compare register CHyCV

pub fn toggle(self) -> &'a mut W<REG>

OxCPRE toggles when CNT=CHyCV

pub fn force_inactive(self) -> &'a mut W<REG>

OxCPRE is forced low

pub fn force_active(self) -> &'a mut W<REG>

OxCPRE is forced high

pub fn pwm_mode0(self) -> &'a mut W<REG>

In upcounting, channel is active as long as CNT<CHyCV else inactive. In downcounting, channel is inactive as long as CNT>CHyCV else active

pub fn pwm_mode1(self) -> &'a mut W<REG>

Inversely to PwmMode0