1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357

#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "0x00 - control register 0"]
    pub ctl0: CTL0,
    _reserved1: [u8; 2usize],
    #[doc = "0x04 - control register 1"]
    pub ctl1: CTL1,
    _reserved2: [u8; 2usize],
    #[doc = "0x08 - slave mode configuration register"]
    pub smcfg: SMCFG,
    _reserved3: [u8; 2usize],
    #[doc = "0x0c - DMA/Interrupt enable register"]
    pub dmainten: DMAINTEN,
    _reserved4: [u8; 2usize],
    #[doc = "0x10 - status register"]
    pub intf: INTF,
    _reserved5: [u8; 2usize],
    #[doc = "0x14 - Software event generation register"]
    pub swevg: SWEVG,
    _reserved6: [u8; 2usize],
    _reserved_6_chctl0: [u8; 2usize],
    _reserved7: [u8; 2usize],
    _reserved_7_chctl1: [u8; 2usize],
    _reserved8: [u8; 2usize],
    #[doc = "0x20 - Channel control register 2"]
    pub chctl2: CHCTL2,
    _reserved9: [u8; 2usize],
    #[doc = "0x24 - Counter register"]
    pub cnt: CNT,
    _reserved10: [u8; 2usize],
    #[doc = "0x28 - Prescaler register"]
    pub psc: PSC,
    _reserved11: [u8; 2usize],
    #[doc = "0x2c - auto-reload register"]
    pub car: CAR,
    _reserved12: [u8; 2usize],
    #[doc = "0x30 - repetition counter register"]
    pub crep: CREP,
    _reserved13: [u8; 2usize],
    #[doc = "0x34 - Channel 0 capture/compare value register"]
    pub ch0cv: CH0CV,
    _reserved14: [u8; 2usize],
    #[doc = "0x38 - Channel 1 capture/compare value register"]
    pub ch1cv: CH1CV,
    _reserved15: [u8; 2usize],
    #[doc = "0x3c - Channel 2 capture/compare value register"]
    pub ch2cv: CH2CV,
    _reserved16: [u8; 2usize],
    #[doc = "0x40 - Channel 3 capture/compare value register"]
    pub ch3cv: CH3CV,
    _reserved17: [u8; 2usize],
    #[doc = "0x44 - channel complementary protection register"]
    pub cchp: CCHP,
    _reserved18: [u8; 2usize],
    #[doc = "0x48 - DMA configuration register"]
    pub dmacfg: DMACFG,
    _reserved19: [u8; 2usize],
    #[doc = "0x4c - DMA Transfer buffer register"]
    pub dmatb: DMATB,
    _reserved20: [u8; 174usize],
    #[doc = "0xfc - Configuration register"]
    pub cfg: CFG,
}
impl RegisterBlock {
    #[doc = "0x18 - Channel control register 0 (input mode)"]
    #[inline(always)]
    pub fn chctl0_input(&self) -> &CHCTL0_INPUT {
        unsafe { &*(((self as *const Self) as *const u8).add(24usize) as *const CHCTL0_INPUT) }
    }
    #[doc = "0x18 - Channel control register 0 (input mode)"]
    #[inline(always)]
    pub fn chctl0_input_mut(&self) -> &mut CHCTL0_INPUT {
        unsafe { &mut *(((self as *const Self) as *mut u8).add(24usize) as *mut CHCTL0_INPUT) }
    }
    #[doc = "0x18 - Channel control register 0 (output mode)"]
    #[inline(always)]
    pub fn chctl0_output(&self) -> &CHCTL0_OUTPUT {
        unsafe { &*(((self as *const Self) as *const u8).add(24usize) as *const CHCTL0_OUTPUT) }
    }
    #[doc = "0x18 - Channel control register 0 (output mode)"]
    #[inline(always)]
    pub fn chctl0_output_mut(&self) -> &mut CHCTL0_OUTPUT {
        unsafe { &mut *(((self as *const Self) as *mut u8).add(24usize) as *mut CHCTL0_OUTPUT) }
    }
    #[doc = "0x1c - Channel control register 1 (input mode)"]
    #[inline(always)]
    pub fn chctl1_input(&self) -> &CHCTL1_INPUT {
        unsafe { &*(((self as *const Self) as *const u8).add(28usize) as *const CHCTL1_INPUT) }
    }
    #[doc = "0x1c - Channel control register 1 (input mode)"]
    #[inline(always)]
    pub fn chctl1_input_mut(&self) -> &mut CHCTL1_INPUT {
        unsafe { &mut *(((self as *const Self) as *mut u8).add(28usize) as *mut CHCTL1_INPUT) }
    }
    #[doc = "0x1c - Channel control register 1 (output mode)"]
    #[inline(always)]
    pub fn chctl1_output(&self) -> &CHCTL1_OUTPUT {
        unsafe { &*(((self as *const Self) as *const u8).add(28usize) as *const CHCTL1_OUTPUT) }
    }
    #[doc = "0x1c - Channel control register 1 (output mode)"]
    #[inline(always)]
    pub fn chctl1_output_mut(&self) -> &mut CHCTL1_OUTPUT {
        unsafe { &mut *(((self as *const Self) as *mut u8).add(28usize) as *mut CHCTL1_OUTPUT) }
    }
}
#[doc = "control register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl0](ctl0) module"]
pub type CTL0 = crate::Reg<u16, _CTL0>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CTL0;
#[doc = "`read()` method returns [ctl0::R](ctl0::R) reader structure"]
impl crate::Readable for CTL0 {}
#[doc = "`write(|w| ..)` method takes [ctl0::W](ctl0::W) writer structure"]
impl crate::Writable for CTL0 {}
#[doc = "control register 0"]
pub mod ctl0;
#[doc = "control register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl1](ctl1) module"]
pub type CTL1 = crate::Reg<u16, _CTL1>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CTL1;
#[doc = "`read()` method returns [ctl1::R](ctl1::R) reader structure"]
impl crate::Readable for CTL1 {}
#[doc = "`write(|w| ..)` method takes [ctl1::W](ctl1::W) writer structure"]
impl crate::Writable for CTL1 {}
#[doc = "control register 1"]
pub mod ctl1;
#[doc = "slave mode configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smcfg](smcfg) module"]
pub type SMCFG = crate::Reg<u16, _SMCFG>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _SMCFG;
#[doc = "`read()` method returns [smcfg::R](smcfg::R) reader structure"]
impl crate::Readable for SMCFG {}
#[doc = "`write(|w| ..)` method takes [smcfg::W](smcfg::W) writer structure"]
impl crate::Writable for SMCFG {}
#[doc = "slave mode configuration register"]
pub mod smcfg;
#[doc = "DMA/Interrupt enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmainten](dmainten) module"]
pub type DMAINTEN = crate::Reg<u16, _DMAINTEN>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _DMAINTEN;
#[doc = "`read()` method returns [dmainten::R](dmainten::R) reader structure"]
impl crate::Readable for DMAINTEN {}
#[doc = "`write(|w| ..)` method takes [dmainten::W](dmainten::W) writer structure"]
impl crate::Writable for DMAINTEN {}
#[doc = "DMA/Interrupt enable register"]
pub mod dmainten;
#[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intf](intf) module"]
pub type INTF = crate::Reg<u16, _INTF>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _INTF;
#[doc = "`read()` method returns [intf::R](intf::R) reader structure"]
impl crate::Readable for INTF {}
#[doc = "`write(|w| ..)` method takes [intf::W](intf::W) writer structure"]
impl crate::Writable for INTF {}
#[doc = "status register"]
pub mod intf;
#[doc = "Software event generation register\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swevg](swevg) module"]
pub type SWEVG = crate::Reg<u16, _SWEVG>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _SWEVG;
#[doc = "`write(|w| ..)` method takes [swevg::W](swevg::W) writer structure"]
impl crate::Writable for SWEVG {}
#[doc = "Software event generation register"]
pub mod swevg;
#[doc = "Channel control register 0 (output mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctl0_output](chctl0_output) module"]
pub type CHCTL0_OUTPUT = crate::Reg<u16, _CHCTL0_OUTPUT>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CHCTL0_OUTPUT;
#[doc = "`read()` method returns [chctl0_output::R](chctl0_output::R) reader structure"]
impl crate::Readable for CHCTL0_OUTPUT {}
#[doc = "`write(|w| ..)` method takes [chctl0_output::W](chctl0_output::W) writer structure"]
impl crate::Writable for CHCTL0_OUTPUT {}
#[doc = "Channel control register 0 (output mode)"]
pub mod chctl0_output;
#[doc = "Channel control register 0 (input mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctl0_input](chctl0_input) module"]
pub type CHCTL0_INPUT = crate::Reg<u16, _CHCTL0_INPUT>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CHCTL0_INPUT;
#[doc = "`read()` method returns [chctl0_input::R](chctl0_input::R) reader structure"]
impl crate::Readable for CHCTL0_INPUT {}
#[doc = "`write(|w| ..)` method takes [chctl0_input::W](chctl0_input::W) writer structure"]
impl crate::Writable for CHCTL0_INPUT {}
#[doc = "Channel control register 0 (input mode)"]
pub mod chctl0_input;
#[doc = "Channel control register 1 (output mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctl1_output](chctl1_output) module"]
pub type CHCTL1_OUTPUT = crate::Reg<u16, _CHCTL1_OUTPUT>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CHCTL1_OUTPUT;
#[doc = "`read()` method returns [chctl1_output::R](chctl1_output::R) reader structure"]
impl crate::Readable for CHCTL1_OUTPUT {}
#[doc = "`write(|w| ..)` method takes [chctl1_output::W](chctl1_output::W) writer structure"]
impl crate::Writable for CHCTL1_OUTPUT {}
#[doc = "Channel control register 1 (output mode)"]
pub mod chctl1_output;
#[doc = "Channel control register 1 (input mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctl1_input](chctl1_input) module"]
pub type CHCTL1_INPUT = crate::Reg<u16, _CHCTL1_INPUT>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CHCTL1_INPUT;
#[doc = "`read()` method returns [chctl1_input::R](chctl1_input::R) reader structure"]
impl crate::Readable for CHCTL1_INPUT {}
#[doc = "`write(|w| ..)` method takes [chctl1_input::W](chctl1_input::W) writer structure"]
impl crate::Writable for CHCTL1_INPUT {}
#[doc = "Channel control register 1 (input mode)"]
pub mod chctl1_input;
#[doc = "Channel control register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctl2](chctl2) module"]
pub type CHCTL2 = crate::Reg<u16, _CHCTL2>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CHCTL2;
#[doc = "`read()` method returns [chctl2::R](chctl2::R) reader structure"]
impl crate::Readable for CHCTL2 {}
#[doc = "`write(|w| ..)` method takes [chctl2::W](chctl2::W) writer structure"]
impl crate::Writable for CHCTL2 {}
#[doc = "Channel control register 2"]
pub mod chctl2;
#[doc = "Counter register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt](cnt) module"]
pub type CNT = crate::Reg<u16, _CNT>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CNT;
#[doc = "`read()` method returns [cnt::R](cnt::R) reader structure"]
impl crate::Readable for CNT {}
#[doc = "`write(|w| ..)` method takes [cnt::W](cnt::W) writer structure"]
impl crate::Writable for CNT {}
#[doc = "Counter register"]
pub mod cnt;
#[doc = "Prescaler register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psc](psc) module"]
pub type PSC = crate::Reg<u16, _PSC>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _PSC;
#[doc = "`read()` method returns [psc::R](psc::R) reader structure"]
impl crate::Readable for PSC {}
#[doc = "`write(|w| ..)` method takes [psc::W](psc::W) writer structure"]
impl crate::Writable for PSC {}
#[doc = "Prescaler register"]
pub mod psc;
#[doc = "auto-reload register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [car](car) module"]
pub type CAR = crate::Reg<u16, _CAR>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CAR;
#[doc = "`read()` method returns [car::R](car::R) reader structure"]
impl crate::Readable for CAR {}
#[doc = "`write(|w| ..)` method takes [car::W](car::W) writer structure"]
impl crate::Writable for CAR {}
#[doc = "auto-reload register"]
pub mod car;
#[doc = "repetition counter register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crep](crep) module"]
pub type CREP = crate::Reg<u16, _CREP>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CREP;
#[doc = "`read()` method returns [crep::R](crep::R) reader structure"]
impl crate::Readable for CREP {}
#[doc = "`write(|w| ..)` method takes [crep::W](crep::W) writer structure"]
impl crate::Writable for CREP {}
#[doc = "repetition counter register"]
pub mod crep;
#[doc = "Channel 0 capture/compare value register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch0cv](ch0cv) module"]
pub type CH0CV = crate::Reg<u16, _CH0CV>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CH0CV;
#[doc = "`read()` method returns [ch0cv::R](ch0cv::R) reader structure"]
impl crate::Readable for CH0CV {}
#[doc = "`write(|w| ..)` method takes [ch0cv::W](ch0cv::W) writer structure"]
impl crate::Writable for CH0CV {}
#[doc = "Channel 0 capture/compare value register"]
pub mod ch0cv;
#[doc = "Channel 1 capture/compare value register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch1cv](ch1cv) module"]
pub type CH1CV = crate::Reg<u16, _CH1CV>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CH1CV;
#[doc = "`read()` method returns [ch1cv::R](ch1cv::R) reader structure"]
impl crate::Readable for CH1CV {}
#[doc = "`write(|w| ..)` method takes [ch1cv::W](ch1cv::W) writer structure"]
impl crate::Writable for CH1CV {}
#[doc = "Channel 1 capture/compare value register"]
pub mod ch1cv;
#[doc = "Channel 2 capture/compare value register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch2cv](ch2cv) module"]
pub type CH2CV = crate::Reg<u16, _CH2CV>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CH2CV;
#[doc = "`read()` method returns [ch2cv::R](ch2cv::R) reader structure"]
impl crate::Readable for CH2CV {}
#[doc = "`write(|w| ..)` method takes [ch2cv::W](ch2cv::W) writer structure"]
impl crate::Writable for CH2CV {}
#[doc = "Channel 2 capture/compare value register"]
pub mod ch2cv;
#[doc = "Channel 3 capture/compare value register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch3cv](ch3cv) module"]
pub type CH3CV = crate::Reg<u16, _CH3CV>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CH3CV;
#[doc = "`read()` method returns [ch3cv::R](ch3cv::R) reader structure"]
impl crate::Readable for CH3CV {}
#[doc = "`write(|w| ..)` method takes [ch3cv::W](ch3cv::W) writer structure"]
impl crate::Writable for CH3CV {}
#[doc = "Channel 3 capture/compare value register"]
pub mod ch3cv;
#[doc = "channel complementary protection register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cchp](cchp) module"]
pub type CCHP = crate::Reg<u16, _CCHP>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CCHP;
#[doc = "`read()` method returns [cchp::R](cchp::R) reader structure"]
impl crate::Readable for CCHP {}
#[doc = "`write(|w| ..)` method takes [cchp::W](cchp::W) writer structure"]
impl crate::Writable for CCHP {}
#[doc = "channel complementary protection register"]
pub mod cchp;
#[doc = "DMA configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacfg](dmacfg) module"]
pub type DMACFG = crate::Reg<u16, _DMACFG>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _DMACFG;
#[doc = "`read()` method returns [dmacfg::R](dmacfg::R) reader structure"]
impl crate::Readable for DMACFG {}
#[doc = "`write(|w| ..)` method takes [dmacfg::W](dmacfg::W) writer structure"]
impl crate::Writable for DMACFG {}
#[doc = "DMA configuration register"]
pub mod dmacfg;
#[doc = "DMA Transfer buffer register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatb](dmatb) module"]
pub type DMATB = crate::Reg<u16, _DMATB>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _DMATB;
#[doc = "`read()` method returns [dmatb::R](dmatb::R) reader structure"]
impl crate::Readable for DMATB {}
#[doc = "`write(|w| ..)` method takes [dmatb::W](dmatb::W) writer structure"]
impl crate::Writable for DMATB {}
#[doc = "DMA Transfer buffer register"]
pub mod dmatb;
#[doc = "Configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub type CFG = crate::Reg<u16, _CFG>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CFG;
#[doc = "`read()` method returns [cfg::R](cfg::R) reader structure"]
impl crate::Readable for CFG {}
#[doc = "`write(|w| ..)` method takes [cfg::W](cfg::W) writer structure"]
impl crate::Writable for CFG {}
#[doc = "Configuration register"]
pub mod cfg;