Module gd32f1::gd32f170::timer0::chctl1_output[][src]

Channel control register 1 (output mode)

Structs

CH2COMCEN_W

Write proxy for field CH2COMCEN

CH2COMCTL_W

Write proxy for field CH2COMCTL

CH2COMFEN_W

Write proxy for field CH2COMFEN

CH2COMSEN_W

Write proxy for field CH2COMSEN

CH2MS_W

Write proxy for field CH2MS

CH3COMCEN_W

Write proxy for field CH3COMCEN

CH3COMCTL_W

Write proxy for field CH3COMCTL

CH3COMFEN_W

Write proxy for field CH3COMFEN

CH3COMSEN_W

Write proxy for field CH3COMSEN

CH3MS_W

Write proxy for field CH3MS

Enums

CH3COMCEN_A

Channel 3 output compare clear enable

CH3COMCTL_A

Channel 3 compare output control

CH3COMFEN_A

Channel 3 output compare fast enable

CH3COMSEN_A

Channel 3 output compare shadow enable

CH3MS_A

Channel 3 mode selection

Type Definitions

CH2COMCEN_A

Channel 2 output compare clear enable

CH2COMCEN_R

Reader of field CH2COMCEN

CH2COMCTL_A

Channel 2 compare output control

CH2COMCTL_R

Reader of field CH2COMCTL

CH2COMFEN_A

Channel 2 output compare fast enable

CH2COMFEN_R

Reader of field CH2COMFEN

CH2COMSEN_A

Channel 2 output compare shadow enable

CH2COMSEN_R

Reader of field CH2COMSEN

CH2MS_A

Channel 2 mode selection

CH2MS_R

Reader of field CH2MS

CH3COMCEN_R

Reader of field CH3COMCEN

CH3COMCTL_R

Reader of field CH3COMCTL

CH3COMFEN_R

Reader of field CH3COMFEN

CH3COMSEN_R

Reader of field CH3COMSEN

CH3MS_R

Reader of field CH3MS

R

Reader of register CHCTL1_Output

W

Writer for register CHCTL1_Output