Module gd32f1::gd32f170::dma::ch3ctl0 [−][src]
DMA channel configuration register (DMA_CH3CTL0)
Structs
| CHEN_W | Write proxy for field |
| CMEN_W | Write proxy for field |
| DIR_W | Write proxy for field |
| FTFIE_W | Write proxy for field |
| HTFIE_W | Write proxy for field |
| M2M_W | Write proxy for field |
| MNAGA_W | Write proxy for field |
| MWIDTH_W | Write proxy for field |
| PNAGA_W | Write proxy for field |
| PRIO_W | Write proxy for field |
| PWIDTH_W | Write proxy for field |
| TAEIE_W | Write proxy for field |
Enums
| CHEN_A | Channel enable |
| CMEN_A | Circular mode enable |
| DIR_A | Transfer mode |
| FTFIE_A | Enable bit for full transfer finish interrupt |
| HTFIE_A | Enable bit for half transfer finish interrupt |
| M2M_A | Memory to memory mode |
| PNAGA_A | Next address generation algorithm of peripheral |
| PRIO_A | Priority Level of this channel |
| PWIDTH_A | Transfer data size of peripheral |
| TAEIE_A | Enable bit for tranfer access error interrupt |
Type Definitions
| CHEN_R | Reader of field |
| CMEN_R | Reader of field |
| DIR_R | Reader of field |
| FTFIE_R | Reader of field |
| HTFIE_R | Reader of field |
| M2M_R | Reader of field |
| MNAGA_A | Next address generation algorithm of memory |
| MNAGA_R | Reader of field |
| MWIDTH_A | Transfer data size of memory |
| MWIDTH_R | Reader of field |
| PNAGA_R | Reader of field |
| PRIO_R | Reader of field |
| PWIDTH_R | Reader of field |
| R | Reader of register CH3CTL0 |
| TAEIE_R | Reader of field |
| W | Writer for register CH3CTL0 |