Module gd32f1::gd32f130::adc [−][src]
Analog to digital converter
Modules
| ctl0 | control register 0 |
| ctl1 | control register 1 |
| idata0 | injected data register 0 |
| idata1 | injected data register 1 |
| idata2 | injected data register 2 |
| idata3 | injected data register 3 |
| ioff0 | Inserted channel data offset register 0 |
| ioff1 | Inserted channel data offset register 1 |
| ioff2 | Inserted channel data offset register 2 |
| ioff3 | Inserted channel data offset register 3 |
| isq | Inserted sequence register |
| ovsampctl | oversample control register |
| rdata | regular data register |
| rsq0 | regular sequence register 0 |
| rsq1 | regular sequence register 1 |
| rsq2 | regular sequence register 2 |
| sampt0 | Sampling time register 1 |
| sampt1 | Sampling time register 2 |
| stat | status register |
| wdht | watchdog higher threshold register |
| wdlt | watchdog lower threshold register |
Structs
| RegisterBlock | Register block |
Type Definitions
| CTL0 | control register 0 |
| CTL1 | control register 1 |
| IDATA0 | injected data register 0 |
| IDATA1 | injected data register 1 |
| IDATA2 | injected data register 2 |
| IDATA3 | injected data register 3 |
| IOFF0 | Inserted channel data offset register 0 |
| IOFF1 | Inserted channel data offset register 1 |
| IOFF2 | Inserted channel data offset register 2 |
| IOFF3 | Inserted channel data offset register 3 |
| ISQ | Inserted sequence register |
| OVSAMPCTL | oversample control register |
| RDATA | regular data register |
| RSQ0 | regular sequence register 0 |
| RSQ1 | regular sequence register 1 |
| RSQ2 | regular sequence register 2 |
| SAMPT0 | Sampling time register 1 |
| SAMPT1 | Sampling time register 2 |
| STAT | status register |
| WDHT | watchdog higher threshold register |
| WDLT | watchdog lower threshold register |