esp32p4/lp_i2s0/
rx_timing.rs

1#[doc = "Register `RX_TIMING` reader"]
2pub type R = crate::R<RX_TIMING_SPEC>;
3#[doc = "Register `RX_TIMING` writer"]
4pub type W = crate::W<RX_TIMING_SPEC>;
5#[doc = "Field `RX_SD_IN_DM` reader - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
6pub type RX_SD_IN_DM_R = crate::FieldReader;
7#[doc = "Field `RX_SD_IN_DM` writer - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
8pub type RX_SD_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `RX_WS_OUT_DM` reader - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
10pub type RX_WS_OUT_DM_R = crate::FieldReader;
11#[doc = "Field `RX_WS_OUT_DM` writer - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
12pub type RX_WS_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `RX_BCK_OUT_DM` reader - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
14pub type RX_BCK_OUT_DM_R = crate::FieldReader;
15#[doc = "Field `RX_BCK_OUT_DM` writer - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
16pub type RX_BCK_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `RX_WS_IN_DM` reader - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
18pub type RX_WS_IN_DM_R = crate::FieldReader;
19#[doc = "Field `RX_WS_IN_DM` writer - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
20pub type RX_WS_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `RX_BCK_IN_DM` reader - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
22pub type RX_BCK_IN_DM_R = crate::FieldReader;
23#[doc = "Field `RX_BCK_IN_DM` writer - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
24pub type RX_BCK_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25impl R {
26    #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
27    #[inline(always)]
28    pub fn rx_sd_in_dm(&self) -> RX_SD_IN_DM_R {
29        RX_SD_IN_DM_R::new((self.bits & 3) as u8)
30    }
31    #[doc = "Bits 16:17 - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
32    #[inline(always)]
33    pub fn rx_ws_out_dm(&self) -> RX_WS_OUT_DM_R {
34        RX_WS_OUT_DM_R::new(((self.bits >> 16) & 3) as u8)
35    }
36    #[doc = "Bits 20:21 - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
37    #[inline(always)]
38    pub fn rx_bck_out_dm(&self) -> RX_BCK_OUT_DM_R {
39        RX_BCK_OUT_DM_R::new(((self.bits >> 20) & 3) as u8)
40    }
41    #[doc = "Bits 24:25 - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
42    #[inline(always)]
43    pub fn rx_ws_in_dm(&self) -> RX_WS_IN_DM_R {
44        RX_WS_IN_DM_R::new(((self.bits >> 24) & 3) as u8)
45    }
46    #[doc = "Bits 28:29 - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
47    #[inline(always)]
48    pub fn rx_bck_in_dm(&self) -> RX_BCK_IN_DM_R {
49        RX_BCK_IN_DM_R::new(((self.bits >> 28) & 3) as u8)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("RX_TIMING")
56            .field(
57                "rx_sd_in_dm",
58                &format_args!("{}", self.rx_sd_in_dm().bits()),
59            )
60            .field(
61                "rx_ws_out_dm",
62                &format_args!("{}", self.rx_ws_out_dm().bits()),
63            )
64            .field(
65                "rx_bck_out_dm",
66                &format_args!("{}", self.rx_bck_out_dm().bits()),
67            )
68            .field(
69                "rx_ws_in_dm",
70                &format_args!("{}", self.rx_ws_in_dm().bits()),
71            )
72            .field(
73                "rx_bck_in_dm",
74                &format_args!("{}", self.rx_bck_in_dm().bits()),
75            )
76            .finish()
77    }
78}
79#[cfg(feature = "impl-register-debug")]
80impl core::fmt::Debug for crate::generic::Reg<RX_TIMING_SPEC> {
81    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
82        core::fmt::Debug::fmt(&self.read(), f)
83    }
84}
85impl W {
86    #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
87    #[inline(always)]
88    #[must_use]
89    pub fn rx_sd_in_dm(&mut self) -> RX_SD_IN_DM_W<RX_TIMING_SPEC> {
90        RX_SD_IN_DM_W::new(self, 0)
91    }
92    #[doc = "Bits 16:17 - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
93    #[inline(always)]
94    #[must_use]
95    pub fn rx_ws_out_dm(&mut self) -> RX_WS_OUT_DM_W<RX_TIMING_SPEC> {
96        RX_WS_OUT_DM_W::new(self, 16)
97    }
98    #[doc = "Bits 20:21 - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
99    #[inline(always)]
100    #[must_use]
101    pub fn rx_bck_out_dm(&mut self) -> RX_BCK_OUT_DM_W<RX_TIMING_SPEC> {
102        RX_BCK_OUT_DM_W::new(self, 20)
103    }
104    #[doc = "Bits 24:25 - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
105    #[inline(always)]
106    #[must_use]
107    pub fn rx_ws_in_dm(&mut self) -> RX_WS_IN_DM_W<RX_TIMING_SPEC> {
108        RX_WS_IN_DM_W::new(self, 24)
109    }
110    #[doc = "Bits 28:29 - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
111    #[inline(always)]
112    #[must_use]
113    pub fn rx_bck_in_dm(&mut self) -> RX_BCK_IN_DM_W<RX_TIMING_SPEC> {
114        RX_BCK_IN_DM_W::new(self, 28)
115    }
116}
117#[doc = "I2S RX timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_timing::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_timing::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
118pub struct RX_TIMING_SPEC;
119impl crate::RegisterSpec for RX_TIMING_SPEC {
120    type Ux = u32;
121}
122#[doc = "`read()` method returns [`rx_timing::R`](R) reader structure"]
123impl crate::Readable for RX_TIMING_SPEC {}
124#[doc = "`write(|w| ..)` method takes [`rx_timing::W`](W) writer structure"]
125impl crate::Writable for RX_TIMING_SPEC {
126    type Safety = crate::Unsafe;
127    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
128    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
129}
130#[doc = "`reset()` method sets RX_TIMING to value 0"]
131impl crate::Resettable for RX_TIMING_SPEC {
132    const RESET_VALUE: u32 = 0;
133}
esp32p4/lp_i2s0/rx_timing.rs

esp32p4/lp_i2s0/
rx_timing.rs
