Type Alias esp32c3::spi2::dma_conf::W

pub type W = W<DMA_CONF_SPEC>;

Register DMA_CONF writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn dma_slv_seg_trans_en( &mut self ) -> DMA_SLV_SEG_TRANS_EN_W<'_, DMA_CONF_SPEC>

Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.

pub fn slv_rx_seg_trans_clr_en( &mut self ) -> SLV_RX_SEG_TRANS_CLR_EN_W<'_, DMA_CONF_SPEC>

Bit 19 - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.

pub fn slv_tx_seg_trans_clr_en( &mut self ) -> SLV_TX_SEG_TRANS_CLR_EN_W<'_, DMA_CONF_SPEC>

Bit 20 - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.

pub fn rx_eof_en(&mut self) -> RX_EOF_EN_W<'_, DMA_CONF_SPEC>

Bit 21 - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.

pub fn dma_rx_ena(&mut self) -> DMA_RX_ENA_W<'_, DMA_CONF_SPEC>

Bit 27 - Set this bit to enable SPI DMA controlled receive data mode.

pub fn dma_tx_ena(&mut self) -> DMA_TX_ENA_W<'_, DMA_CONF_SPEC>

Bit 28 - Set this bit to enable SPI DMA controlled send data mode.

pub fn rx_afifo_rst(&mut self) -> RX_AFIFO_RST_W<'_, DMA_CONF_SPEC>

Bit 29 - Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.

pub fn buf_afifo_rst(&mut self) -> BUF_AFIFO_RST_W<'_, DMA_CONF_SPEC>

Bit 30 - Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.

pub fn dma_afifo_rst(&mut self) -> DMA_AFIFO_RST_W<'_, DMA_CONF_SPEC>

Bit 31 - Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.