Type Alias esp32c3::spi1::sus_status::R

pub type R = R<SUS_STATUS_SPEC>;

Register SUS_STATUS reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn flash_sus(&self) -> FLASH_SUS_R

Bit 0 - The status of flash suspend, only used in SPI1.

pub fn wait_pesr_cmd_2b(&self) -> WAIT_PESR_CMD_2B_R

Bit 1 - 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.

pub fn flash_hpm_dly_128(&self) -> FLASH_HPM_DLY_128_R

Bit 2 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.

pub fn flash_res_dly_128(&self) -> FLASH_RES_DLY_128_R

Bit 3 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.

pub fn flash_dp_dly_128(&self) -> FLASH_DP_DLY_128_R

Bit 4 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.

pub fn flash_per_dly_128(&self) -> FLASH_PER_DLY_128_R

Bit 5 - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.

pub fn flash_pes_dly_128(&self) -> FLASH_PES_DLY_128_R

Bit 6 - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.

pub fn spi0_lock_en(&self) -> SPI0_LOCK_EN_R

Bit 7 - 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.