Type Alias esp32c3::sensitive::CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5
source · pub type CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 = Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>;
Expand description
CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 (rw) register accessor: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG
You can read
this register and get core_x_iram0_dram0_dma_split_line_constrain_5::R
. You can reset
, write
, write_with_zero
this register using core_x_iram0_dram0_dma_split_line_constrain_5::W
. You can also modify
this register. See API.
For information about available fields see core_x_iram0_dram0_dma_split_line_constrain_5
module
Aliased Type§
struct CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 { /* private fields */ }