Type Alias esp32c3::sensitive::core_x_iram0_dram0_dma_split_line_constrain_2::R

pub type R = R<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_SPEC>;

Register CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn core_x_iram0_sram_line_0_category_0( &self ) -> CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_R

Bits 0:1 - core_x_iram0_sram_line_0_category_0

pub fn core_x_iram0_sram_line_0_category_1( &self ) -> CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_R

Bits 2:3 - core_x_iram0_sram_line_0_category_1

pub fn core_x_iram0_sram_line_0_category_2( &self ) -> CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_R

Bits 4:5 - core_x_iram0_sram_line_0_category_2

pub fn core_x_iram0_sram_line_0_splitaddr( &self ) -> CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_R

Bits 14:21 - core_x_iram0_sram_line_0_splitaddr