Type Alias esp32c3::rtc_cntl::clk_conf::W

pub type W = W<CLK_CONF_SPEC>;

Register CLK_CONF writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn efuse_clk_force_gating( &mut self ) -> EFUSE_CLK_FORCE_GATING_W<'_, CLK_CONF_SPEC>

Bit 1 - efuse_clk_force_gating

pub fn efuse_clk_force_nogating( &mut self ) -> EFUSE_CLK_FORCE_NOGATING_W<'_, CLK_CONF_SPEC>

Bit 2 - efuse_clk_force_nogating

pub fn ck8m_div_sel_vld(&mut self) -> CK8M_DIV_SEL_VLD_W<'_, CLK_CONF_SPEC>

Bit 3 - used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel

pub fn ck8m_div(&mut self) -> CK8M_DIV_W<'_, CLK_CONF_SPEC>

Bits 4:5 - CK8M_D256_OUT divider. 00: div128

pub fn enb_ck8m(&mut self) -> ENB_CK8M_W<'_, CLK_CONF_SPEC>

Bit 6 - disable CK8M and CK8M_D256_OUT

pub fn enb_ck8m_div(&mut self) -> ENB_CK8M_DIV_W<'_, CLK_CONF_SPEC>

Bit 7 - 1: CK8M_D256_OUT is actually CK8M

pub fn dig_xtal32k_en(&mut self) -> DIG_XTAL32K_EN_W<'_, CLK_CONF_SPEC>

Bit 8 - enable CK_XTAL_32K for digital core (no relationship with RTC core)

pub fn dig_clk8m_d256_en(&mut self) -> DIG_CLK8M_D256_EN_W<'_, CLK_CONF_SPEC>

Bit 9 - enable CK8M_D256_OUT for digital core (no relationship with RTC core)

pub fn dig_clk8m_en(&mut self) -> DIG_CLK8M_EN_W<'_, CLK_CONF_SPEC>

Bit 10 - enable CK8M for digital core (no relationship with RTC core)

pub fn ck8m_div_sel(&mut self) -> CK8M_DIV_SEL_W<'_, CLK_CONF_SPEC>

Bits 12:14 - divider = reg_ck8m_div_sel + 1

pub fn xtal_force_nogating( &mut self ) -> XTAL_FORCE_NOGATING_W<'_, CLK_CONF_SPEC>

Bit 15 - XTAL force no gating during sleep

pub fn ck8m_force_nogating( &mut self ) -> CK8M_FORCE_NOGATING_W<'_, CLK_CONF_SPEC>

Bit 16 - CK8M force no gating during sleep

pub fn ck8m_dfreq(&mut self) -> CK8M_DFREQ_W<'_, CLK_CONF_SPEC>

Bits 17:24 - CK8M_DFREQ

pub fn ck8m_force_pd(&mut self) -> CK8M_FORCE_PD_W<'_, CLK_CONF_SPEC>

Bit 25 - CK8M force power down

pub fn ck8m_force_pu(&mut self) -> CK8M_FORCE_PU_W<'_, CLK_CONF_SPEC>

Bit 26 - CK8M force power up

pub fn xtal_global_force_gating( &mut self ) -> XTAL_GLOBAL_FORCE_GATING_W<'_, CLK_CONF_SPEC>

Bit 27 - force enable xtal clk gating

pub fn xtal_global_force_nogating( &mut self ) -> XTAL_GLOBAL_FORCE_NOGATING_W<'_, CLK_CONF_SPEC>

Bit 28 - force bypass xtal clk gating

pub fn fast_clk_rtc_sel(&mut self) -> FAST_CLK_RTC_SEL_W<'_, CLK_CONF_SPEC>

Bit 29 - fast_clk_rtc sel. 0: XTAL div 4

pub fn ana_clk_rtc_sel(&mut self) -> ANA_CLK_RTC_SEL_W<'_, CLK_CONF_SPEC>

Bits 30:31 - slelect rtc slow clk