Type Alias esp32c3::rmt::int_clr::W

pub type W = W<INT_CLR_SPEC>;

Register INT_CLR writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn ch_tx_end(&mut self, n: u8) -> CH_TX_END_W<'_, INT_CLR_SPEC>

reg_ch(0-1)_tx_end_int_clr.

NOTE: n is number of field in register. n == 0 corresponds to CH0_TX_END field

pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<'_, INT_CLR_SPEC>

Bit 0 - reg_ch0_tx_end_int_clr.

pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<'_, INT_CLR_SPEC>

Bit 1 - reg_ch1_tx_end_int_clr.

pub fn ch_rx_end(&mut self, n: u8) -> CH_RX_END_W<'_, INT_CLR_SPEC>

reg_ch2_rx_end_int_clr.

NOTE: n is number of field in register. n == 0 corresponds to CH2_RX_END field

pub fn ch2_rx_end(&mut self) -> CH_RX_END_W<'_, INT_CLR_SPEC>

Bit 2 - reg_ch2_rx_end_int_clr.

pub fn ch3_rx_end(&mut self) -> CH_RX_END_W<'_, INT_CLR_SPEC>

Bit 3 - reg_ch2_rx_end_int_clr.

pub fn ch_tx_err(&mut self, n: u8) -> CH_TX_ERR_W<'_, INT_CLR_SPEC>

reg_ch(0-1)_err_int_clr.

NOTE: n is number of field in register. n == 0 corresponds to CH0_TX_ERR field

pub fn ch0_tx_err(&mut self) -> CH_TX_ERR_W<'_, INT_CLR_SPEC>

Bit 4 - reg_ch0_err_int_clr.

pub fn ch1_tx_err(&mut self) -> CH_TX_ERR_W<'_, INT_CLR_SPEC>

Bit 5 - reg_ch1_err_int_clr.

pub fn ch_rx_err(&mut self, n: u8) -> CH_RX_ERR_W<'_, INT_CLR_SPEC>

reg_ch2_err_int_clr.

NOTE: n is number of field in register. n == 0 corresponds to CH2_RX_ERR field

pub fn ch2_rx_err(&mut self) -> CH_RX_ERR_W<'_, INT_CLR_SPEC>

Bit 6 - reg_ch2_err_int_clr.

pub fn ch3_rx_err(&mut self) -> CH_RX_ERR_W<'_, INT_CLR_SPEC>

Bit 7 - reg_ch2_err_int_clr.

pub fn ch_tx_thr_event(&mut self, n: u8) -> CH_TX_THR_EVENT_W<'_, INT_CLR_SPEC>

reg_ch(0-1)_tx_thr_event_int_clr.

NOTE: n is number of field in register. n == 0 corresponds to CH0_TX_THR_EVENT field

pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<'_, INT_CLR_SPEC>

Bit 8 - reg_ch0_tx_thr_event_int_clr.

pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<'_, INT_CLR_SPEC>

Bit 9 - reg_ch1_tx_thr_event_int_clr.

pub fn ch_rx_thr_event(&mut self, n: u8) -> CH_RX_THR_EVENT_W<'_, INT_CLR_SPEC>

reg_ch2_rx_thr_event_int_clr.

NOTE: n is number of field in register. n == 0 corresponds to CH2_RX_THR_EVENT field

pub fn ch2_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<'_, INT_CLR_SPEC>

Bit 10 - reg_ch2_rx_thr_event_int_clr.

pub fn ch3_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<'_, INT_CLR_SPEC>

Bit 11 - reg_ch2_rx_thr_event_int_clr.

pub fn ch_tx_loop(&mut self, n: u8) -> CH_TX_LOOP_W<'_, INT_CLR_SPEC>

reg_ch(0-1)_tx_loop_int_clr.

NOTE: n is number of field in register. n == 0 corresponds to CH0_TX_LOOP field

pub fn ch0_tx_loop(&mut self) -> CH_TX_LOOP_W<'_, INT_CLR_SPEC>

Bit 12 - reg_ch0_tx_loop_int_clr.

pub fn ch1_tx_loop(&mut self) -> CH_TX_LOOP_W<'_, INT_CLR_SPEC>

Bit 13 - reg_ch1_tx_loop_int_clr.