pub type R = R<CLK_CONF_SPEC>;
Expand description
Register CLK_CONF
reader
Aliased Type§
struct R { /* private fields */ }
Implementations§
source§impl R
impl R
sourcepub fn sclk_div_b(&self) -> SCLK_DIV_B_R
pub fn sclk_div_b(&self) -> SCLK_DIV_B_R
Bits 0:5 - The denominator of the frequency divider factor.
sourcepub fn sclk_div_a(&self) -> SCLK_DIV_A_R
pub fn sclk_div_a(&self) -> SCLK_DIV_A_R
Bits 6:11 - The numerator of the frequency divider factor.
sourcepub fn sclk_div_num(&self) -> SCLK_DIV_NUM_R
pub fn sclk_div_num(&self) -> SCLK_DIV_NUM_R
Bits 12:19 - The integral part of the frequency divider factor.
sourcepub fn sclk_sel(&self) -> SCLK_SEL_R
pub fn sclk_sel(&self) -> SCLK_SEL_R
Bits 20:21 - UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
sourcepub fn rst_core(&self) -> RST_CORE_R
pub fn rst_core(&self) -> RST_CORE_R
Bit 23 - Write 1 then write 0 to this bit, reset UART Tx/Rx.
sourcepub fn tx_sclk_en(&self) -> TX_SCLK_EN_R
pub fn tx_sclk_en(&self) -> TX_SCLK_EN_R
Bit 24 - Set this bit to enable UART Tx clock.
sourcepub fn rx_sclk_en(&self) -> RX_SCLK_EN_R
pub fn rx_sclk_en(&self) -> RX_SCLK_EN_R
Bit 25 - Set this bit to enable UART Rx clock.
sourcepub fn tx_rst_core(&self) -> TX_RST_CORE_R
pub fn tx_rst_core(&self) -> TX_RST_CORE_R
Bit 26 - Write 1 then write 0 to this bit, reset UART Tx.
sourcepub fn rx_rst_core(&self) -> RX_RST_CORE_R
pub fn rx_rst_core(&self) -> RX_RST_CORE_R
Bit 27 - Write 1 then write 0 to this bit, reset UART Rx.