Type Alias esp32c3::spi0::ctrl2::W

pub type W = W<CTRL2_SPEC>;

Register CTRL2 writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn cs_setup_time(&mut self) -> CS_SETUP_TIME_W<'_, CTRL2_SPEC>

Bits 0:4 - (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.

pub fn cs_hold_time(&mut self) -> CS_HOLD_TIME_W<'_, CTRL2_SPEC>

Bits 5:9 - Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.

pub fn cs_hold_delay(&mut self) -> CS_HOLD_DELAY_W<'_, CTRL2_SPEC>

Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.

pub fn sync_reset(&mut self) -> SYNC_RESET_W<'_, CTRL2_SPEC>

Bit 31 - The FSM will be reset.