Type Alias esp32c3::spi0::core_clk_sel::R

pub type R = R<CORE_CLK_SEL_SPEC>;

Register CORE_CLK_SEL reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn spi01_clk_sel(&self) -> SPI01_CLK_SEL_R

Bits 0:1 - When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.