Struct esp32c3::spi_mem::RegisterBlock[−][src]

#[repr(C)]pub struct RegisterBlock {
    pub spi_mem_cmd: SPI_MEM_CMD,
    pub spi_mem_addr: SPI_MEM_ADDR,
    pub spi_mem_ctrl: SPI_MEM_CTRL,
    pub spi_mem_ctrl1: SPI_MEM_CTRL1,
    pub spi_mem_ctrl2: SPI_MEM_CTRL2,
    pub spi_mem_clock: SPI_MEM_CLOCK,
    pub spi_mem_user: SPI_MEM_USER,
    pub spi_mem_user1: SPI_MEM_USER1,
    pub spi_mem_user2: SPI_MEM_USER2,
    pub spi_mem_mosi_dlen: SPI_MEM_MOSI_DLEN,
    pub spi_mem_miso_dlen: SPI_MEM_MISO_DLEN,
    pub spi_mem_rd_status: SPI_MEM_RD_STATUS,
    pub spi_mem_misc: SPI_MEM_MISC,
    pub spi_mem_tx_crc: SPI_MEM_TX_CRC,
    pub spi_mem_cache_fctrl: SPI_MEM_CACHE_FCTRL,
    pub spi_mem_fsm: SPI_MEM_FSM,
    pub spi_mem_w0: SPI_MEM_W0,
    pub spi_mem_w1: SPI_MEM_W1,
    pub spi_mem_w2: SPI_MEM_W2,
    pub spi_mem_w3: SPI_MEM_W3,
    pub spi_mem_w4: SPI_MEM_W4,
    pub spi_mem_w5: SPI_MEM_W5,
    pub spi_mem_w6: SPI_MEM_W6,
    pub spi_mem_w7: SPI_MEM_W7,
    pub spi_mem_w8: SPI_MEM_W8,
    pub spi_mem_w9: SPI_MEM_W9,
    pub spi_mem_w10: SPI_MEM_W10,
    pub spi_mem_w11: SPI_MEM_W11,
    pub spi_mem_w12: SPI_MEM_W12,
    pub spi_mem_w13: SPI_MEM_W13,
    pub spi_mem_w14: SPI_MEM_W14,
    pub spi_mem_w15: SPI_MEM_W15,
    pub spi_mem_flash_waiti_ctrl: SPI_MEM_FLASH_WAITI_CTRL,
    pub spi_mem_flash_sus_ctrl: SPI_MEM_FLASH_SUS_CTRL,
    pub spi_mem_flash_sus_cmd: SPI_MEM_FLASH_SUS_CMD,
    pub spi_mem_sus_status: SPI_MEM_SUS_STATUS,
    pub spi_mem_timing_cali: SPI_MEM_TIMING_CALI,
    pub spi_mem_din_mode: SPI_MEM_DIN_MODE,
    pub spi_mem_din_num: SPI_MEM_DIN_NUM,
    pub spi_mem_dout_mode: SPI_MEM_DOUT_MODE,
    pub spi_mem_int_ena: SPI_MEM_INT_ENA,
    pub spi_mem_int_clr: SPI_MEM_INT_CLR,
    pub spi_mem_int_raw: SPI_MEM_INT_RAW,
    pub spi_mem_int_st: SPI_MEM_INT_ST,
    pub spi_mem_clock_gate: SPI_MEM_CLOCK_GATE,
    pub spi_mem_core_clk_sel: SPI_MEM_CORE_CLK_SEL,
    pub spi_mem_date: SPI_MEM_DATE,
    // some fields omitted
}

Register block

Fields

spi_mem_cmd: SPI_MEM_CMD

0x00 - SPI_MEM_CMD

spi_mem_addr: SPI_MEM_ADDR

0x04 - SPI_MEM_ADDR

spi_mem_ctrl: SPI_MEM_CTRL

0x08 - SPI_MEM_CTRL

spi_mem_ctrl1: SPI_MEM_CTRL1

0x0c - SPI_MEM_CTRL1

spi_mem_ctrl2: SPI_MEM_CTRL2

0x10 - SPI_MEM_CTRL2

spi_mem_clock: SPI_MEM_CLOCK

0x14 - SPI_MEM_CLOCK

spi_mem_user: SPI_MEM_USER

0x18 - SPI_MEM_USER

spi_mem_user1: SPI_MEM_USER1

0x1c - SPI_MEM_USER1

spi_mem_user2: SPI_MEM_USER2

0x20 - SPI_MEM_USER2

spi_mem_mosi_dlen: SPI_MEM_MOSI_DLEN

0x24 - SPI_MEM_MOSI_DLEN

spi_mem_miso_dlen: SPI_MEM_MISO_DLEN

0x28 - SPI_MEM_MISO_DLEN

spi_mem_rd_status: SPI_MEM_RD_STATUS

0x2c - SPI_MEM_RD_STATUS

spi_mem_misc: SPI_MEM_MISC

0x34 - SPI_MEM_MISC

spi_mem_tx_crc: SPI_MEM_TX_CRC

0x38 - SPI_MEM_TX_CRC

spi_mem_cache_fctrl: SPI_MEM_CACHE_FCTRL

0x3c - SPI_MEM_CACHE_FCTRL

spi_mem_fsm: SPI_MEM_FSM

0x54 - SPI_MEM_FSM

spi_mem_w0: SPI_MEM_W0

0x58 - SPI_MEM_W0

spi_mem_w1: SPI_MEM_W1

0x5c - SPI_MEM_W1

spi_mem_w2: SPI_MEM_W2

0x60 - SPI_MEM_W2

spi_mem_w3: SPI_MEM_W3

0x64 - SPI_MEM_W3

spi_mem_w4: SPI_MEM_W4

0x68 - SPI_MEM_W4

spi_mem_w5: SPI_MEM_W5

0x6c - SPI_MEM_W5

spi_mem_w6: SPI_MEM_W6

0x70 - SPI_MEM_W6

spi_mem_w7: SPI_MEM_W7

0x74 - SPI_MEM_W7

spi_mem_w8: SPI_MEM_W8

0x78 - SPI_MEM_W8

spi_mem_w9: SPI_MEM_W9

0x7c - SPI_MEM_W9

spi_mem_w10: SPI_MEM_W10

0x80 - SPI_MEM_W10

spi_mem_w11: SPI_MEM_W11

0x84 - SPI_MEM_W11

spi_mem_w12: SPI_MEM_W12

0x88 - SPI_MEM_W12

spi_mem_w13: SPI_MEM_W13

0x8c - SPI_MEM_W13

spi_mem_w14: SPI_MEM_W14

0x90 - SPI_MEM_W14

spi_mem_w15: SPI_MEM_W15

0x94 - SPI_MEM_W15

spi_mem_flash_waiti_ctrl: SPI_MEM_FLASH_WAITI_CTRL

0x98 - SPI_MEM_FLASH_WAITI_CTRL

spi_mem_flash_sus_ctrl: SPI_MEM_FLASH_SUS_CTRL

0x9c - SPI_MEM_FLASH_SUS_CTRL

spi_mem_flash_sus_cmd: SPI_MEM_FLASH_SUS_CMD

0xa0 - SPI_MEM_FLASH_SUS_CMD

spi_mem_sus_status: SPI_MEM_SUS_STATUS

0xa4 - SPI_MEM_SUS_STATUS

spi_mem_timing_cali: SPI_MEM_TIMING_CALI

0xa8 - SPI_MEM_TIMING_CALI

spi_mem_din_mode: SPI_MEM_DIN_MODE

0xac - SPI_MEM_DIN_MODE

spi_mem_din_num: SPI_MEM_DIN_NUM

0xb0 - SPI_MEM_DIN_NUM

spi_mem_dout_mode: SPI_MEM_DOUT_MODE

0xb4 - SPI_MEM_DOUT_MODE

spi_mem_int_ena: SPI_MEM_INT_ENA

0xc0 - SPI_MEM_INT_ENA

spi_mem_int_clr: SPI_MEM_INT_CLR

0xc4 - SPI_MEM_INT_CLR

spi_mem_int_raw: SPI_MEM_INT_RAW

0xc8 - SPI_MEM_INT_RAW

spi_mem_int_st: SPI_MEM_INT_ST

0xcc - SPI_MEM_INT_ST

spi_mem_clock_gate: SPI_MEM_CLOCK_GATE

0xdc - SPI_MEM_CLOCK_GATE

spi_mem_core_clk_sel: SPI_MEM_CORE_CLK_SEL

0xe0 - SPI_MEM_CORE_CLK_SEL

spi_mem_date: SPI_MEM_DATE

0x3fc - SPI_MEM_DATE

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