Module esp32c3_hal::interrupt

Interrupt handling - RISCV

When the vectored feature is enabled, CPU interrupts 1 through 15 are reserved for each of the possible interrupt priorities.

interrupt1() => Priority::Priority1
interrupt2() => Priority::Priority2
...
interrupt15() => Priority::Priority15

Enums

CpuInterrupt

Enumeration of available CPU interrupts. It is possible to create a handler for each of the interrupts. (e.g. interrupt3)

Error

Interrupt Error

InterruptKind

Interrupt kind

Priority

Interrupt priority levels.

Functions

clear

Clear a CPU interrupt

disable

Disable the given peripheral interrupt.

enable

Enables a interrupt at a given priority

enable_cpu_interrupt^⚠

Enable a CPU interrupt

get_status

Get status of peripheral interrupts

map^⚠

Assign a peripheral interrupt to an CPU interrupt.

set_kind

Set the interrupt kind (i.e. level or edge) of an CPU interrupt

set_priority^⚠

Set the priority level of an CPU interrupt