Type Alias esp32::apb_ctrl::apb_saradc_ctrl::W

pub type W = W<APB_SARADC_CTRL_SPEC>;

Register APB_SARADC_CTRL writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn saradc_start_force( &mut self ) -> SARADC_START_FORCE_W<'_, APB_SARADC_CTRL_SPEC>

Bit 0

pub fn saradc_start(&mut self) -> SARADC_START_W<'_, APB_SARADC_CTRL_SPEC>

Bit 1

pub fn saradc_sar2_mux(&mut self) -> SARADC_SAR2_MUX_W<'_, APB_SARADC_CTRL_SPEC>

Bit 2 - 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL

pub fn saradc_work_mode( &mut self ) -> SARADC_WORK_MODE_W<'_, APB_SARADC_CTRL_SPEC>

Bits 3:4 - 0: single mode 1: double mode 2: alternate mode

pub fn saradc_sar_sel(&mut self) -> SARADC_SAR_SEL_W<'_, APB_SARADC_CTRL_SPEC>

Bit 5 - 0: SAR1 1: SAR2 only work for single SAR mode

pub fn saradc_sar_clk_gated( &mut self ) -> SARADC_SAR_CLK_GATED_W<'_, APB_SARADC_CTRL_SPEC>

Bit 6

pub fn saradc_sar_clk_div( &mut self ) -> SARADC_SAR_CLK_DIV_W<'_, APB_SARADC_CTRL_SPEC>

Bits 7:14 - SAR clock divider

pub fn saradc_sar1_patt_len( &mut self ) -> SARADC_SAR1_PATT_LEN_W<'_, APB_SARADC_CTRL_SPEC>

Bits 15:18 - 0 ~ 15 means length 1 ~ 16

pub fn saradc_sar2_patt_len( &mut self ) -> SARADC_SAR2_PATT_LEN_W<'_, APB_SARADC_CTRL_SPEC>

Bits 19:22 - 0 ~ 15 means length 1 ~ 16

pub fn saradc_sar1_patt_p_clear( &mut self ) -> SARADC_SAR1_PATT_P_CLEAR_W<'_, APB_SARADC_CTRL_SPEC>

Bit 23 - clear the pointer of pattern table for DIG ADC1 CTRL

pub fn saradc_sar2_patt_p_clear( &mut self ) -> SARADC_SAR2_PATT_P_CLEAR_W<'_, APB_SARADC_CTRL_SPEC>

Bit 24 - clear the pointer of pattern table for DIG ADC2 CTRL

pub fn saradc_data_sar_sel( &mut self ) -> SARADC_DATA_SAR_SEL_W<'_, APB_SARADC_CTRL_SPEC>

Bit 25 - 1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.

pub fn saradc_data_to_i2s( &mut self ) -> SARADC_DATA_TO_I2S_W<'_, APB_SARADC_CTRL_SPEC>

Bit 26 - 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix