Struct esp32::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer.

Used as an argument to the closures in the write and modify methods of the register.

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register.

impl W<u32, Reg<u32, _START>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Write 1 to start AES operation

impl W<u32, Reg<u32, _MODE>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:2 - Selects AES accelerator mode

impl W<u32, Reg<u32, _ENDIAN>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:5 - Select AES endian mode

impl W<u32, Reg<u32, _CFG_DATA0>>

pub fn device_id_fn1(&mut self) -> DEVICE_ID_FN1_W<'_>

Bits 16:31

pub fn user_id_fn1(&mut self) -> USER_ID_FN1_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CFG_DATA1>>

pub fn sdio20_conf1(&mut self) -> SDIO20_CONF1_W<'_>

Bits 29:31

pub fn func2_eps(&mut self) -> FUNC2_EPS_W<'_>

Bit 28

pub fn sdio_ver(&mut self) -> SDIO_VER_W<'_>

Bits 16:27

pub fn sdio20_conf0(&mut self) -> SDIO20_CONF0_W<'_>

Bits 12:15

pub fn ioenable1(&mut self) -> IOENABLE1_W<'_>

Bit 11

pub fn emp(&mut self) -> EMP_W<'_>

Bit 10

pub fn func1_eps(&mut self) -> FUNC1_EPS_W<'_>

Bit 9

pub fn cd_disable(&mut self) -> CD_DISABLE_W<'_>

Bit 8

pub fn ioenable2(&mut self) -> IOENABLE2_W<'_>

Bit 7

pub fn sdio_int_mask(&mut self) -> SDIO_INT_MASK_W<'_>

Bit 6

pub fn sdio_ioready2(&mut self) -> SDIO_IOREADY2_W<'_>

Bit 5

pub fn sdio_cd_enable(&mut self) -> SDIO_CD_ENABLE_W<'_>

Bit 4

pub fn highspeed_mode(&mut self) -> HIGHSPEED_MODE_W<'_>

Bit 3

pub fn highspeed_enable(&mut self) -> HIGHSPEED_ENABLE_W<'_>

Bit 2

pub fn sdio_ioready1(&mut self) -> SDIO_IOREADY1_W<'_>

Bit 1

pub fn sdio_enable(&mut self) -> SDIO_ENABLE_W<'_>

Bit 0

impl W<u32, Reg<u32, _CFG_DATA7>>

pub fn sdio_ioready0(&mut self) -> SDIO_IOREADY0_W<'_>

Bit 17

pub fn sdio_rst(&mut self) -> SDIO_RST_W<'_>

Bit 16

pub fn chip_state(&mut self) -> CHIP_STATE_W<'_>

Bits 8:15

pub fn pin_state(&mut self) -> PIN_STATE_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CIS_CONF0>>

pub fn cis_conf_w0(&mut self) -> CIS_CONF_W0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CIS_CONF1>>

pub fn cis_conf_w1(&mut self) -> CIS_CONF_W1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CIS_CONF2>>

pub fn cis_conf_w2(&mut self) -> CIS_CONF_W2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CIS_CONF3>>

pub fn cis_conf_w3(&mut self) -> CIS_CONF_W3_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CIS_CONF4>>

pub fn cis_conf_w4(&mut self) -> CIS_CONF_W4_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CIS_CONF5>>

pub fn cis_conf_w5(&mut self) -> CIS_CONF_W5_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CIS_CONF6>>

pub fn cis_conf_w6(&mut self) -> CIS_CONF_W6_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CIS_CONF7>>

pub fn cis_conf_w7(&mut self) -> CIS_CONF_W7_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CFG_DATA16>>

pub fn device_id_fn2(&mut self) -> DEVICE_ID_FN2_W<'_>

Bits 16:31

pub fn user_id_fn2(&mut self) -> USER_ID_FN2_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _DATE>>

pub fn sdio_date(&mut self) -> SDIO_DATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CMD>>

pub fn flash_read(&mut self) -> FLASH_READ_W<'_>

Bit 31

pub fn flash_wren(&mut self) -> FLASH_WREN_W<'_>

Bit 30

pub fn flash_wrdi(&mut self) -> FLASH_WRDI_W<'_>

Bit 29

pub fn flash_rdid(&mut self) -> FLASH_RDID_W<'_>

Bit 28

pub fn flash_rdsr(&mut self) -> FLASH_RDSR_W<'_>

Bit 27

pub fn flash_wrsr(&mut self) -> FLASH_WRSR_W<'_>

Bit 26

pub fn flash_pp(&mut self) -> FLASH_PP_W<'_>

Bit 25

pub fn flash_se(&mut self) -> FLASH_SE_W<'_>

Bit 24

pub fn flash_be(&mut self) -> FLASH_BE_W<'_>

Bit 23

pub fn flash_ce(&mut self) -> FLASH_CE_W<'_>

Bit 22

pub fn flash_dp(&mut self) -> FLASH_DP_W<'_>

Bit 21

pub fn flash_res(&mut self) -> FLASH_RES_W<'_>

Bit 20

pub fn flash_hpm(&mut self) -> FLASH_HPM_W<'_>

Bit 19

pub fn usr(&mut self) -> USR_W<'_>

Bit 18

pub fn flash_pes(&mut self) -> FLASH_PES_W<'_>

Bit 17

pub fn flash_per(&mut self) -> FLASH_PER_W<'_>

Bit 16

impl W<u32, Reg<u32, _CTRL>>

pub fn wr_bit_order(&mut self) -> WR_BIT_ORDER_W<'_>

Bit 26

pub fn rd_bit_order(&mut self) -> RD_BIT_ORDER_W<'_>

Bit 25

pub fn fread_qio(&mut self) -> FREAD_QIO_W<'_>

Bit 24

pub fn fread_dio(&mut self) -> FREAD_DIO_W<'_>

Bit 23

pub fn wrsr_2b(&mut self) -> WRSR_2B_W<'_>

Bit 22

pub fn wp_reg(&mut self) -> WP_REG_W<'_>

Bit 21

pub fn fread_quad(&mut self) -> FREAD_QUAD_W<'_>

Bit 20

pub fn resandres(&mut self) -> RESANDRES_W<'_>

Bit 15

pub fn fread_dual(&mut self) -> FREAD_DUAL_W<'_>

Bit 14

pub fn fastrd_mode(&mut self) -> FASTRD_MODE_W<'_>

Bit 13

pub fn wait_flash_idle_en(&mut self) -> WAIT_FLASH_IDLE_EN_W<'_>

Bit 12

pub fn tx_crc_en(&mut self) -> TX_CRC_EN_W<'_>

Bit 11

pub fn fcs_crc_en(&mut self) -> FCS_CRC_EN_W<'_>

Bit 10

impl W<u32, Reg<u32, _CTRL1>>

pub fn cs_hold_delay(&mut self) -> CS_HOLD_DELAY_W<'_>

Bits 28:31

pub fn cs_hold_delay_res(&mut self) -> CS_HOLD_DELAY_RES_W<'_>

Bits 16:27

impl W<u32, Reg<u32, _RD_STATUS>>

pub fn status_ext(&mut self) -> STATUS_EXT_W<'_>

Bits 24:31

pub fn wb_mode(&mut self) -> WB_MODE_W<'_>

Bits 16:23

pub fn status(&mut self) -> STATUS_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CTRL2>>

pub fn cs_delay_num(&mut self) -> CS_DELAY_NUM_W<'_>

Bits 28:31

pub fn cs_delay_mode(&mut self) -> CS_DELAY_MODE_W<'_>

Bits 26:27

pub fn mosi_delay_num(&mut self) -> MOSI_DELAY_NUM_W<'_>

Bits 23:25

pub fn mosi_delay_mode(&mut self) -> MOSI_DELAY_MODE_W<'_>

Bits 21:22

pub fn miso_delay_num(&mut self) -> MISO_DELAY_NUM_W<'_>

Bits 18:20

pub fn miso_delay_mode(&mut self) -> MISO_DELAY_MODE_W<'_>

Bits 16:17

pub fn ck_out_high_mode(&mut self) -> CK_OUT_HIGH_MODE_W<'_>

Bits 12:15

pub fn ck_out_low_mode(&mut self) -> CK_OUT_LOW_MODE_W<'_>

Bits 8:11

pub fn hold_time(&mut self) -> HOLD_TIME_W<'_>

Bits 4:7

pub fn setup_time(&mut self) -> SETUP_TIME_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _CLOCK>>

pub fn clk_equ_sysclk(&mut self) -> CLK_EQU_SYSCLK_W<'_>

Bit 31

pub fn clkdiv_pre(&mut self) -> CLKDIV_PRE_W<'_>

Bits 18:30

pub fn clkcnt_n(&mut self) -> CLKCNT_N_W<'_>

Bits 12:17

pub fn clkcnt_h(&mut self) -> CLKCNT_H_W<'_>

Bits 6:11

pub fn clkcnt_l(&mut self) -> CLKCNT_L_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _USER>>

pub fn usr_command(&mut self) -> USR_COMMAND_W<'_>

Bit 31

pub fn usr_addr(&mut self) -> USR_ADDR_W<'_>

Bit 30

pub fn usr_dummy(&mut self) -> USR_DUMMY_W<'_>

Bit 29

pub fn usr_miso(&mut self) -> USR_MISO_W<'_>

Bit 28

pub fn usr_mosi(&mut self) -> USR_MOSI_W<'_>

Bit 27

pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<'_>

Bit 26

pub fn usr_mosi_highpart(&mut self) -> USR_MOSI_HIGHPART_W<'_>

Bit 25

pub fn usr_miso_highpart(&mut self) -> USR_MISO_HIGHPART_W<'_>

Bit 24

pub fn usr_prep_hold(&mut self) -> USR_PREP_HOLD_W<'_>

Bit 23

pub fn usr_cmd_hold(&mut self) -> USR_CMD_HOLD_W<'_>

Bit 22

pub fn usr_addr_hold(&mut self) -> USR_ADDR_HOLD_W<'_>

Bit 21

pub fn usr_dummy_hold(&mut self) -> USR_DUMMY_HOLD_W<'_>

Bit 20

pub fn usr_din_hold(&mut self) -> USR_DIN_HOLD_W<'_>

Bit 19

pub fn usr_dout_hold(&mut self) -> USR_DOUT_HOLD_W<'_>

Bit 18

pub fn usr_hold_pol(&mut self) -> USR_HOLD_POL_W<'_>

Bit 17

pub fn sio(&mut self) -> SIO_W<'_>

Bit 16

pub fn fwrite_qio(&mut self) -> FWRITE_QIO_W<'_>

Bit 15

pub fn fwrite_dio(&mut self) -> FWRITE_DIO_W<'_>

Bit 14

pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<'_>

Bit 13

pub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<'_>

Bit 12

pub fn wr_byte_order(&mut self) -> WR_BYTE_ORDER_W<'_>

Bit 11

pub fn rd_byte_order(&mut self) -> RD_BYTE_ORDER_W<'_>

Bit 10

pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<'_>

Bit 7

pub fn ck_i_edge(&mut self) -> CK_I_EDGE_W<'_>

Bit 6

pub fn cs_setup(&mut self) -> CS_SETUP_W<'_>

Bit 5

pub fn cs_hold(&mut self) -> CS_HOLD_W<'_>

Bit 4

pub fn doutdin(&mut self) -> DOUTDIN_W<'_>

Bit 0

impl W<u32, Reg<u32, _USER1>>

pub fn usr_addr_bitlen(&mut self) -> USR_ADDR_BITLEN_W<'_>

Bits 26:31

pub fn usr_dummy_cyclelen(&mut self) -> USR_DUMMY_CYCLELEN_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _USER2>>

pub fn usr_command_bitlen(&mut self) -> USR_COMMAND_BITLEN_W<'_>

Bits 28:31

pub fn usr_command_value(&mut self) -> USR_COMMAND_VALUE_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _MOSI_DLEN>>

pub fn usr_mosi_dbitlen(&mut self) -> USR_MOSI_DBITLEN_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _MISO_DLEN>>

pub fn usr_miso_dbitlen(&mut self) -> USR_MISO_DBITLEN_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _SLV_WR_STATUS>>

pub fn slv_wr_st(&mut self) -> SLV_WR_ST_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _PIN>>

pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<'_>

Bit 30

pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<'_>

Bit 29

pub fn master_ck_sel(&mut self) -> MASTER_CK_SEL_W<'_>

Bits 11:13

pub fn master_cs_pol(&mut self) -> MASTER_CS_POL_W<'_>

Bits 6:8

pub fn ck_dis(&mut self) -> CK_DIS_W<'_>

Bit 5

pub fn cs2_dis(&mut self) -> CS2_DIS_W<'_>

Bit 2

pub fn cs1_dis(&mut self) -> CS1_DIS_W<'_>

Bit 1

pub fn cs0_dis(&mut self) -> CS0_DIS_W<'_>

Bit 0

impl W<u32, Reg<u32, _SLAVE>>

pub fn sync_reset(&mut self) -> SYNC_RESET_W<'_>

Bit 31

pub fn slave_mode(&mut self) -> SLAVE_MODE_W<'_>

Bit 30

pub fn slv_wr_rd_buf_en(&mut self) -> SLV_WR_RD_BUF_EN_W<'_>

Bit 29

pub fn slv_wr_rd_sta_en(&mut self) -> SLV_WR_RD_STA_EN_W<'_>

Bit 28

pub fn slv_cmd_define(&mut self) -> SLV_CMD_DEFINE_W<'_>

Bit 27

pub fn trans_cnt(&mut self) -> TRANS_CNT_W<'_>

Bits 23:26

pub fn slv_last_state(&mut self) -> SLV_LAST_STATE_W<'_>

Bits 20:22

pub fn slv_last_command(&mut self) -> SLV_LAST_COMMAND_W<'_>

Bits 17:19

pub fn cs_i_mode(&mut self) -> CS_I_MODE_W<'_>

Bits 10:11

pub fn int_en(&mut self) -> INT_EN_W<'_>

Bits 5:9

pub fn trans_done(&mut self) -> TRANS_DONE_W<'_>

Bit 4

pub fn slv_wr_sta_done(&mut self) -> SLV_WR_STA_DONE_W<'_>

Bit 3

pub fn slv_rd_sta_done(&mut self) -> SLV_RD_STA_DONE_W<'_>

Bit 2

pub fn slv_wr_buf_done(&mut self) -> SLV_WR_BUF_DONE_W<'_>

Bit 1

pub fn slv_rd_buf_done(&mut self) -> SLV_RD_BUF_DONE_W<'_>

Bit 0

impl W<u32, Reg<u32, _SLAVE1>>

pub fn slv_status_bitlen(&mut self) -> SLV_STATUS_BITLEN_W<'_>

Bits 27:31

pub fn slv_status_fast_en(&mut self) -> SLV_STATUS_FAST_EN_W<'_>

Bit 26

pub fn slv_status_readback(&mut self) -> SLV_STATUS_READBACK_W<'_>

Bit 25

pub fn slv_rd_addr_bitlen(&mut self) -> SLV_RD_ADDR_BITLEN_W<'_>

Bits 10:15

pub fn slv_wr_addr_bitlen(&mut self) -> SLV_WR_ADDR_BITLEN_W<'_>

Bits 4:9

pub fn slv_wrsta_dummy_en(&mut self) -> SLV_WRSTA_DUMMY_EN_W<'_>

Bit 3

pub fn slv_rdsta_dummy_en(&mut self) -> SLV_RDSTA_DUMMY_EN_W<'_>

Bit 2

pub fn slv_wrbuf_dummy_en(&mut self) -> SLV_WRBUF_DUMMY_EN_W<'_>

Bit 1

pub fn slv_rdbuf_dummy_en(&mut self) -> SLV_RDBUF_DUMMY_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _SLAVE2>>

pub fn slv_wrbuf_dummy_cyclelen(&mut self) -> SLV_WRBUF_DUMMY_CYCLELEN_W<'_>

Bits 24:31

pub fn slv_rdbuf_dummy_cyclelen(&mut self) -> SLV_RDBUF_DUMMY_CYCLELEN_W<'_>

Bits 16:23

pub fn slv_wrsta_dummy_cyclelen(&mut self) -> SLV_WRSTA_DUMMY_CYCLELEN_W<'_>

Bits 8:15

pub fn slv_rdsta_dummy_cyclelen(&mut self) -> SLV_RDSTA_DUMMY_CYCLELEN_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SLAVE3>>

pub fn slv_wrsta_cmd_value(&mut self) -> SLV_WRSTA_CMD_VALUE_W<'_>

Bits 24:31

pub fn slv_rdsta_cmd_value(&mut self) -> SLV_RDSTA_CMD_VALUE_W<'_>

Bits 16:23

pub fn slv_wrbuf_cmd_value(&mut self) -> SLV_WRBUF_CMD_VALUE_W<'_>

Bits 8:15

pub fn slv_rdbuf_cmd_value(&mut self) -> SLV_RDBUF_CMD_VALUE_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SLV_WRBUF_DLEN>>

pub fn slv_wrbuf_dbitlen(&mut self) -> SLV_WRBUF_DBITLEN_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _SLV_RDBUF_DLEN>>

pub fn slv_rdbuf_dbitlen(&mut self) -> SLV_RDBUF_DBITLEN_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _CACHE_FCTRL>>

pub fn cache_flash_pes_en(&mut self) -> CACHE_FLASH_PES_EN_W<'_>

Bit 3

pub fn cache_flash_usr_cmd(&mut self) -> CACHE_FLASH_USR_CMD_W<'_>

Bit 2

pub fn cache_usr_cmd_4byte(&mut self) -> CACHE_USR_CMD_4BYTE_W<'_>

Bit 1

pub fn cache_req_en(&mut self) -> CACHE_REQ_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _CACHE_SCTRL>>

pub fn cache_sram_usr_wcmd(&mut self) -> CACHE_SRAM_USR_WCMD_W<'_>

Bit 28

pub fn sram_addr_bitlen(&mut self) -> SRAM_ADDR_BITLEN_W<'_>

Bits 22:27

pub fn sram_dummy_cyclelen(&mut self) -> SRAM_DUMMY_CYCLELEN_W<'_>

Bits 14:21

pub fn sram_bytes_len(&mut self) -> SRAM_BYTES_LEN_W<'_>

Bits 6:13

pub fn cache_sram_usr_rcmd(&mut self) -> CACHE_SRAM_USR_RCMD_W<'_>

Bit 5

pub fn usr_rd_sram_dummy(&mut self) -> USR_RD_SRAM_DUMMY_W<'_>

Bit 4

pub fn usr_wr_sram_dummy(&mut self) -> USR_WR_SRAM_DUMMY_W<'_>

Bit 3

pub fn usr_sram_qio(&mut self) -> USR_SRAM_QIO_W<'_>

Bit 2

pub fn usr_sram_dio(&mut self) -> USR_SRAM_DIO_W<'_>

Bit 1

impl W<u32, Reg<u32, _SRAM_CMD>>

pub fn sram_rstio(&mut self) -> SRAM_RSTIO_W<'_>

Bit 4

pub fn sram_qio(&mut self) -> SRAM_QIO_W<'_>

Bit 1

pub fn sram_dio(&mut self) -> SRAM_DIO_W<'_>

Bit 0

impl W<u32, Reg<u32, _SRAM_DRD_CMD>>

pub fn cache_sram_usr_rd_cmd_bitlen(
    &mut self
) -> CACHE_SRAM_USR_RD_CMD_BITLEN_W<'_>

Bits 28:31

pub fn cache_sram_usr_rd_cmd_value(
    &mut self
) -> CACHE_SRAM_USR_RD_CMD_VALUE_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SRAM_DWR_CMD>>

pub fn cache_sram_usr_wr_cmd_bitlen(
    &mut self
) -> CACHE_SRAM_USR_WR_CMD_BITLEN_W<'_>

Bits 28:31

pub fn cache_sram_usr_wr_cmd_value(
    &mut self
) -> CACHE_SRAM_USR_WR_CMD_VALUE_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SLV_RD_BIT>>

pub fn slv_rdata_bit(&mut self) -> SLV_RDATA_BIT_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _W>>

pub fn buf(&mut self) -> BUF_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _TX_CRC>>

pub fn tx_crc_data(&mut self) -> TX_CRC_DATA_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _EXT0>>

pub fn t_pp_ena(&mut self) -> T_PP_ENA_W<'_>

Bit 31

pub fn t_pp_shift(&mut self) -> T_PP_SHIFT_W<'_>

Bits 16:19

pub fn t_pp_time(&mut self) -> T_PP_TIME_W<'_>

Bits 0:11

impl W<u32, Reg<u32, _EXT1>>

pub fn t_erase_ena(&mut self) -> T_ERASE_ENA_W<'_>

Bit 31

pub fn t_erase_shift(&mut self) -> T_ERASE_SHIFT_W<'_>

Bits 16:19

pub fn t_erase_time(&mut self) -> T_ERASE_TIME_W<'_>

Bits 0:11

impl W<u32, Reg<u32, _EXT2>>

pub fn st(&mut self) -> ST_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _EXT3>>

pub fn int_hold_ena(&mut self) -> INT_HOLD_ENA_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _DMA_CONF>>

pub fn dma_continue(&mut self) -> DMA_CONTINUE_W<'_>

Bit 16

pub fn dma_tx_stop(&mut self) -> DMA_TX_STOP_W<'_>

Bit 15

pub fn dma_rx_stop(&mut self) -> DMA_RX_STOP_W<'_>

Bit 14

pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<'_>

Bit 12

pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<'_>

Bit 11

pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<'_>

Bit 10

pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<'_>

Bit 9

pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<'_>

Bit 8

pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<'_>

Bit 7

pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<'_>

Bit 6

pub fn ahbm_rst(&mut self) -> AHBM_RST_W<'_>

Bit 5

pub fn ahbm_fifo_rst(&mut self) -> AHBM_FIFO_RST_W<'_>

Bit 4

pub fn out_rst(&mut self) -> OUT_RST_W<'_>

Bit 3

pub fn in_rst(&mut self) -> IN_RST_W<'_>

Bit 2

impl W<u32, Reg<u32, _DMA_OUT_LINK>>

pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<'_>

Bit 30

pub fn outlink_start(&mut self) -> OUTLINK_START_W<'_>

Bit 29

pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<'_>

Bit 28

pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _DMA_IN_LINK>>

pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<'_>

Bit 30

pub fn inlink_start(&mut self) -> INLINK_START_W<'_>

Bit 29

pub fn inlink_stop(&mut self) -> INLINK_STOP_W<'_>

Bit 28

pub fn inlink_auto_ret(&mut self) -> INLINK_AUTO_RET_W<'_>

Bit 20

pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _DMA_STATUS>>

pub fn dma_tx_en(&mut self) -> DMA_TX_EN_W<'_>

Bit 1

pub fn dma_rx_en(&mut self) -> DMA_RX_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _DMA_INT_ENA>>

pub fn out_total_eof_int_ena(&mut self) -> OUT_TOTAL_EOF_INT_ENA_W<'_>

Bit 8

pub fn out_eof_int_ena(&mut self) -> OUT_EOF_INT_ENA_W<'_>

Bit 7

pub fn out_done_int_ena(&mut self) -> OUT_DONE_INT_ENA_W<'_>

Bit 6

pub fn in_suc_eof_int_ena(&mut self) -> IN_SUC_EOF_INT_ENA_W<'_>

Bit 5

pub fn in_err_eof_int_ena(&mut self) -> IN_ERR_EOF_INT_ENA_W<'_>

Bit 4

pub fn in_done_int_ena(&mut self) -> IN_DONE_INT_ENA_W<'_>

Bit 3

pub fn inlink_dscr_error_int_ena(&mut self) -> INLINK_DSCR_ERROR_INT_ENA_W<'_>

Bit 2

pub fn outlink_dscr_error_int_ena(&mut self) -> OUTLINK_DSCR_ERROR_INT_ENA_W<'_>

Bit 1

pub fn inlink_dscr_empty_int_ena(&mut self) -> INLINK_DSCR_EMPTY_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _DMA_INT_RAW>>

pub fn out_total_eof_int_raw(&mut self) -> OUT_TOTAL_EOF_INT_RAW_W<'_>

Bit 8

pub fn out_eof_int_raw(&mut self) -> OUT_EOF_INT_RAW_W<'_>

Bit 7

pub fn out_done_int_raw(&mut self) -> OUT_DONE_INT_RAW_W<'_>

Bit 6

pub fn in_suc_eof_int_raw(&mut self) -> IN_SUC_EOF_INT_RAW_W<'_>

Bit 5

pub fn in_err_eof_int_raw(&mut self) -> IN_ERR_EOF_INT_RAW_W<'_>

Bit 4

pub fn in_done_int_raw(&mut self) -> IN_DONE_INT_RAW_W<'_>

Bit 3

pub fn inlink_dscr_error_int_raw(&mut self) -> INLINK_DSCR_ERROR_INT_RAW_W<'_>

Bit 2

pub fn outlink_dscr_error_int_raw(&mut self) -> OUTLINK_DSCR_ERROR_INT_RAW_W<'_>

Bit 1

pub fn inlink_dscr_empty_int_raw(&mut self) -> INLINK_DSCR_EMPTY_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, _DMA_INT_ST>>

pub fn out_total_eof_int_st(&mut self) -> OUT_TOTAL_EOF_INT_ST_W<'_>

Bit 8

pub fn out_eof_int_st(&mut self) -> OUT_EOF_INT_ST_W<'_>

Bit 7

pub fn out_done_int_st(&mut self) -> OUT_DONE_INT_ST_W<'_>

Bit 6

pub fn in_suc_eof_int_st(&mut self) -> IN_SUC_EOF_INT_ST_W<'_>

Bit 5

pub fn in_err_eof_int_st(&mut self) -> IN_ERR_EOF_INT_ST_W<'_>

Bit 4

pub fn in_done_int_st(&mut self) -> IN_DONE_INT_ST_W<'_>

Bit 3

pub fn inlink_dscr_error_int_st(&mut self) -> INLINK_DSCR_ERROR_INT_ST_W<'_>

Bit 2

pub fn outlink_dscr_error_int_st(&mut self) -> OUTLINK_DSCR_ERROR_INT_ST_W<'_>

Bit 1

pub fn inlink_dscr_empty_int_st(&mut self) -> INLINK_DSCR_EMPTY_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, _DMA_INT_CLR>>

pub fn out_total_eof_int_clr(&mut self) -> OUT_TOTAL_EOF_INT_CLR_W<'_>

Bit 8

pub fn out_eof_int_clr(&mut self) -> OUT_EOF_INT_CLR_W<'_>

Bit 7

pub fn out_done_int_clr(&mut self) -> OUT_DONE_INT_CLR_W<'_>

Bit 6

pub fn in_suc_eof_int_clr(&mut self) -> IN_SUC_EOF_INT_CLR_W<'_>

Bit 5

pub fn in_err_eof_int_clr(&mut self) -> IN_ERR_EOF_INT_CLR_W<'_>

Bit 4

pub fn in_done_int_clr(&mut self) -> IN_DONE_INT_CLR_W<'_>

Bit 3

pub fn inlink_dscr_error_int_clr(&mut self) -> INLINK_DSCR_ERROR_INT_CLR_W<'_>

Bit 2

pub fn outlink_dscr_error_int_clr(&mut self) -> OUTLINK_DSCR_ERROR_INT_CLR_W<'_>

Bit 1

pub fn inlink_dscr_empty_int_clr(&mut self) -> INLINK_DSCR_EMPTY_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, _IN_ERR_EOF_DES_ADDR>>

pub fn dma_in_err_eof_des_addr(&mut self) -> DMA_IN_ERR_EOF_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _IN_SUC_EOF_DES_ADDR>>

pub fn dma_in_suc_eof_des_addr(&mut self) -> DMA_IN_SUC_EOF_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _INLINK_DSCR>>

pub fn dma_inlink_dscr(&mut self) -> DMA_INLINK_DSCR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _INLINK_DSCR_BF0>>

pub fn dma_inlink_dscr_bf0(&mut self) -> DMA_INLINK_DSCR_BF0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _INLINK_DSCR_BF1>>

pub fn dma_inlink_dscr_bf1(&mut self) -> DMA_INLINK_DSCR_BF1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _OUT_EOF_BFR_DES_ADDR>>

pub fn dma_out_eof_bfr_des_addr(&mut self) -> DMA_OUT_EOF_BFR_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _OUT_EOF_DES_ADDR>>

pub fn dma_out_eof_des_addr(&mut self) -> DMA_OUT_EOF_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _OUTLINK_DSCR>>

pub fn dma_outlink_dscr(&mut self) -> DMA_OUTLINK_DSCR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _OUTLINK_DSCR_BF0>>

pub fn dma_outlink_dscr_bf0(&mut self) -> DMA_OUTLINK_DSCR_BF0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _OUTLINK_DSCR_BF1>>

pub fn dma_outlink_dscr_bf1(&mut self) -> DMA_OUTLINK_DSCR_BF1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DMA_RSTATUS>>

pub fn dma_out_status(&mut self) -> DMA_OUT_STATUS_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DMA_TSTATUS>>

pub fn dma_in_status(&mut self) -> DMA_IN_STATUS_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DATE>>

pub fn date(&mut self) -> DATE_W<'_>

Bits 0:27

impl W<u32, Reg<u32, _SCL_LOW_PERIOD>>

pub fn period(&mut self) -> PERIOD_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _CTR>>

pub fn clk_en(&mut self) -> CLK_EN_W<'_>

Bit 8

pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<'_>

Bit 7

pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<'_>

Bit 6

pub fn trans_start(&mut self) -> TRANS_START_W<'_>

Bit 5

pub fn ms_mode(&mut self) -> MS_MODE_W<'_>

Bit 4

pub fn sample_scl_level(&mut self) -> SAMPLE_SCL_LEVEL_W<'_>

Bit 2

pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<'_>

Bit 1

pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<'_>

Bit 0

impl W<u32, Reg<u32, _SR>>

pub fn scl_state_last(&mut self) -> SCL_STATE_LAST_W<'_>

Bits 28:30

pub fn scl_main_state_last(&mut self) -> SCL_MAIN_STATE_LAST_W<'_>

Bits 24:26

pub fn txfifo_cnt(&mut self) -> TXFIFO_CNT_W<'_>

Bits 18:23

pub fn rxfifo_cnt(&mut self) -> RXFIFO_CNT_W<'_>

Bits 8:13

pub fn byte_trans(&mut self) -> BYTE_TRANS_W<'_>

Bit 6

pub fn slave_addressed(&mut self) -> SLAVE_ADDRESSED_W<'_>

Bit 5

pub fn bus_busy(&mut self) -> BUS_BUSY_W<'_>

Bit 4

pub fn arb_lost(&mut self) -> ARB_LOST_W<'_>

Bit 3

pub fn time_out(&mut self) -> TIME_OUT_W<'_>

Bit 2

pub fn slave_rw(&mut self) -> SLAVE_RW_W<'_>

Bit 1

pub fn ack_rec(&mut self) -> ACK_REC_W<'_>

Bit 0

impl W<u32, Reg<u32, _TO>>

pub fn time_out_reg(&mut self) -> TIME_OUT_REG_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _SLAVE_ADDR>>

pub fn addr_10bit_en(&mut self) -> ADDR_10BIT_EN_W<'_>

Bit 31

pub fn slave_addr(&mut self) -> SLAVE_ADDR_W<'_>

Bits 0:14

impl W<u32, Reg<u32, _RXFIFO_ST>>

pub fn txfifo_end_addr(&mut self) -> TXFIFO_END_ADDR_W<'_>

Bits 15:19

pub fn txfifo_start_addr(&mut self) -> TXFIFO_START_ADDR_W<'_>

Bits 10:14

pub fn rxfifo_end_addr(&mut self) -> RXFIFO_END_ADDR_W<'_>

Bits 5:9

pub fn rxfifo_start_addr(&mut self) -> RXFIFO_START_ADDR_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _FIFO_CONF>>

pub fn nonfifo_tx_thres(&mut self) -> NONFIFO_TX_THRES_W<'_>

Bits 20:25

pub fn nonfifo_rx_thres(&mut self) -> NONFIFO_RX_THRES_W<'_>

Bits 14:19

pub fn tx_fifo_rst(&mut self) -> TX_FIFO_RST_W<'_>

Bit 13

pub fn rx_fifo_rst(&mut self) -> RX_FIFO_RST_W<'_>

Bit 12

pub fn fifo_addr_cfg_en(&mut self) -> FIFO_ADDR_CFG_EN_W<'_>

Bit 11

pub fn nonfifo_en(&mut self) -> NONFIFO_EN_W<'_>

Bit 10

pub fn txfifo_empty_thrhd(&mut self) -> TXFIFO_EMPTY_THRHD_W<'_>

Bits 5:9

pub fn rxfifo_full_thrhd(&mut self) -> RXFIFO_FULL_THRHD_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _DATA>>

pub fn fifo_rdata(&mut self) -> FIFO_RDATA_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _INT_RAW>>

pub fn tx_send_empty_int_raw(&mut self) -> TX_SEND_EMPTY_INT_RAW_W<'_>

Bit 12

pub fn rx_rec_full_int_raw(&mut self) -> RX_REC_FULL_INT_RAW_W<'_>

Bit 11

pub fn ack_err_int_raw(&mut self) -> ACK_ERR_INT_RAW_W<'_>

Bit 10

pub fn trans_start_int_raw(&mut self) -> TRANS_START_INT_RAW_W<'_>

Bit 9

pub fn time_out_int_raw(&mut self) -> TIME_OUT_INT_RAW_W<'_>

Bit 8

pub fn trans_complete_int_raw(&mut self) -> TRANS_COMPLETE_INT_RAW_W<'_>

Bit 7

pub fn master_tran_comp_int_raw(&mut self) -> MASTER_TRAN_COMP_INT_RAW_W<'_>

Bit 6

pub fn arbitration_lost_int_raw(&mut self) -> ARBITRATION_LOST_INT_RAW_W<'_>

Bit 5

pub fn slave_tran_comp_int_raw(&mut self) -> SLAVE_TRAN_COMP_INT_RAW_W<'_>

Bit 4

pub fn end_detect_int_raw(&mut self) -> END_DETECT_INT_RAW_W<'_>

Bit 3

pub fn rxfifo_ovf_int_raw(&mut self) -> RXFIFO_OVF_INT_RAW_W<'_>

Bit 2

pub fn txfifo_empty_int_raw(&mut self) -> TXFIFO_EMPTY_INT_RAW_W<'_>

Bit 1

pub fn rxfifo_full_int_raw(&mut self) -> RXFIFO_FULL_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_CLR>>

pub fn tx_send_empty_int_clr(&mut self) -> TX_SEND_EMPTY_INT_CLR_W<'_>

Bit 12

pub fn rx_rec_full_int_clr(&mut self) -> RX_REC_FULL_INT_CLR_W<'_>

Bit 11

pub fn ack_err_int_clr(&mut self) -> ACK_ERR_INT_CLR_W<'_>

Bit 10

pub fn trans_start_int_clr(&mut self) -> TRANS_START_INT_CLR_W<'_>

Bit 9

pub fn time_out_int_clr(&mut self) -> TIME_OUT_INT_CLR_W<'_>

Bit 8

pub fn trans_complete_int_clr(&mut self) -> TRANS_COMPLETE_INT_CLR_W<'_>

Bit 7

pub fn master_tran_comp_int_clr(&mut self) -> MASTER_TRAN_COMP_INT_CLR_W<'_>

Bit 6

pub fn arbitration_lost_int_clr(&mut self) -> ARBITRATION_LOST_INT_CLR_W<'_>

Bit 5

pub fn slave_tran_comp_int_clr(&mut self) -> SLAVE_TRAN_COMP_INT_CLR_W<'_>

Bit 4

pub fn end_detect_int_clr(&mut self) -> END_DETECT_INT_CLR_W<'_>

Bit 3

pub fn rxfifo_ovf_int_clr(&mut self) -> RXFIFO_OVF_INT_CLR_W<'_>

Bit 2

pub fn txfifo_empty_int_clr(&mut self) -> TXFIFO_EMPTY_INT_CLR_W<'_>

Bit 1

pub fn rxfifo_full_int_clr(&mut self) -> RXFIFO_FULL_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ENA>>

pub fn tx_send_empty_int_ena(&mut self) -> TX_SEND_EMPTY_INT_ENA_W<'_>

Bit 12

pub fn rx_rec_full_int_ena(&mut self) -> RX_REC_FULL_INT_ENA_W<'_>

Bit 11

pub fn ack_err_int_ena(&mut self) -> ACK_ERR_INT_ENA_W<'_>

Bit 10

pub fn trans_start_int_ena(&mut self) -> TRANS_START_INT_ENA_W<'_>

Bit 9

pub fn time_out_int_ena(&mut self) -> TIME_OUT_INT_ENA_W<'_>

Bit 8

pub fn trans_complete_int_ena(&mut self) -> TRANS_COMPLETE_INT_ENA_W<'_>

Bit 7

pub fn master_tran_comp_int_ena(&mut self) -> MASTER_TRAN_COMP_INT_ENA_W<'_>

Bit 6

pub fn arbitration_lost_int_ena(&mut self) -> ARBITRATION_LOST_INT_ENA_W<'_>

Bit 5

pub fn slave_tran_comp_int_ena(&mut self) -> SLAVE_TRAN_COMP_INT_ENA_W<'_>

Bit 4

pub fn end_detect_int_ena(&mut self) -> END_DETECT_INT_ENA_W<'_>

Bit 3

pub fn rxfifo_ovf_int_ena(&mut self) -> RXFIFO_OVF_INT_ENA_W<'_>

Bit 2

pub fn txfifo_empty_int_ena(&mut self) -> TXFIFO_EMPTY_INT_ENA_W<'_>

Bit 1

pub fn rxfifo_full_int_ena(&mut self) -> RXFIFO_FULL_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_STATUS>>

pub fn tx_send_empty_int_st(&mut self) -> TX_SEND_EMPTY_INT_ST_W<'_>

Bit 12

pub fn rx_rec_full_int_st(&mut self) -> RX_REC_FULL_INT_ST_W<'_>

Bit 11

pub fn ack_err_int_st(&mut self) -> ACK_ERR_INT_ST_W<'_>

Bit 10

pub fn trans_start_int_st(&mut self) -> TRANS_START_INT_ST_W<'_>

Bit 9

pub fn time_out_int_st(&mut self) -> TIME_OUT_INT_ST_W<'_>

Bit 8

pub fn trans_complete_int_st(&mut self) -> TRANS_COMPLETE_INT_ST_W<'_>

Bit 7

pub fn master_tran_comp_int_st(&mut self) -> MASTER_TRAN_COMP_INT_ST_W<'_>

Bit 6

pub fn arbitration_lost_int_st(&mut self) -> ARBITRATION_LOST_INT_ST_W<'_>

Bit 5

pub fn slave_tran_comp_int_st(&mut self) -> SLAVE_TRAN_COMP_INT_ST_W<'_>

Bit 4

pub fn end_detect_int_st(&mut self) -> END_DETECT_INT_ST_W<'_>

Bit 3

pub fn rxfifo_ovf_int_st(&mut self) -> RXFIFO_OVF_INT_ST_W<'_>

Bit 2

pub fn txfifo_empty_int_st(&mut self) -> TXFIFO_EMPTY_INT_ST_W<'_>

Bit 1

pub fn rxfifo_full_int_st(&mut self) -> RXFIFO_FULL_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, _SDA_HOLD>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _SDA_SAMPLE>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _SCL_HIGH_PERIOD>>

pub fn period(&mut self) -> PERIOD_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _SCL_START_HOLD>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _SCL_RSTART_SETUP>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _SCL_STOP_HOLD>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _SCL_STOP_SETUP>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _SCL_FILTER_CFG>>

pub fn scl_filter_en(&mut self) -> SCL_FILTER_EN_W<'_>

Bit 3

pub fn scl_filter_thres(&mut self) -> SCL_FILTER_THRES_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _SDA_FILTER_CFG>>

pub fn sda_filter_en(&mut self) -> SDA_FILTER_EN_W<'_>

Bit 3

pub fn sda_filter_thres(&mut self) -> SDA_FILTER_THRES_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _COMD0>>

pub fn command0_done(&mut self) -> COMMAND0_DONE_W<'_>

Bit 31

pub fn command0(&mut self) -> COMMAND0_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _COMD1>>

pub fn command1_done(&mut self) -> COMMAND1_DONE_W<'_>

Bit 31

pub fn command1(&mut self) -> COMMAND1_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _COMD2>>

pub fn command2_done(&mut self) -> COMMAND2_DONE_W<'_>

Bit 31

pub fn command2(&mut self) -> COMMAND2_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _COMD3>>

pub fn command3_done(&mut self) -> COMMAND3_DONE_W<'_>

Bit 31

pub fn command3(&mut self) -> COMMAND3_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _COMD4>>

pub fn command4_done(&mut self) -> COMMAND4_DONE_W<'_>

Bit 31

pub fn command4(&mut self) -> COMMAND4_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _COMD5>>

pub fn command5_done(&mut self) -> COMMAND5_DONE_W<'_>

Bit 31

pub fn command5(&mut self) -> COMMAND5_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _COMD6>>

pub fn command6_done(&mut self) -> COMMAND6_DONE_W<'_>

Bit 31

pub fn command6(&mut self) -> COMMAND6_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _COMD7>>

pub fn command7_done(&mut self) -> COMMAND7_DONE_W<'_>

Bit 31

pub fn command7(&mut self) -> COMMAND7_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _COMD8>>

pub fn command8_done(&mut self) -> COMMAND8_DONE_W<'_>

Bit 31

pub fn command8(&mut self) -> COMMAND8_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _COMD9>>

pub fn command9_done(&mut self) -> COMMAND9_DONE_W<'_>

Bit 31

pub fn command9(&mut self) -> COMMAND9_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _COMD10>>

pub fn command10_done(&mut self) -> COMMAND10_DONE_W<'_>

Bit 31

pub fn command10(&mut self) -> COMMAND10_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _COMD11>>

pub fn command11_done(&mut self) -> COMMAND11_DONE_W<'_>

Bit 31

pub fn command11(&mut self) -> COMMAND11_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _COMD12>>

pub fn command12_done(&mut self) -> COMMAND12_DONE_W<'_>

Bit 31

pub fn command12(&mut self) -> COMMAND12_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _COMD13>>

pub fn command13_done(&mut self) -> COMMAND13_DONE_W<'_>

Bit 31

pub fn command13(&mut self) -> COMMAND13_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _COMD14>>

pub fn command14_done(&mut self) -> COMMAND14_DONE_W<'_>

Bit 31

pub fn command14(&mut self) -> COMMAND14_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _COMD15>>

pub fn command15_done(&mut self) -> COMMAND15_DONE_W<'_>

Bit 31

pub fn command15(&mut self) -> COMMAND15_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _DATE>>

pub fn date(&mut self) -> DATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK0_RDATA0>>

pub fn rd_flash_crypt_cnt(&mut self) -> RD_FLASH_CRYPT_CNT_W<'_>

Bits 20:26

pub fn rd_efuse_rd_dis(&mut self) -> RD_EFUSE_RD_DIS_W<'_>

Bits 16:19

impl W<u32, Reg<u32, _BLK0_RDATA1>>

pub fn rd_wifi_mac_crc_low(&mut self) -> RD_WIFI_MAC_CRC_LOW_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK0_RDATA2>>

pub fn rd_wifi_mac_crc_high(&mut self) -> RD_WIFI_MAC_CRC_HIGH_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _BLK0_RDATA3>>

pub fn rd_chip_ver_rev1(&mut self) -> RD_CHIP_VER_REV1_W<'_>

Bit 15

pub fn rd_chip_cpu_freq_rated(&mut self) -> RD_CHIP_CPU_FREQ_RATED_W<'_>

Bit 13

pub fn rd_chip_cpu_freq_low(&mut self) -> RD_CHIP_CPU_FREQ_LOW_W<'_>

Bit 12

pub fn rd_chip_ver_pkg(&mut self) -> RD_CHIP_VER_PKG_W<'_>

Bits 9:11

pub fn rd_spi_pad_config_hd(&mut self) -> RD_SPI_PAD_CONFIG_HD_W<'_>

Bits 4:8

pub fn rd_chip_ver_dis_cache(&mut self) -> RD_CHIP_VER_DIS_CACHE_W<'_>

Bit 3

pub fn rd_chip_ver_32pad(&mut self) -> RD_CHIP_VER_32PAD_W<'_>

Bit 2

pub fn rd_chip_ver_dis_bt(&mut self) -> RD_CHIP_VER_DIS_BT_W<'_>

Bit 1

pub fn rd_chip_ver_dis_app_cpu(&mut self) -> RD_CHIP_VER_DIS_APP_CPU_W<'_>

Bit 0

impl W<u32, Reg<u32, _BLK0_RDATA4>>

pub fn rd_sdio_force(&mut self) -> RD_SDIO_FORCE_W<'_>

Bit 16

pub fn rd_sdio_tieh(&mut self) -> RD_SDIO_TIEH_W<'_>

Bit 15

pub fn rd_xpd_sdio_reg(&mut self) -> RD_XPD_SDIO_REG_W<'_>

Bit 14

pub fn rd_adc_vref(&mut self) -> RD_ADC_VREF_W<'_>

Bits 8:12

pub fn rd_sdio_drefl(&mut self) -> RD_SDIO_DREFL_W<'_>

Bits 12:13

pub fn rd_sdio_drefm(&mut self) -> RD_SDIO_DREFM_W<'_>

Bits 10:11

pub fn rd_sdio_drefh(&mut self) -> RD_SDIO_DREFH_W<'_>

Bits 8:9

pub fn rd_ck8m_freq(&mut self) -> RD_CK8M_FREQ_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _BLK0_RDATA5>>

pub fn rd_flash_crypt_config(&mut self) -> RD_FLASH_CRYPT_CONFIG_W<'_>

Bits 28:31

pub fn rd_inst_config(&mut self) -> RD_INST_CONFIG_W<'_>

Bits 20:27

pub fn rd_spi_pad_config_d(&mut self) -> RD_SPI_PAD_CONFIG_D_W<'_>

Bits 10:14

pub fn rd_spi_pad_config_q(&mut self) -> RD_SPI_PAD_CONFIG_Q_W<'_>

Bits 5:9

pub fn rd_spi_pad_config_clk(&mut self) -> RD_SPI_PAD_CONFIG_CLK_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _BLK0_RDATA6>>

pub fn rd_key_status(&mut self) -> RD_KEY_STATUS_W<'_>

Bit 10

pub fn rd_disable_dl_cache(&mut self) -> RD_DISABLE_DL_CACHE_W<'_>

Bit 9

pub fn rd_disable_dl_decrypt(&mut self) -> RD_DISABLE_DL_DECRYPT_W<'_>

Bit 8

pub fn rd_disable_dl_encrypt(&mut self) -> RD_DISABLE_DL_ENCRYPT_W<'_>

Bit 7

pub fn rd_disable_jtag(&mut self) -> RD_DISABLE_JTAG_W<'_>

Bit 6

pub fn rd_abs_done_1(&mut self) -> RD_ABS_DONE_1_W<'_>

Bit 5

pub fn rd_abs_done_0(&mut self) -> RD_ABS_DONE_0_W<'_>

Bit 4

pub fn rd_disable_sdio_host(&mut self) -> RD_DISABLE_SDIO_HOST_W<'_>

Bit 3

pub fn rd_console_debug_disable(&mut self) -> RD_CONSOLE_DEBUG_DISABLE_W<'_>

Bit 2

pub fn rd_coding_scheme(&mut self) -> RD_CODING_SCHEME_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _BLK0_WDATA0>>

pub fn flash_crypt_cnt(&mut self) -> FLASH_CRYPT_CNT_W<'_>

Bits 20:26

pub fn rd_dis(&mut self) -> RD_DIS_W<'_>

Bits 16:19

pub fn wr_dis(&mut self) -> WR_DIS_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _BLK0_WDATA1>>

pub fn wifi_mac_crc_low(&mut self) -> WIFI_MAC_CRC_LOW_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK0_WDATA2>>

pub fn wifi_mac_crc_high(&mut self) -> WIFI_MAC_CRC_HIGH_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _BLK0_WDATA3>>

pub fn chip_ver_rev1(&mut self) -> CHIP_VER_REV1_W<'_>

Bit 15

pub fn chip_cpu_freq_rated(&mut self) -> CHIP_CPU_FREQ_RATED_W<'_>

Bit 13

pub fn chip_cpu_freq_low(&mut self) -> CHIP_CPU_FREQ_LOW_W<'_>

Bit 12

pub fn chip_ver_pkg(&mut self) -> CHIP_VER_PKG_W<'_>

Bits 9:11

pub fn spi_pad_config_hd(&mut self) -> SPI_PAD_CONFIG_HD_W<'_>

Bits 4:8

pub fn chip_ver_dis_cache(&mut self) -> CHIP_VER_DIS_CACHE_W<'_>

Bit 3

pub fn chip_ver_32pad(&mut self) -> CHIP_VER_32PAD_W<'_>

Bit 2

pub fn chip_ver_dis_bt(&mut self) -> CHIP_VER_DIS_BT_W<'_>

Bit 1

pub fn chip_ver_dis_app_cpu(&mut self) -> CHIP_VER_DIS_APP_CPU_W<'_>

Bit 0

impl W<u32, Reg<u32, _BLK0_WDATA4>>

pub fn sdio_force(&mut self) -> SDIO_FORCE_W<'_>

Bit 16

pub fn sdio_tieh(&mut self) -> SDIO_TIEH_W<'_>

Bit 15

pub fn xpd_sdio_reg(&mut self) -> XPD_SDIO_REG_W<'_>

Bit 14

pub fn adc_vref(&mut self) -> ADC_VREF_W<'_>

Bits 8:12

pub fn sdio_drefl(&mut self) -> SDIO_DREFL_W<'_>

Bits 12:13

pub fn sdio_drefm(&mut self) -> SDIO_DREFM_W<'_>

Bits 10:11

pub fn sdio_drefh(&mut self) -> SDIO_DREFH_W<'_>

Bits 8:9

pub fn ck8m_freq(&mut self) -> CK8M_FREQ_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _BLK0_WDATA5>>

pub fn flash_crypt_config(&mut self) -> FLASH_CRYPT_CONFIG_W<'_>

Bits 28:31

pub fn inst_config(&mut self) -> INST_CONFIG_W<'_>

Bits 20:27

pub fn spi_pad_config_d(&mut self) -> SPI_PAD_CONFIG_D_W<'_>

Bits 10:14

pub fn spi_pad_config_q(&mut self) -> SPI_PAD_CONFIG_Q_W<'_>

Bits 5:9

pub fn spi_pad_config_clk(&mut self) -> SPI_PAD_CONFIG_CLK_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _BLK0_WDATA6>>

pub fn key_status(&mut self) -> KEY_STATUS_W<'_>

Bit 10

pub fn disable_dl_cache(&mut self) -> DISABLE_DL_CACHE_W<'_>

Bit 9

pub fn disable_dl_decrypt(&mut self) -> DISABLE_DL_DECRYPT_W<'_>

Bit 8

pub fn disable_dl_encrypt(&mut self) -> DISABLE_DL_ENCRYPT_W<'_>

Bit 7

pub fn disable_jtag(&mut self) -> DISABLE_JTAG_W<'_>

Bit 6

pub fn abs_done_1(&mut self) -> ABS_DONE_1_W<'_>

Bit 5

pub fn abs_done_0(&mut self) -> ABS_DONE_0_W<'_>

Bit 4

pub fn disable_sdio_host(&mut self) -> DISABLE_SDIO_HOST_W<'_>

Bit 3

pub fn console_debug_disable(&mut self) -> CONSOLE_DEBUG_DISABLE_W<'_>

Bit 2

pub fn coding_scheme(&mut self) -> CODING_SCHEME_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _BLK1_RDATA0>>

pub fn blk1_dout0(&mut self) -> BLK1_DOUT0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK1_RDATA1>>

pub fn blk1_dout1(&mut self) -> BLK1_DOUT1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK1_RDATA2>>

pub fn blk1_dout2(&mut self) -> BLK1_DOUT2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK1_RDATA3>>

pub fn blk1_dout3(&mut self) -> BLK1_DOUT3_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK1_RDATA4>>

pub fn blk1_dout4(&mut self) -> BLK1_DOUT4_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK1_RDATA5>>

pub fn blk1_dout5(&mut self) -> BLK1_DOUT5_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK1_RDATA6>>

pub fn blk1_dout6(&mut self) -> BLK1_DOUT6_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK1_RDATA7>>

pub fn blk1_dout7(&mut self) -> BLK1_DOUT7_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_RDATA0>>

pub fn blk2_dout0(&mut self) -> BLK2_DOUT0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_RDATA1>>

pub fn blk2_dout1(&mut self) -> BLK2_DOUT1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_RDATA2>>

pub fn blk2_dout2(&mut self) -> BLK2_DOUT2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_RDATA3>>

pub fn blk2_dout3(&mut self) -> BLK2_DOUT3_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_RDATA4>>

pub fn blk2_dout4(&mut self) -> BLK2_DOUT4_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_RDATA5>>

pub fn blk2_dout5(&mut self) -> BLK2_DOUT5_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_RDATA6>>

pub fn blk2_dout6(&mut self) -> BLK2_DOUT6_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_RDATA7>>

pub fn blk2_dout7(&mut self) -> BLK2_DOUT7_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK3_RDATA0>>

pub fn blk3_dout0(&mut self) -> BLK3_DOUT0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK3_RDATA1>>

pub fn blk3_dout1(&mut self) -> BLK3_DOUT1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK3_RDATA2>>

pub fn blk3_dout2(&mut self) -> BLK3_DOUT2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK3_RDATA3>>

pub fn blk3_dout3(&mut self) -> BLK3_DOUT3_W<'_>

Bits 0:31

pub fn rd_adc2_tp_high(&mut self) -> RD_ADC2_TP_HIGH_W<'_>

Bits 23:31

pub fn rd_adc2_tp_low(&mut self) -> RD_ADC2_TP_LOW_W<'_>

Bits 16:22

pub fn rd_adc1_tp_high(&mut self) -> RD_ADC1_TP_HIGH_W<'_>

Bits 7:15

pub fn rd_adc1_tp_low(&mut self) -> RD_ADC1_TP_LOW_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _BLK3_RDATA4>>

pub fn blk3_dout4(&mut self) -> BLK3_DOUT4_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK3_RDATA5>>

pub fn blk3_dout5(&mut self) -> BLK3_DOUT5_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK3_RDATA6>>

pub fn blk3_dout6(&mut self) -> BLK3_DOUT6_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK3_RDATA7>>

pub fn blk3_dout7(&mut self) -> BLK3_DOUT7_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK1_WDATA0>>

pub fn blk1_din0(&mut self) -> BLK1_DIN0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK1_WDATA1>>

pub fn blk1_din1(&mut self) -> BLK1_DIN1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK1_WDATA2>>

pub fn blk1_din2(&mut self) -> BLK1_DIN2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK1_WDATA3>>

pub fn blk1_din3(&mut self) -> BLK1_DIN3_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK1_WDATA4>>

pub fn blk1_din4(&mut self) -> BLK1_DIN4_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK1_WDATA5>>

pub fn blk1_din5(&mut self) -> BLK1_DIN5_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK1_WDATA6>>

pub fn blk1_din6(&mut self) -> BLK1_DIN6_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK1_WDATA7>>

pub fn blk1_din7(&mut self) -> BLK1_DIN7_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_WDATA0>>

pub fn blk2_din0(&mut self) -> BLK2_DIN0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_WDATA1>>

pub fn blk2_din1(&mut self) -> BLK2_DIN1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_WDATA2>>

pub fn blk2_din2(&mut self) -> BLK2_DIN2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_WDATA3>>

pub fn blk2_din3(&mut self) -> BLK2_DIN3_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_WDATA4>>

pub fn blk2_din4(&mut self) -> BLK2_DIN4_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_WDATA5>>

pub fn blk2_din5(&mut self) -> BLK2_DIN5_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_WDATA6>>

pub fn blk2_din6(&mut self) -> BLK2_DIN6_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK2_WDATA7>>

pub fn blk2_din7(&mut self) -> BLK2_DIN7_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK3_WDATA0>>

pub fn blk3_din0(&mut self) -> BLK3_DIN0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK3_WDATA1>>

pub fn blk3_din1(&mut self) -> BLK3_DIN1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK3_WDATA2>>

pub fn blk3_din2(&mut self) -> BLK3_DIN2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK3_WDATA3>>

pub fn blk3_din3(&mut self) -> BLK3_DIN3_W<'_>

Bits 0:31

pub fn adc2_tp_high(&mut self) -> ADC2_TP_HIGH_W<'_>

Bits 23:31

pub fn adc2_tp_low(&mut self) -> ADC2_TP_LOW_W<'_>

Bits 16:22

pub fn adc1_tp_high(&mut self) -> ADC1_TP_HIGH_W<'_>

Bits 7:15

pub fn adc1_tp_low(&mut self) -> ADC1_TP_LOW_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _BLK3_WDATA4>>

pub fn blk3_din4(&mut self) -> BLK3_DIN4_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK3_WDATA5>>

pub fn blk3_din5(&mut self) -> BLK3_DIN5_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK3_WDATA6>>

pub fn blk3_din6(&mut self) -> BLK3_DIN6_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BLK3_WDATA7>>

pub fn blk3_din7(&mut self) -> BLK3_DIN7_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CLK>>

pub fn clk_en(&mut self) -> CLK_EN_W<'_>

Bit 16

pub fn clk_sel1(&mut self) -> CLK_SEL1_W<'_>

Bits 8:15

pub fn clk_sel0(&mut self) -> CLK_SEL0_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CONF>>

pub fn force_no_wr_rd_dis(&mut self) -> FORCE_NO_WR_RD_DIS_W<'_>

Bit 16

pub fn op_code(&mut self) -> OP_CODE_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _STATUS>>

pub fn debug(&mut self) -> DEBUG_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CMD>>

pub fn pgm_cmd(&mut self) -> PGM_CMD_W<'_>

Bit 1

pub fn read_cmd(&mut self) -> READ_CMD_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_RAW>>

pub fn pgm_done_int_raw(&mut self) -> PGM_DONE_INT_RAW_W<'_>

Bit 1

pub fn read_done_int_raw(&mut self) -> READ_DONE_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ST>>

pub fn pgm_done_int_st(&mut self) -> PGM_DONE_INT_ST_W<'_>

Bit 1

pub fn read_done_int_st(&mut self) -> READ_DONE_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ENA>>

pub fn pgm_done_int_ena(&mut self) -> PGM_DONE_INT_ENA_W<'_>

Bit 1

pub fn read_done_int_ena(&mut self) -> READ_DONE_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_CLR>>

pub fn pgm_done_int_clr(&mut self) -> PGM_DONE_INT_CLR_W<'_>

Bit 1

pub fn read_done_int_clr(&mut self) -> READ_DONE_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, _DAC_CONF>>

pub fn dac_clk_pad_sel(&mut self) -> DAC_CLK_PAD_SEL_W<'_>

Bit 8

pub fn dac_clk_div(&mut self) -> DAC_CLK_DIV_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _DEC_STATUS>>

pub fn dec_warnings(&mut self) -> DEC_WARNINGS_W<'_>

Bits 0:11

impl W<u32, Reg<u32, _DATE>>

pub fn date(&mut self) -> DATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _U0_CONF0>>

pub fn ch1_lctrl_mode_u0(&mut self) -> CH1_LCTRL_MODE_U0_W<'_>

Bits 30:31

pub fn ch1_hctrl_mode_u0(&mut self) -> CH1_HCTRL_MODE_U0_W<'_>

Bits 28:29

pub fn ch1_pos_mode_u0(&mut self) -> CH1_POS_MODE_U0_W<'_>

Bits 26:27

pub fn ch1_neg_mode_u0(&mut self) -> CH1_NEG_MODE_U0_W<'_>

Bits 24:25

pub fn ch0_lctrl_mode_u0(&mut self) -> CH0_LCTRL_MODE_U0_W<'_>

Bits 22:23

pub fn ch0_hctrl_mode_u0(&mut self) -> CH0_HCTRL_MODE_U0_W<'_>

Bits 20:21

pub fn ch0_pos_mode_u0(&mut self) -> CH0_POS_MODE_U0_W<'_>

Bits 18:19

pub fn ch0_neg_mode_u0(&mut self) -> CH0_NEG_MODE_U0_W<'_>

Bits 16:17

pub fn thr_thres1_en_u0(&mut self) -> THR_THRES1_EN_U0_W<'_>

Bit 15

pub fn thr_thres0_en_u0(&mut self) -> THR_THRES0_EN_U0_W<'_>

Bit 14

pub fn thr_l_lim_en_u0(&mut self) -> THR_L_LIM_EN_U0_W<'_>

Bit 13

pub fn thr_h_lim_en_u0(&mut self) -> THR_H_LIM_EN_U0_W<'_>

Bit 12

pub fn thr_zero_en_u0(&mut self) -> THR_ZERO_EN_U0_W<'_>

Bit 11

pub fn filter_en_u0(&mut self) -> FILTER_EN_U0_W<'_>

Bit 10

pub fn filter_thres_u0(&mut self) -> FILTER_THRES_U0_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _U0_CONF1>>

pub fn cnt_thres1_u0(&mut self) -> CNT_THRES1_U0_W<'_>

Bits 16:31

pub fn cnt_thres0_u0(&mut self) -> CNT_THRES0_U0_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U0_CONF2>>

pub fn cnt_l_lim_u0(&mut self) -> CNT_L_LIM_U0_W<'_>

Bits 16:31

pub fn cnt_h_lim_u0(&mut self) -> CNT_H_LIM_U0_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U1_CONF0>>

pub fn ch1_lctrl_mode_u1(&mut self) -> CH1_LCTRL_MODE_U1_W<'_>

Bits 30:31

pub fn ch1_hctrl_mode_u1(&mut self) -> CH1_HCTRL_MODE_U1_W<'_>

Bits 28:29

pub fn ch1_pos_mode_u1(&mut self) -> CH1_POS_MODE_U1_W<'_>

Bits 26:27

pub fn ch1_neg_mode_u1(&mut self) -> CH1_NEG_MODE_U1_W<'_>

Bits 24:25

pub fn ch0_lctrl_mode_u1(&mut self) -> CH0_LCTRL_MODE_U1_W<'_>

Bits 22:23

pub fn ch0_hctrl_mode_u1(&mut self) -> CH0_HCTRL_MODE_U1_W<'_>

Bits 20:21

pub fn ch0_pos_mode_u1(&mut self) -> CH0_POS_MODE_U1_W<'_>

Bits 18:19

pub fn ch0_neg_mode_u1(&mut self) -> CH0_NEG_MODE_U1_W<'_>

Bits 16:17

pub fn thr_thres1_en_u1(&mut self) -> THR_THRES1_EN_U1_W<'_>

Bit 15

pub fn thr_thres0_en_u1(&mut self) -> THR_THRES0_EN_U1_W<'_>

Bit 14

pub fn thr_l_lim_en_u1(&mut self) -> THR_L_LIM_EN_U1_W<'_>

Bit 13

pub fn thr_h_lim_en_u1(&mut self) -> THR_H_LIM_EN_U1_W<'_>

Bit 12

pub fn thr_zero_en_u1(&mut self) -> THR_ZERO_EN_U1_W<'_>

Bit 11

pub fn filter_en_u1(&mut self) -> FILTER_EN_U1_W<'_>

Bit 10

pub fn filter_thres_u1(&mut self) -> FILTER_THRES_U1_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _U1_CONF1>>

pub fn cnt_thres1_u1(&mut self) -> CNT_THRES1_U1_W<'_>

Bits 16:31

pub fn cnt_thres0_u1(&mut self) -> CNT_THRES0_U1_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U1_CONF2>>

pub fn cnt_l_lim_u1(&mut self) -> CNT_L_LIM_U1_W<'_>

Bits 16:31

pub fn cnt_h_lim_u1(&mut self) -> CNT_H_LIM_U1_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U2_CONF0>>

pub fn ch1_lctrl_mode_u2(&mut self) -> CH1_LCTRL_MODE_U2_W<'_>

Bits 30:31

pub fn ch1_hctrl_mode_u2(&mut self) -> CH1_HCTRL_MODE_U2_W<'_>

Bits 28:29

pub fn ch1_pos_mode_u2(&mut self) -> CH1_POS_MODE_U2_W<'_>

Bits 26:27

pub fn ch1_neg_mode_u2(&mut self) -> CH1_NEG_MODE_U2_W<'_>

Bits 24:25

pub fn ch0_lctrl_mode_u2(&mut self) -> CH0_LCTRL_MODE_U2_W<'_>

Bits 22:23

pub fn ch0_hctrl_mode_u2(&mut self) -> CH0_HCTRL_MODE_U2_W<'_>

Bits 20:21

pub fn ch0_pos_mode_u2(&mut self) -> CH0_POS_MODE_U2_W<'_>

Bits 18:19

pub fn ch0_neg_mode_u2(&mut self) -> CH0_NEG_MODE_U2_W<'_>

Bits 16:17

pub fn thr_thres1_en_u2(&mut self) -> THR_THRES1_EN_U2_W<'_>

Bit 15

pub fn thr_thres0_en_u2(&mut self) -> THR_THRES0_EN_U2_W<'_>

Bit 14

pub fn thr_l_lim_en_u2(&mut self) -> THR_L_LIM_EN_U2_W<'_>

Bit 13

pub fn thr_h_lim_en_u2(&mut self) -> THR_H_LIM_EN_U2_W<'_>

Bit 12

pub fn thr_zero_en_u2(&mut self) -> THR_ZERO_EN_U2_W<'_>

Bit 11

pub fn filter_en_u2(&mut self) -> FILTER_EN_U2_W<'_>

Bit 10

pub fn filter_thres_u2(&mut self) -> FILTER_THRES_U2_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _U2_CONF1>>

pub fn cnt_thres1_u2(&mut self) -> CNT_THRES1_U2_W<'_>

Bits 16:31

pub fn cnt_thres0_u2(&mut self) -> CNT_THRES0_U2_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U2_CONF2>>

pub fn cnt_l_lim_u2(&mut self) -> CNT_L_LIM_U2_W<'_>

Bits 16:31

pub fn cnt_h_lim_u2(&mut self) -> CNT_H_LIM_U2_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U3_CONF0>>

pub fn ch1_lctrl_mode_u3(&mut self) -> CH1_LCTRL_MODE_U3_W<'_>

Bits 30:31

pub fn ch1_hctrl_mode_u3(&mut self) -> CH1_HCTRL_MODE_U3_W<'_>

Bits 28:29

pub fn ch1_pos_mode_u3(&mut self) -> CH1_POS_MODE_U3_W<'_>

Bits 26:27

pub fn ch1_neg_mode_u3(&mut self) -> CH1_NEG_MODE_U3_W<'_>

Bits 24:25

pub fn ch0_lctrl_mode_u3(&mut self) -> CH0_LCTRL_MODE_U3_W<'_>

Bits 22:23

pub fn ch0_hctrl_mode_u3(&mut self) -> CH0_HCTRL_MODE_U3_W<'_>

Bits 20:21

pub fn ch0_pos_mode_u3(&mut self) -> CH0_POS_MODE_U3_W<'_>

Bits 18:19

pub fn ch0_neg_mode_u3(&mut self) -> CH0_NEG_MODE_U3_W<'_>

Bits 16:17

pub fn thr_thres1_en_u3(&mut self) -> THR_THRES1_EN_U3_W<'_>

Bit 15

pub fn thr_thres0_en_u3(&mut self) -> THR_THRES0_EN_U3_W<'_>

Bit 14

pub fn thr_l_lim_en_u3(&mut self) -> THR_L_LIM_EN_U3_W<'_>

Bit 13

pub fn thr_h_lim_en_u3(&mut self) -> THR_H_LIM_EN_U3_W<'_>

Bit 12

pub fn thr_zero_en_u3(&mut self) -> THR_ZERO_EN_U3_W<'_>

Bit 11

pub fn filter_en_u3(&mut self) -> FILTER_EN_U3_W<'_>

Bit 10

pub fn filter_thres_u3(&mut self) -> FILTER_THRES_U3_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _U3_CONF1>>

pub fn cnt_thres1_u3(&mut self) -> CNT_THRES1_U3_W<'_>

Bits 16:31

pub fn cnt_thres0_u3(&mut self) -> CNT_THRES0_U3_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U3_CONF2>>

pub fn cnt_l_lim_u3(&mut self) -> CNT_L_LIM_U3_W<'_>

Bits 16:31

pub fn cnt_h_lim_u3(&mut self) -> CNT_H_LIM_U3_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U4_CONF0>>

pub fn ch1_lctrl_mode_u4(&mut self) -> CH1_LCTRL_MODE_U4_W<'_>

Bits 30:31

pub fn ch1_hctrl_mode_u4(&mut self) -> CH1_HCTRL_MODE_U4_W<'_>

Bits 28:29

pub fn ch1_pos_mode_u4(&mut self) -> CH1_POS_MODE_U4_W<'_>

Bits 26:27

pub fn ch1_neg_mode_u4(&mut self) -> CH1_NEG_MODE_U4_W<'_>

Bits 24:25

pub fn ch0_lctrl_mode_u4(&mut self) -> CH0_LCTRL_MODE_U4_W<'_>

Bits 22:23

pub fn ch0_hctrl_mode_u4(&mut self) -> CH0_HCTRL_MODE_U4_W<'_>

Bits 20:21

pub fn ch0_pos_mode_u4(&mut self) -> CH0_POS_MODE_U4_W<'_>

Bits 18:19

pub fn ch0_neg_mode_u4(&mut self) -> CH0_NEG_MODE_U4_W<'_>

Bits 16:17

pub fn thr_thres1_en_u4(&mut self) -> THR_THRES1_EN_U4_W<'_>

Bit 15

pub fn thr_thres0_en_u4(&mut self) -> THR_THRES0_EN_U4_W<'_>

Bit 14

pub fn thr_l_lim_en_u4(&mut self) -> THR_L_LIM_EN_U4_W<'_>

Bit 13

pub fn thr_h_lim_en_u4(&mut self) -> THR_H_LIM_EN_U4_W<'_>

Bit 12

pub fn thr_zero_en_u4(&mut self) -> THR_ZERO_EN_U4_W<'_>

Bit 11

pub fn filter_en_u4(&mut self) -> FILTER_EN_U4_W<'_>

Bit 10

pub fn filter_thres_u4(&mut self) -> FILTER_THRES_U4_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _U4_CONF1>>

pub fn cnt_thres1_u4(&mut self) -> CNT_THRES1_U4_W<'_>

Bits 16:31

pub fn cnt_thres0_u4(&mut self) -> CNT_THRES0_U4_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U4_CONF2>>

pub fn cnt_l_lim_u4(&mut self) -> CNT_L_LIM_U4_W<'_>

Bits 16:31

pub fn cnt_h_lim_u4(&mut self) -> CNT_H_LIM_U4_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U5_CONF0>>

pub fn ch1_lctrl_mode_u5(&mut self) -> CH1_LCTRL_MODE_U5_W<'_>

Bits 30:31

pub fn ch1_hctrl_mode_u5(&mut self) -> CH1_HCTRL_MODE_U5_W<'_>

Bits 28:29

pub fn ch1_pos_mode_u5(&mut self) -> CH1_POS_MODE_U5_W<'_>

Bits 26:27

pub fn ch1_neg_mode_u5(&mut self) -> CH1_NEG_MODE_U5_W<'_>

Bits 24:25

pub fn ch0_lctrl_mode_u5(&mut self) -> CH0_LCTRL_MODE_U5_W<'_>

Bits 22:23

pub fn ch0_hctrl_mode_u5(&mut self) -> CH0_HCTRL_MODE_U5_W<'_>

Bits 20:21

pub fn ch0_pos_mode_u5(&mut self) -> CH0_POS_MODE_U5_W<'_>

Bits 18:19

pub fn ch0_neg_mode_u5(&mut self) -> CH0_NEG_MODE_U5_W<'_>

Bits 16:17

pub fn thr_thres1_en_u5(&mut self) -> THR_THRES1_EN_U5_W<'_>

Bit 15

pub fn thr_thres0_en_u5(&mut self) -> THR_THRES0_EN_U5_W<'_>

Bit 14

pub fn thr_l_lim_en_u5(&mut self) -> THR_L_LIM_EN_U5_W<'_>

Bit 13

pub fn thr_h_lim_en_u5(&mut self) -> THR_H_LIM_EN_U5_W<'_>

Bit 12

pub fn thr_zero_en_u5(&mut self) -> THR_ZERO_EN_U5_W<'_>

Bit 11

pub fn filter_en_u5(&mut self) -> FILTER_EN_U5_W<'_>

Bit 10

pub fn filter_thres_u5(&mut self) -> FILTER_THRES_U5_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _U5_CONF1>>

pub fn cnt_thres1_u5(&mut self) -> CNT_THRES1_U5_W<'_>

Bits 16:31

pub fn cnt_thres0_u5(&mut self) -> CNT_THRES0_U5_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U5_CONF2>>

pub fn cnt_l_lim_u5(&mut self) -> CNT_L_LIM_U5_W<'_>

Bits 16:31

pub fn cnt_h_lim_u5(&mut self) -> CNT_H_LIM_U5_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U6_CONF0>>

pub fn ch1_lctrl_mode_u6(&mut self) -> CH1_LCTRL_MODE_U6_W<'_>

Bits 30:31

pub fn ch1_hctrl_mode_u6(&mut self) -> CH1_HCTRL_MODE_U6_W<'_>

Bits 28:29

pub fn ch1_pos_mode_u6(&mut self) -> CH1_POS_MODE_U6_W<'_>

Bits 26:27

pub fn ch1_neg_mode_u6(&mut self) -> CH1_NEG_MODE_U6_W<'_>

Bits 24:25

pub fn ch0_lctrl_mode_u6(&mut self) -> CH0_LCTRL_MODE_U6_W<'_>

Bits 22:23

pub fn ch0_hctrl_mode_u6(&mut self) -> CH0_HCTRL_MODE_U6_W<'_>

Bits 20:21

pub fn ch0_pos_mode_u6(&mut self) -> CH0_POS_MODE_U6_W<'_>

Bits 18:19

pub fn ch0_neg_mode_u6(&mut self) -> CH0_NEG_MODE_U6_W<'_>

Bits 16:17

pub fn thr_thres1_en_u6(&mut self) -> THR_THRES1_EN_U6_W<'_>

Bit 15

pub fn thr_thres0_en_u6(&mut self) -> THR_THRES0_EN_U6_W<'_>

Bit 14

pub fn thr_l_lim_en_u6(&mut self) -> THR_L_LIM_EN_U6_W<'_>

Bit 13

pub fn thr_h_lim_en_u6(&mut self) -> THR_H_LIM_EN_U6_W<'_>

Bit 12

pub fn thr_zero_en_u6(&mut self) -> THR_ZERO_EN_U6_W<'_>

Bit 11

pub fn filter_en_u6(&mut self) -> FILTER_EN_U6_W<'_>

Bit 10

pub fn filter_thres_u6(&mut self) -> FILTER_THRES_U6_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _U6_CONF1>>

pub fn cnt_thres1_u6(&mut self) -> CNT_THRES1_U6_W<'_>

Bits 16:31

pub fn cnt_thres0_u6(&mut self) -> CNT_THRES0_U6_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U6_CONF2>>

pub fn cnt_l_lim_u6(&mut self) -> CNT_L_LIM_U6_W<'_>

Bits 16:31

pub fn cnt_h_lim_u6(&mut self) -> CNT_H_LIM_U6_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U7_CONF0>>

pub fn ch1_lctrl_mode_u7(&mut self) -> CH1_LCTRL_MODE_U7_W<'_>

Bits 30:31

pub fn ch1_hctrl_mode_u7(&mut self) -> CH1_HCTRL_MODE_U7_W<'_>

Bits 28:29

pub fn ch1_pos_mode_u7(&mut self) -> CH1_POS_MODE_U7_W<'_>

Bits 26:27

pub fn ch1_neg_mode_u7(&mut self) -> CH1_NEG_MODE_U7_W<'_>

Bits 24:25

pub fn ch0_lctrl_mode_u7(&mut self) -> CH0_LCTRL_MODE_U7_W<'_>

Bits 22:23

pub fn ch0_hctrl_mode_u7(&mut self) -> CH0_HCTRL_MODE_U7_W<'_>

Bits 20:21

pub fn ch0_pos_mode_u7(&mut self) -> CH0_POS_MODE_U7_W<'_>

Bits 18:19

pub fn ch0_neg_mode_u7(&mut self) -> CH0_NEG_MODE_U7_W<'_>

Bits 16:17

pub fn thr_thres1_en_u7(&mut self) -> THR_THRES1_EN_U7_W<'_>

Bit 15

pub fn thr_thres0_en_u7(&mut self) -> THR_THRES0_EN_U7_W<'_>

Bit 14

pub fn thr_l_lim_en_u7(&mut self) -> THR_L_LIM_EN_U7_W<'_>

Bit 13

pub fn thr_h_lim_en_u7(&mut self) -> THR_H_LIM_EN_U7_W<'_>

Bit 12

pub fn thr_zero_en_u7(&mut self) -> THR_ZERO_EN_U7_W<'_>

Bit 11

pub fn filter_en_u7(&mut self) -> FILTER_EN_U7_W<'_>

Bit 10

pub fn filter_thres_u7(&mut self) -> FILTER_THRES_U7_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _U7_CONF1>>

pub fn cnt_thres1_u7(&mut self) -> CNT_THRES1_U7_W<'_>

Bits 16:31

pub fn cnt_thres0_u7(&mut self) -> CNT_THRES0_U7_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U7_CONF2>>

pub fn cnt_l_lim_u7(&mut self) -> CNT_L_LIM_U7_W<'_>

Bits 16:31

pub fn cnt_h_lim_u7(&mut self) -> CNT_H_LIM_U7_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U0_CNT>>

pub fn plus_cnt_u0(&mut self) -> PLUS_CNT_U0_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U1_CNT>>

pub fn plus_cnt_u1(&mut self) -> PLUS_CNT_U1_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U2_CNT>>

pub fn plus_cnt_u2(&mut self) -> PLUS_CNT_U2_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U3_CNT>>

pub fn plus_cnt_u3(&mut self) -> PLUS_CNT_U3_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U4_CNT>>

pub fn plus_cnt_u4(&mut self) -> PLUS_CNT_U4_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U5_CNT>>

pub fn plus_cnt_u5(&mut self) -> PLUS_CNT_U5_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U6_CNT>>

pub fn plus_cnt_u6(&mut self) -> PLUS_CNT_U6_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _U7_CNT>>

pub fn plus_cnt_u7(&mut self) -> PLUS_CNT_U7_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _INT_RAW>>

pub fn cnt_thr_event_u7_int_raw(&mut self) -> CNT_THR_EVENT_U7_INT_RAW_W<'_>

Bit 7

pub fn cnt_thr_event_u6_int_raw(&mut self) -> CNT_THR_EVENT_U6_INT_RAW_W<'_>

Bit 6

pub fn cnt_thr_event_u5_int_raw(&mut self) -> CNT_THR_EVENT_U5_INT_RAW_W<'_>

Bit 5

pub fn cnt_thr_event_u4_int_raw(&mut self) -> CNT_THR_EVENT_U4_INT_RAW_W<'_>

Bit 4

pub fn cnt_thr_event_u3_int_raw(&mut self) -> CNT_THR_EVENT_U3_INT_RAW_W<'_>

Bit 3

pub fn cnt_thr_event_u2_int_raw(&mut self) -> CNT_THR_EVENT_U2_INT_RAW_W<'_>

Bit 2

pub fn cnt_thr_event_u1_int_raw(&mut self) -> CNT_THR_EVENT_U1_INT_RAW_W<'_>

Bit 1

pub fn cnt_thr_event_u0_int_raw(&mut self) -> CNT_THR_EVENT_U0_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ST>>

pub fn cnt_thr_event_u7_int_st(&mut self) -> CNT_THR_EVENT_U7_INT_ST_W<'_>

Bit 7

pub fn cnt_thr_event_u6_int_st(&mut self) -> CNT_THR_EVENT_U6_INT_ST_W<'_>

Bit 6

pub fn cnt_thr_event_u5_int_st(&mut self) -> CNT_THR_EVENT_U5_INT_ST_W<'_>

Bit 5

pub fn cnt_thr_event_u4_int_st(&mut self) -> CNT_THR_EVENT_U4_INT_ST_W<'_>

Bit 4

pub fn cnt_thr_event_u3_int_st(&mut self) -> CNT_THR_EVENT_U3_INT_ST_W<'_>

Bit 3

pub fn cnt_thr_event_u2_int_st(&mut self) -> CNT_THR_EVENT_U2_INT_ST_W<'_>

Bit 2

pub fn cnt_thr_event_u1_int_st(&mut self) -> CNT_THR_EVENT_U1_INT_ST_W<'_>

Bit 1

pub fn cnt_thr_event_u0_int_st(&mut self) -> CNT_THR_EVENT_U0_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ENA>>

pub fn cnt_thr_event_u7_int_ena(&mut self) -> CNT_THR_EVENT_U7_INT_ENA_W<'_>

Bit 7

pub fn cnt_thr_event_u6_int_ena(&mut self) -> CNT_THR_EVENT_U6_INT_ENA_W<'_>

Bit 6

pub fn cnt_thr_event_u5_int_ena(&mut self) -> CNT_THR_EVENT_U5_INT_ENA_W<'_>

Bit 5

pub fn cnt_thr_event_u4_int_ena(&mut self) -> CNT_THR_EVENT_U4_INT_ENA_W<'_>

Bit 4

pub fn cnt_thr_event_u3_int_ena(&mut self) -> CNT_THR_EVENT_U3_INT_ENA_W<'_>

Bit 3

pub fn cnt_thr_event_u2_int_ena(&mut self) -> CNT_THR_EVENT_U2_INT_ENA_W<'_>

Bit 2

pub fn cnt_thr_event_u1_int_ena(&mut self) -> CNT_THR_EVENT_U1_INT_ENA_W<'_>

Bit 1

pub fn cnt_thr_event_u0_int_ena(&mut self) -> CNT_THR_EVENT_U0_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_CLR>>

pub fn cnt_thr_event_u7_int_clr(&mut self) -> CNT_THR_EVENT_U7_INT_CLR_W<'_>

Bit 7

pub fn cnt_thr_event_u6_int_clr(&mut self) -> CNT_THR_EVENT_U6_INT_CLR_W<'_>

Bit 6

pub fn cnt_thr_event_u5_int_clr(&mut self) -> CNT_THR_EVENT_U5_INT_CLR_W<'_>

Bit 5

pub fn cnt_thr_event_u4_int_clr(&mut self) -> CNT_THR_EVENT_U4_INT_CLR_W<'_>

Bit 4

pub fn cnt_thr_event_u3_int_clr(&mut self) -> CNT_THR_EVENT_U3_INT_CLR_W<'_>

Bit 3

pub fn cnt_thr_event_u2_int_clr(&mut self) -> CNT_THR_EVENT_U2_INT_CLR_W<'_>

Bit 2

pub fn cnt_thr_event_u1_int_clr(&mut self) -> CNT_THR_EVENT_U1_INT_CLR_W<'_>

Bit 1

pub fn cnt_thr_event_u0_int_clr(&mut self) -> CNT_THR_EVENT_U0_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, _U0_STATUS>>

pub fn core_status_u0(&mut self) -> CORE_STATUS_U0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _U1_STATUS>>

pub fn core_status_u1(&mut self) -> CORE_STATUS_U1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _U2_STATUS>>

pub fn core_status_u2(&mut self) -> CORE_STATUS_U2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _U3_STATUS>>

pub fn core_status_u3(&mut self) -> CORE_STATUS_U3_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _U4_STATUS>>

pub fn core_status_u4(&mut self) -> CORE_STATUS_U4_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _U5_STATUS>>

pub fn core_status_u5(&mut self) -> CORE_STATUS_U5_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _U6_STATUS>>

pub fn core_status_u6(&mut self) -> CORE_STATUS_U6_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _U7_STATUS>>

pub fn core_status_u7(&mut self) -> CORE_STATUS_U7_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CTRL>>

pub fn clk_en(&mut self) -> CLK_EN_W<'_>

Bit 16

pub fn cnt_pause_u7(&mut self) -> CNT_PAUSE_U7_W<'_>

Bit 15

pub fn plus_cnt_rst_u7(&mut self) -> PLUS_CNT_RST_U7_W<'_>

Bit 14

pub fn cnt_pause_u6(&mut self) -> CNT_PAUSE_U6_W<'_>

Bit 13

pub fn plus_cnt_rst_u6(&mut self) -> PLUS_CNT_RST_U6_W<'_>

Bit 12

pub fn cnt_pause_u5(&mut self) -> CNT_PAUSE_U5_W<'_>

Bit 11

pub fn plus_cnt_rst_u5(&mut self) -> PLUS_CNT_RST_U5_W<'_>

Bit 10

pub fn cnt_pause_u4(&mut self) -> CNT_PAUSE_U4_W<'_>

Bit 9

pub fn plus_cnt_rst_u4(&mut self) -> PLUS_CNT_RST_U4_W<'_>

Bit 8

pub fn cnt_pause_u3(&mut self) -> CNT_PAUSE_U3_W<'_>

Bit 7

pub fn plus_cnt_rst_u3(&mut self) -> PLUS_CNT_RST_U3_W<'_>

Bit 6

pub fn cnt_pause_u2(&mut self) -> CNT_PAUSE_U2_W<'_>

Bit 5

pub fn plus_cnt_rst_u2(&mut self) -> PLUS_CNT_RST_U2_W<'_>

Bit 4

pub fn cnt_pause_u1(&mut self) -> CNT_PAUSE_U1_W<'_>

Bit 3

pub fn plus_cnt_rst_u1(&mut self) -> PLUS_CNT_RST_U1_W<'_>

Bit 2

pub fn cnt_pause_u0(&mut self) -> CNT_PAUSE_U0_W<'_>

Bit 1

pub fn plus_cnt_rst_u0(&mut self) -> PLUS_CNT_RST_U0_W<'_>

Bit 0

impl W<u32, Reg<u32, _DATE>>

pub fn date(&mut self) -> DATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CH0CONF0>>

pub fn clk_en(&mut self) -> CLK_EN_W<'_>

Bit 31

pub fn mem_pd(&mut self) -> MEM_PD_W<'_>

Bit 30

pub fn carrier_out_lv_ch0(&mut self) -> CARRIER_OUT_LV_CH0_W<'_>

Bit 29

pub fn carrier_en_ch0(&mut self) -> CARRIER_EN_CH0_W<'_>

Bit 28

pub fn mem_size_ch0(&mut self) -> MEM_SIZE_CH0_W<'_>

Bits 24:27

pub fn idle_thres_ch0(&mut self) -> IDLE_THRES_CH0_W<'_>

Bits 8:23

pub fn div_cnt_ch0(&mut self) -> DIV_CNT_CH0_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CH0CONF1>>

pub fn idle_out_en_ch0(&mut self) -> IDLE_OUT_EN_CH0_W<'_>

Bit 19

pub fn idle_out_lv_ch0(&mut self) -> IDLE_OUT_LV_CH0_W<'_>

Bit 18

pub fn ref_always_on_ch0(&mut self) -> REF_ALWAYS_ON_CH0_W<'_>

Bit 17

pub fn ref_cnt_rst_ch0(&mut self) -> REF_CNT_RST_CH0_W<'_>

Bit 16

pub fn rx_filter_thres_ch0(&mut self) -> RX_FILTER_THRES_CH0_W<'_>

Bits 8:15

pub fn rx_filter_en_ch0(&mut self) -> RX_FILTER_EN_CH0_W<'_>

Bit 7

pub fn tx_conti_mode_ch0(&mut self) -> TX_CONTI_MODE_CH0_W<'_>

Bit 6

pub fn mem_owner_ch0(&mut self) -> MEM_OWNER_CH0_W<'_>

Bit 5

pub fn apb_mem_rst_ch0(&mut self) -> APB_MEM_RST_CH0_W<'_>

Bit 4

pub fn mem_rd_rst_ch0(&mut self) -> MEM_RD_RST_CH0_W<'_>

Bit 3

pub fn mem_wr_rst_ch0(&mut self) -> MEM_WR_RST_CH0_W<'_>

Bit 2

pub fn rx_en_ch0(&mut self) -> RX_EN_CH0_W<'_>

Bit 1

pub fn tx_start_ch0(&mut self) -> TX_START_CH0_W<'_>

Bit 0

impl W<u32, Reg<u32, _CH1CONF0>>

pub fn carrier_out_lv_ch1(&mut self) -> CARRIER_OUT_LV_CH1_W<'_>

Bit 29

pub fn carrier_en_ch1(&mut self) -> CARRIER_EN_CH1_W<'_>

Bit 28

pub fn mem_size_ch1(&mut self) -> MEM_SIZE_CH1_W<'_>

Bits 24:27

pub fn idle_thres_ch1(&mut self) -> IDLE_THRES_CH1_W<'_>

Bits 8:23

pub fn div_cnt_ch1(&mut self) -> DIV_CNT_CH1_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CH1CONF1>>

pub fn idle_out_en_ch1(&mut self) -> IDLE_OUT_EN_CH1_W<'_>

Bit 19

pub fn idle_out_lv_ch1(&mut self) -> IDLE_OUT_LV_CH1_W<'_>

Bit 18

pub fn ref_always_on_ch1(&mut self) -> REF_ALWAYS_ON_CH1_W<'_>

Bit 17

pub fn ref_cnt_rst_ch1(&mut self) -> REF_CNT_RST_CH1_W<'_>

Bit 16

pub fn rx_filter_thres_ch1(&mut self) -> RX_FILTER_THRES_CH1_W<'_>

Bits 8:15

pub fn rx_filter_en_ch1(&mut self) -> RX_FILTER_EN_CH1_W<'_>

Bit 7

pub fn tx_conti_mode_ch1(&mut self) -> TX_CONTI_MODE_CH1_W<'_>

Bit 6

pub fn mem_owner_ch1(&mut self) -> MEM_OWNER_CH1_W<'_>

Bit 5

pub fn apb_mem_rst_ch1(&mut self) -> APB_MEM_RST_CH1_W<'_>

Bit 4

pub fn mem_rd_rst_ch1(&mut self) -> MEM_RD_RST_CH1_W<'_>

Bit 3

pub fn mem_wr_rst_ch1(&mut self) -> MEM_WR_RST_CH1_W<'_>

Bit 2

pub fn rx_en_ch1(&mut self) -> RX_EN_CH1_W<'_>

Bit 1

pub fn tx_start_ch1(&mut self) -> TX_START_CH1_W<'_>

Bit 0

impl W<u32, Reg<u32, _CH2CONF0>>

pub fn carrier_out_lv_ch2(&mut self) -> CARRIER_OUT_LV_CH2_W<'_>

Bit 29

pub fn carrier_en_ch2(&mut self) -> CARRIER_EN_CH2_W<'_>

Bit 28

pub fn mem_size_ch2(&mut self) -> MEM_SIZE_CH2_W<'_>

Bits 24:27

pub fn idle_thres_ch2(&mut self) -> IDLE_THRES_CH2_W<'_>

Bits 8:23

pub fn div_cnt_ch2(&mut self) -> DIV_CNT_CH2_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CH2CONF1>>

pub fn idle_out_en_ch2(&mut self) -> IDLE_OUT_EN_CH2_W<'_>

Bit 19

pub fn idle_out_lv_ch2(&mut self) -> IDLE_OUT_LV_CH2_W<'_>

Bit 18

pub fn ref_always_on_ch2(&mut self) -> REF_ALWAYS_ON_CH2_W<'_>

Bit 17

pub fn ref_cnt_rst_ch2(&mut self) -> REF_CNT_RST_CH2_W<'_>

Bit 16

pub fn rx_filter_thres_ch2(&mut self) -> RX_FILTER_THRES_CH2_W<'_>

Bits 8:15

pub fn rx_filter_en_ch2(&mut self) -> RX_FILTER_EN_CH2_W<'_>

Bit 7

pub fn tx_conti_mode_ch2(&mut self) -> TX_CONTI_MODE_CH2_W<'_>

Bit 6

pub fn mem_owner_ch2(&mut self) -> MEM_OWNER_CH2_W<'_>

Bit 5

pub fn apb_mem_rst_ch2(&mut self) -> APB_MEM_RST_CH2_W<'_>

Bit 4

pub fn mem_rd_rst_ch2(&mut self) -> MEM_RD_RST_CH2_W<'_>

Bit 3

pub fn mem_wr_rst_ch2(&mut self) -> MEM_WR_RST_CH2_W<'_>

Bit 2

pub fn rx_en_ch2(&mut self) -> RX_EN_CH2_W<'_>

Bit 1

pub fn tx_start_ch2(&mut self) -> TX_START_CH2_W<'_>

Bit 0

impl W<u32, Reg<u32, _CH3CONF0>>

pub fn carrier_out_lv_ch3(&mut self) -> CARRIER_OUT_LV_CH3_W<'_>

Bit 29

pub fn carrier_en_ch3(&mut self) -> CARRIER_EN_CH3_W<'_>

Bit 28

pub fn mem_size_ch3(&mut self) -> MEM_SIZE_CH3_W<'_>

Bits 24:27

pub fn idle_thres_ch3(&mut self) -> IDLE_THRES_CH3_W<'_>

Bits 8:23

pub fn div_cnt_ch3(&mut self) -> DIV_CNT_CH3_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CH3CONF1>>

pub fn idle_out_en_ch3(&mut self) -> IDLE_OUT_EN_CH3_W<'_>

Bit 19

pub fn idle_out_lv_ch3(&mut self) -> IDLE_OUT_LV_CH3_W<'_>

Bit 18

pub fn ref_always_on_ch3(&mut self) -> REF_ALWAYS_ON_CH3_W<'_>

Bit 17

pub fn ref_cnt_rst_ch3(&mut self) -> REF_CNT_RST_CH3_W<'_>

Bit 16

pub fn rx_filter_thres_ch3(&mut self) -> RX_FILTER_THRES_CH3_W<'_>

Bits 8:15

pub fn rx_filter_en_ch3(&mut self) -> RX_FILTER_EN_CH3_W<'_>

Bit 7

pub fn tx_conti_mode_ch3(&mut self) -> TX_CONTI_MODE_CH3_W<'_>

Bit 6

pub fn mem_owner_ch3(&mut self) -> MEM_OWNER_CH3_W<'_>

Bit 5

pub fn apb_mem_rst_ch3(&mut self) -> APB_MEM_RST_CH3_W<'_>

Bit 4

pub fn mem_rd_rst_ch3(&mut self) -> MEM_RD_RST_CH3_W<'_>

Bit 3

pub fn mem_wr_rst_ch3(&mut self) -> MEM_WR_RST_CH3_W<'_>

Bit 2

pub fn rx_en_ch3(&mut self) -> RX_EN_CH3_W<'_>

Bit 1

pub fn tx_start_ch3(&mut self) -> TX_START_CH3_W<'_>

Bit 0

impl W<u32, Reg<u32, _CH4CONF0>>

pub fn carrier_out_lv_ch4(&mut self) -> CARRIER_OUT_LV_CH4_W<'_>

Bit 29

pub fn carrier_en_ch4(&mut self) -> CARRIER_EN_CH4_W<'_>

Bit 28

pub fn mem_size_ch4(&mut self) -> MEM_SIZE_CH4_W<'_>

Bits 24:27

pub fn idle_thres_ch4(&mut self) -> IDLE_THRES_CH4_W<'_>

Bits 8:23

pub fn div_cnt_ch4(&mut self) -> DIV_CNT_CH4_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CH4CONF1>>

pub fn idle_out_en_ch4(&mut self) -> IDLE_OUT_EN_CH4_W<'_>

Bit 19

pub fn idle_out_lv_ch4(&mut self) -> IDLE_OUT_LV_CH4_W<'_>

Bit 18

pub fn ref_always_on_ch4(&mut self) -> REF_ALWAYS_ON_CH4_W<'_>

Bit 17

pub fn ref_cnt_rst_ch4(&mut self) -> REF_CNT_RST_CH4_W<'_>

Bit 16

pub fn rx_filter_thres_ch4(&mut self) -> RX_FILTER_THRES_CH4_W<'_>

Bits 8:15

pub fn rx_filter_en_ch4(&mut self) -> RX_FILTER_EN_CH4_W<'_>

Bit 7

pub fn tx_conti_mode_ch4(&mut self) -> TX_CONTI_MODE_CH4_W<'_>

Bit 6

pub fn mem_owner_ch4(&mut self) -> MEM_OWNER_CH4_W<'_>

Bit 5

pub fn apb_mem_rst_ch4(&mut self) -> APB_MEM_RST_CH4_W<'_>

Bit 4

pub fn mem_rd_rst_ch4(&mut self) -> MEM_RD_RST_CH4_W<'_>

Bit 3

pub fn mem_wr_rst_ch4(&mut self) -> MEM_WR_RST_CH4_W<'_>

Bit 2

pub fn rx_en_ch4(&mut self) -> RX_EN_CH4_W<'_>

Bit 1

pub fn tx_start_ch4(&mut self) -> TX_START_CH4_W<'_>

Bit 0

impl W<u32, Reg<u32, _CH5CONF0>>

pub fn carrier_out_lv_ch5(&mut self) -> CARRIER_OUT_LV_CH5_W<'_>

Bit 29

pub fn carrier_en_ch5(&mut self) -> CARRIER_EN_CH5_W<'_>

Bit 28

pub fn mem_size_ch5(&mut self) -> MEM_SIZE_CH5_W<'_>

Bits 24:27

pub fn idle_thres_ch5(&mut self) -> IDLE_THRES_CH5_W<'_>

Bits 8:23

pub fn div_cnt_ch5(&mut self) -> DIV_CNT_CH5_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CH5CONF1>>

pub fn idle_out_en_ch5(&mut self) -> IDLE_OUT_EN_CH5_W<'_>

Bit 19

pub fn idle_out_lv_ch5(&mut self) -> IDLE_OUT_LV_CH5_W<'_>

Bit 18

pub fn ref_always_on_ch5(&mut self) -> REF_ALWAYS_ON_CH5_W<'_>

Bit 17

pub fn ref_cnt_rst_ch5(&mut self) -> REF_CNT_RST_CH5_W<'_>

Bit 16

pub fn rx_filter_thres_ch5(&mut self) -> RX_FILTER_THRES_CH5_W<'_>

Bits 8:15

pub fn rx_filter_en_ch5(&mut self) -> RX_FILTER_EN_CH5_W<'_>

Bit 7

pub fn tx_conti_mode_ch5(&mut self) -> TX_CONTI_MODE_CH5_W<'_>

Bit 6

pub fn mem_owner_ch5(&mut self) -> MEM_OWNER_CH5_W<'_>

Bit 5

pub fn apb_mem_rst_ch5(&mut self) -> APB_MEM_RST_CH5_W<'_>

Bit 4

pub fn mem_rd_rst_ch5(&mut self) -> MEM_RD_RST_CH5_W<'_>

Bit 3

pub fn mem_wr_rst_ch5(&mut self) -> MEM_WR_RST_CH5_W<'_>

Bit 2

pub fn rx_en_ch5(&mut self) -> RX_EN_CH5_W<'_>

Bit 1

pub fn tx_start_ch5(&mut self) -> TX_START_CH5_W<'_>

Bit 0

impl W<u32, Reg<u32, _CH6CONF0>>

pub fn carrier_out_lv_ch6(&mut self) -> CARRIER_OUT_LV_CH6_W<'_>

Bit 29

pub fn carrier_en_ch6(&mut self) -> CARRIER_EN_CH6_W<'_>

Bit 28

pub fn mem_size_ch6(&mut self) -> MEM_SIZE_CH6_W<'_>

Bits 24:27

pub fn idle_thres_ch6(&mut self) -> IDLE_THRES_CH6_W<'_>

Bits 8:23

pub fn div_cnt_ch6(&mut self) -> DIV_CNT_CH6_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CH6CONF1>>

pub fn idle_out_en_ch6(&mut self) -> IDLE_OUT_EN_CH6_W<'_>

Bit 19

pub fn idle_out_lv_ch6(&mut self) -> IDLE_OUT_LV_CH6_W<'_>

Bit 18

pub fn ref_always_on_ch6(&mut self) -> REF_ALWAYS_ON_CH6_W<'_>

Bit 17

pub fn ref_cnt_rst_ch6(&mut self) -> REF_CNT_RST_CH6_W<'_>

Bit 16

pub fn rx_filter_thres_ch6(&mut self) -> RX_FILTER_THRES_CH6_W<'_>

Bits 8:15

pub fn rx_filter_en_ch6(&mut self) -> RX_FILTER_EN_CH6_W<'_>

Bit 7

pub fn tx_conti_mode_ch6(&mut self) -> TX_CONTI_MODE_CH6_W<'_>

Bit 6

pub fn mem_owner_ch6(&mut self) -> MEM_OWNER_CH6_W<'_>

Bit 5

pub fn apb_mem_rst_ch6(&mut self) -> APB_MEM_RST_CH6_W<'_>

Bit 4

pub fn mem_rd_rst_ch6(&mut self) -> MEM_RD_RST_CH6_W<'_>

Bit 3

pub fn mem_wr_rst_ch6(&mut self) -> MEM_WR_RST_CH6_W<'_>

Bit 2

pub fn rx_en_ch6(&mut self) -> RX_EN_CH6_W<'_>

Bit 1

pub fn tx_start_ch6(&mut self) -> TX_START_CH6_W<'_>

Bit 0

impl W<u32, Reg<u32, _CH7CONF0>>

pub fn carrier_out_lv_ch7(&mut self) -> CARRIER_OUT_LV_CH7_W<'_>

Bit 29

pub fn carrier_en_ch7(&mut self) -> CARRIER_EN_CH7_W<'_>

Bit 28

pub fn mem_size_ch7(&mut self) -> MEM_SIZE_CH7_W<'_>

Bits 24:27

pub fn idle_thres_ch7(&mut self) -> IDLE_THRES_CH7_W<'_>

Bits 8:23

pub fn div_cnt_ch7(&mut self) -> DIV_CNT_CH7_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CH7CONF1>>

pub fn idle_out_en_ch7(&mut self) -> IDLE_OUT_EN_CH7_W<'_>

Bit 19

pub fn idle_out_lv_ch7(&mut self) -> IDLE_OUT_LV_CH7_W<'_>

Bit 18

pub fn ref_always_on_ch7(&mut self) -> REF_ALWAYS_ON_CH7_W<'_>

Bit 17

pub fn ref_cnt_rst_ch7(&mut self) -> REF_CNT_RST_CH7_W<'_>

Bit 16

pub fn rx_filter_thres_ch7(&mut self) -> RX_FILTER_THRES_CH7_W<'_>

Bits 8:15

pub fn rx_filter_en_ch7(&mut self) -> RX_FILTER_EN_CH7_W<'_>

Bit 7

pub fn tx_conti_mode_ch7(&mut self) -> TX_CONTI_MODE_CH7_W<'_>

Bit 6

pub fn mem_owner_ch7(&mut self) -> MEM_OWNER_CH7_W<'_>

Bit 5

pub fn apb_mem_rst_ch7(&mut self) -> APB_MEM_RST_CH7_W<'_>

Bit 4

pub fn mem_rd_rst_ch7(&mut self) -> MEM_RD_RST_CH7_W<'_>

Bit 3

pub fn mem_wr_rst_ch7(&mut self) -> MEM_WR_RST_CH7_W<'_>

Bit 2

pub fn rx_en_ch7(&mut self) -> RX_EN_CH7_W<'_>

Bit 1

pub fn tx_start_ch7(&mut self) -> TX_START_CH7_W<'_>

Bit 0

impl W<u32, Reg<u32, _CH0STATUS>>

pub fn status_ch0(&mut self) -> STATUS_CH0_W<'_>

Bits 0:31

pub fn apb_mem_rd_err_ch0(&mut self) -> APB_MEM_RD_ERR_CH0_W<'_>

Bit 31

pub fn apb_mem_wr_err_ch0(&mut self) -> APB_MEM_WR_ERR_CH0_W<'_>

Bit 30

pub fn mem_empty_ch0(&mut self) -> MEM_EMPTY_CH0_W<'_>

Bit 29

pub fn mem_full_ch0(&mut self) -> MEM_FULL_CH0_W<'_>

Bit 28

pub fn mem_owner_err_ch0(&mut self) -> MEM_OWNER_ERR_CH0_W<'_>

Bit 27

pub fn state_ch0(&mut self) -> STATE_CH0_W<'_>

Bits 24:26

pub fn mem_raddr_ex_ch0(&mut self) -> MEM_RADDR_EX_CH0_W<'_>

Bits 12:21

pub fn mem_waddr_ex_ch0(&mut self) -> MEM_WADDR_EX_CH0_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _CH1STATUS>>

pub fn status_ch1(&mut self) -> STATUS_CH1_W<'_>

Bits 0:31

pub fn apb_mem_rd_err_ch1(&mut self) -> APB_MEM_RD_ERR_CH1_W<'_>

Bit 31

pub fn apb_mem_wr_err_ch1(&mut self) -> APB_MEM_WR_ERR_CH1_W<'_>

Bit 30

pub fn mem_empty_ch1(&mut self) -> MEM_EMPTY_CH1_W<'_>

Bit 29

pub fn mem_full_ch1(&mut self) -> MEM_FULL_CH1_W<'_>

Bit 28

pub fn mem_owner_err_ch1(&mut self) -> MEM_OWNER_ERR_CH1_W<'_>

Bit 27

pub fn state_ch1(&mut self) -> STATE_CH1_W<'_>

Bits 24:26

pub fn mem_raddr_ex_ch1(&mut self) -> MEM_RADDR_EX_CH1_W<'_>

Bits 12:21

pub fn mem_waddr_ex_ch1(&mut self) -> MEM_WADDR_EX_CH1_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _CH2STATUS>>

pub fn status_ch2(&mut self) -> STATUS_CH2_W<'_>

Bits 0:31

pub fn apb_mem_rd_err_ch2(&mut self) -> APB_MEM_RD_ERR_CH2_W<'_>

Bit 31

pub fn apb_mem_wr_err_ch2(&mut self) -> APB_MEM_WR_ERR_CH2_W<'_>

Bit 30

pub fn mem_empty_ch2(&mut self) -> MEM_EMPTY_CH2_W<'_>

Bit 29

pub fn mem_full_ch2(&mut self) -> MEM_FULL_CH2_W<'_>

Bit 28

pub fn mem_owner_err_ch2(&mut self) -> MEM_OWNER_ERR_CH2_W<'_>

Bit 27

pub fn state_ch2(&mut self) -> STATE_CH2_W<'_>

Bits 24:26

pub fn mem_raddr_ex_ch2(&mut self) -> MEM_RADDR_EX_CH2_W<'_>

Bits 12:21

pub fn mem_waddr_ex_ch2(&mut self) -> MEM_WADDR_EX_CH2_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _CH3STATUS>>

pub fn status_ch3(&mut self) -> STATUS_CH3_W<'_>

Bits 0:31

pub fn apb_mem_rd_err_ch3(&mut self) -> APB_MEM_RD_ERR_CH3_W<'_>

Bit 31

pub fn apb_mem_wr_err_ch3(&mut self) -> APB_MEM_WR_ERR_CH3_W<'_>

Bit 30

pub fn mem_empty_ch3(&mut self) -> MEM_EMPTY_CH3_W<'_>

Bit 29

pub fn mem_full_ch3(&mut self) -> MEM_FULL_CH3_W<'_>

Bit 28

pub fn mem_owner_err_ch3(&mut self) -> MEM_OWNER_ERR_CH3_W<'_>

Bit 27

pub fn state_ch3(&mut self) -> STATE_CH3_W<'_>

Bits 24:26

pub fn mem_raddr_ex_ch3(&mut self) -> MEM_RADDR_EX_CH3_W<'_>

Bits 12:21

pub fn mem_waddr_ex_ch3(&mut self) -> MEM_WADDR_EX_CH3_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _CH4STATUS>>

pub fn status_ch4(&mut self) -> STATUS_CH4_W<'_>

Bits 0:31

pub fn apb_mem_rd_err_ch4(&mut self) -> APB_MEM_RD_ERR_CH4_W<'_>

Bit 31

pub fn apb_mem_wr_err_ch4(&mut self) -> APB_MEM_WR_ERR_CH4_W<'_>

Bit 30

pub fn mem_empty_ch4(&mut self) -> MEM_EMPTY_CH4_W<'_>

Bit 29

pub fn mem_full_ch4(&mut self) -> MEM_FULL_CH4_W<'_>

Bit 28

pub fn mem_owner_err_ch4(&mut self) -> MEM_OWNER_ERR_CH4_W<'_>

Bit 27

pub fn state_ch4(&mut self) -> STATE_CH4_W<'_>

Bits 24:26

pub fn mem_raddr_ex_ch4(&mut self) -> MEM_RADDR_EX_CH4_W<'_>

Bits 12:21

pub fn mem_waddr_ex_ch4(&mut self) -> MEM_WADDR_EX_CH4_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _CH5STATUS>>

pub fn status_ch5(&mut self) -> STATUS_CH5_W<'_>

Bits 0:31

pub fn apb_mem_rd_err_ch5(&mut self) -> APB_MEM_RD_ERR_CH5_W<'_>

Bit 31

pub fn apb_mem_wr_err_ch5(&mut self) -> APB_MEM_WR_ERR_CH5_W<'_>

Bit 30

pub fn mem_empty_ch5(&mut self) -> MEM_EMPTY_CH5_W<'_>

Bit 29

pub fn mem_full_ch5(&mut self) -> MEM_FULL_CH5_W<'_>

Bit 28

pub fn mem_owner_err_ch5(&mut self) -> MEM_OWNER_ERR_CH5_W<'_>

Bit 27

pub fn state_ch5(&mut self) -> STATE_CH5_W<'_>

Bits 24:26

pub fn mem_raddr_ex_ch5(&mut self) -> MEM_RADDR_EX_CH5_W<'_>

Bits 12:21

pub fn mem_waddr_ex_ch5(&mut self) -> MEM_WADDR_EX_CH5_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _CH6STATUS>>

pub fn status_ch6(&mut self) -> STATUS_CH6_W<'_>

Bits 0:31

pub fn apb_mem_rd_err_ch6(&mut self) -> APB_MEM_RD_ERR_CH6_W<'_>

Bit 31

pub fn apb_mem_wr_err_ch6(&mut self) -> APB_MEM_WR_ERR_CH6_W<'_>

Bit 30

pub fn mem_empty_ch6(&mut self) -> MEM_EMPTY_CH6_W<'_>

Bit 29

pub fn mem_full_ch6(&mut self) -> MEM_FULL_CH6_W<'_>

Bit 28

pub fn mem_owner_err_ch6(&mut self) -> MEM_OWNER_ERR_CH6_W<'_>

Bit 27

pub fn state_ch6(&mut self) -> STATE_CH6_W<'_>

Bits 24:26

pub fn mem_raddr_ex_ch6(&mut self) -> MEM_RADDR_EX_CH6_W<'_>

Bits 12:21

pub fn mem_waddr_ex_ch6(&mut self) -> MEM_WADDR_EX_CH6_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _CH7STATUS>>

pub fn status_ch7(&mut self) -> STATUS_CH7_W<'_>

Bits 0:31

pub fn apb_mem_rd_err_ch7(&mut self) -> APB_MEM_RD_ERR_CH7_W<'_>

Bit 31

pub fn apb_mem_wr_err_ch7(&mut self) -> APB_MEM_WR_ERR_CH7_W<'_>

Bit 30

pub fn mem_empty_ch7(&mut self) -> MEM_EMPTY_CH7_W<'_>

Bit 29

pub fn mem_full_ch7(&mut self) -> MEM_FULL_CH7_W<'_>

Bit 28

pub fn mem_owner_err_ch7(&mut self) -> MEM_OWNER_ERR_CH7_W<'_>

Bit 27

pub fn state_ch7(&mut self) -> STATE_CH7_W<'_>

Bits 24:26

pub fn mem_raddr_ex_ch7(&mut self) -> MEM_RADDR_EX_CH7_W<'_>

Bits 12:21

pub fn mem_waddr_ex_ch7(&mut self) -> MEM_WADDR_EX_CH7_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _CH0ADDR>>

pub fn apb_mem_addr_ch0(&mut self) -> APB_MEM_ADDR_CH0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CH1ADDR>>

pub fn apb_mem_addr_ch1(&mut self) -> APB_MEM_ADDR_CH1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CH2ADDR>>

pub fn apb_mem_addr_ch2(&mut self) -> APB_MEM_ADDR_CH2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CH3ADDR>>

pub fn apb_mem_addr_ch3(&mut self) -> APB_MEM_ADDR_CH3_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CH4ADDR>>

pub fn apb_mem_addr_ch4(&mut self) -> APB_MEM_ADDR_CH4_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CH5ADDR>>

pub fn apb_mem_addr_ch5(&mut self) -> APB_MEM_ADDR_CH5_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CH6ADDR>>

pub fn apb_mem_addr_ch6(&mut self) -> APB_MEM_ADDR_CH6_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CH7ADDR>>

pub fn apb_mem_addr_ch7(&mut self) -> APB_MEM_ADDR_CH7_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _INT_RAW>>

pub fn ch7_tx_thr_event_int_raw(&mut self) -> CH7_TX_THR_EVENT_INT_RAW_W<'_>

Bit 31

pub fn ch6_tx_thr_event_int_raw(&mut self) -> CH6_TX_THR_EVENT_INT_RAW_W<'_>

Bit 30

pub fn ch5_tx_thr_event_int_raw(&mut self) -> CH5_TX_THR_EVENT_INT_RAW_W<'_>

Bit 29

pub fn ch4_tx_thr_event_int_raw(&mut self) -> CH4_TX_THR_EVENT_INT_RAW_W<'_>

Bit 28

pub fn ch3_tx_thr_event_int_raw(&mut self) -> CH3_TX_THR_EVENT_INT_RAW_W<'_>

Bit 27

pub fn ch2_tx_thr_event_int_raw(&mut self) -> CH2_TX_THR_EVENT_INT_RAW_W<'_>

Bit 26

pub fn ch1_tx_thr_event_int_raw(&mut self) -> CH1_TX_THR_EVENT_INT_RAW_W<'_>

Bit 25

pub fn ch0_tx_thr_event_int_raw(&mut self) -> CH0_TX_THR_EVENT_INT_RAW_W<'_>

Bit 24

pub fn ch7_err_int_raw(&mut self) -> CH7_ERR_INT_RAW_W<'_>

Bit 23

pub fn ch7_rx_end_int_raw(&mut self) -> CH7_RX_END_INT_RAW_W<'_>

Bit 22

pub fn ch7_tx_end_int_raw(&mut self) -> CH7_TX_END_INT_RAW_W<'_>

Bit 21

pub fn ch6_err_int_raw(&mut self) -> CH6_ERR_INT_RAW_W<'_>

Bit 20

pub fn ch6_rx_end_int_raw(&mut self) -> CH6_RX_END_INT_RAW_W<'_>

Bit 19

pub fn ch6_tx_end_int_raw(&mut self) -> CH6_TX_END_INT_RAW_W<'_>

Bit 18

pub fn ch5_err_int_raw(&mut self) -> CH5_ERR_INT_RAW_W<'_>

Bit 17

pub fn ch5_rx_end_int_raw(&mut self) -> CH5_RX_END_INT_RAW_W<'_>

Bit 16

pub fn ch5_tx_end_int_raw(&mut self) -> CH5_TX_END_INT_RAW_W<'_>

Bit 15

pub fn ch4_err_int_raw(&mut self) -> CH4_ERR_INT_RAW_W<'_>

Bit 14

pub fn ch4_rx_end_int_raw(&mut self) -> CH4_RX_END_INT_RAW_W<'_>

Bit 13

pub fn ch4_tx_end_int_raw(&mut self) -> CH4_TX_END_INT_RAW_W<'_>

Bit 12

pub fn ch3_err_int_raw(&mut self) -> CH3_ERR_INT_RAW_W<'_>

Bit 11

pub fn ch3_rx_end_int_raw(&mut self) -> CH3_RX_END_INT_RAW_W<'_>

Bit 10

pub fn ch3_tx_end_int_raw(&mut self) -> CH3_TX_END_INT_RAW_W<'_>

Bit 9

pub fn ch2_err_int_raw(&mut self) -> CH2_ERR_INT_RAW_W<'_>

Bit 8

pub fn ch2_rx_end_int_raw(&mut self) -> CH2_RX_END_INT_RAW_W<'_>

Bit 7

pub fn ch2_tx_end_int_raw(&mut self) -> CH2_TX_END_INT_RAW_W<'_>

Bit 6

pub fn ch1_err_int_raw(&mut self) -> CH1_ERR_INT_RAW_W<'_>

Bit 5

pub fn ch1_rx_end_int_raw(&mut self) -> CH1_RX_END_INT_RAW_W<'_>

Bit 4

pub fn ch1_tx_end_int_raw(&mut self) -> CH1_TX_END_INT_RAW_W<'_>

Bit 3

pub fn ch0_err_int_raw(&mut self) -> CH0_ERR_INT_RAW_W<'_>

Bit 2

pub fn ch0_rx_end_int_raw(&mut self) -> CH0_RX_END_INT_RAW_W<'_>

Bit 1

pub fn ch0_tx_end_int_raw(&mut self) -> CH0_TX_END_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ST>>

pub fn ch7_tx_thr_event_int_st(&mut self) -> CH7_TX_THR_EVENT_INT_ST_W<'_>

Bit 31

pub fn ch6_tx_thr_event_int_st(&mut self) -> CH6_TX_THR_EVENT_INT_ST_W<'_>

Bit 30

pub fn ch5_tx_thr_event_int_st(&mut self) -> CH5_TX_THR_EVENT_INT_ST_W<'_>

Bit 29

pub fn ch4_tx_thr_event_int_st(&mut self) -> CH4_TX_THR_EVENT_INT_ST_W<'_>

Bit 28

pub fn ch3_tx_thr_event_int_st(&mut self) -> CH3_TX_THR_EVENT_INT_ST_W<'_>

Bit 27

pub fn ch2_tx_thr_event_int_st(&mut self) -> CH2_TX_THR_EVENT_INT_ST_W<'_>

Bit 26

pub fn ch1_tx_thr_event_int_st(&mut self) -> CH1_TX_THR_EVENT_INT_ST_W<'_>

Bit 25

pub fn ch0_tx_thr_event_int_st(&mut self) -> CH0_TX_THR_EVENT_INT_ST_W<'_>

Bit 24

pub fn ch7_err_int_st(&mut self) -> CH7_ERR_INT_ST_W<'_>

Bit 23

pub fn ch7_rx_end_int_st(&mut self) -> CH7_RX_END_INT_ST_W<'_>

Bit 22

pub fn ch7_tx_end_int_st(&mut self) -> CH7_TX_END_INT_ST_W<'_>

Bit 21

pub fn ch6_err_int_st(&mut self) -> CH6_ERR_INT_ST_W<'_>

Bit 20

pub fn ch6_rx_end_int_st(&mut self) -> CH6_RX_END_INT_ST_W<'_>

Bit 19

pub fn ch6_tx_end_int_st(&mut self) -> CH6_TX_END_INT_ST_W<'_>

Bit 18

pub fn ch5_err_int_st(&mut self) -> CH5_ERR_INT_ST_W<'_>

Bit 17

pub fn ch5_rx_end_int_st(&mut self) -> CH5_RX_END_INT_ST_W<'_>

Bit 16

pub fn ch5_tx_end_int_st(&mut self) -> CH5_TX_END_INT_ST_W<'_>

Bit 15

pub fn ch4_err_int_st(&mut self) -> CH4_ERR_INT_ST_W<'_>

Bit 14

pub fn ch4_rx_end_int_st(&mut self) -> CH4_RX_END_INT_ST_W<'_>

Bit 13

pub fn ch4_tx_end_int_st(&mut self) -> CH4_TX_END_INT_ST_W<'_>

Bit 12

pub fn ch3_err_int_st(&mut self) -> CH3_ERR_INT_ST_W<'_>

Bit 11

pub fn ch3_rx_end_int_st(&mut self) -> CH3_RX_END_INT_ST_W<'_>

Bit 10

pub fn ch3_tx_end_int_st(&mut self) -> CH3_TX_END_INT_ST_W<'_>

Bit 9

pub fn ch2_err_int_st(&mut self) -> CH2_ERR_INT_ST_W<'_>

Bit 8

pub fn ch2_rx_end_int_st(&mut self) -> CH2_RX_END_INT_ST_W<'_>

Bit 7

pub fn ch2_tx_end_int_st(&mut self) -> CH2_TX_END_INT_ST_W<'_>

Bit 6

pub fn ch1_err_int_st(&mut self) -> CH1_ERR_INT_ST_W<'_>

Bit 5

pub fn ch1_rx_end_int_st(&mut self) -> CH1_RX_END_INT_ST_W<'_>

Bit 4

pub fn ch1_tx_end_int_st(&mut self) -> CH1_TX_END_INT_ST_W<'_>

Bit 3

pub fn ch0_err_int_st(&mut self) -> CH0_ERR_INT_ST_W<'_>

Bit 2

pub fn ch0_rx_end_int_st(&mut self) -> CH0_RX_END_INT_ST_W<'_>

Bit 1

pub fn ch0_tx_end_int_st(&mut self) -> CH0_TX_END_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ENA>>

pub fn ch7_tx_thr_event_int_ena(&mut self) -> CH7_TX_THR_EVENT_INT_ENA_W<'_>

Bit 31

pub fn ch6_tx_thr_event_int_ena(&mut self) -> CH6_TX_THR_EVENT_INT_ENA_W<'_>

Bit 30

pub fn ch5_tx_thr_event_int_ena(&mut self) -> CH5_TX_THR_EVENT_INT_ENA_W<'_>

Bit 29

pub fn ch4_tx_thr_event_int_ena(&mut self) -> CH4_TX_THR_EVENT_INT_ENA_W<'_>

Bit 28

pub fn ch3_tx_thr_event_int_ena(&mut self) -> CH3_TX_THR_EVENT_INT_ENA_W<'_>

Bit 27

pub fn ch2_tx_thr_event_int_ena(&mut self) -> CH2_TX_THR_EVENT_INT_ENA_W<'_>

Bit 26

pub fn ch1_tx_thr_event_int_ena(&mut self) -> CH1_TX_THR_EVENT_INT_ENA_W<'_>

Bit 25

pub fn ch0_tx_thr_event_int_ena(&mut self) -> CH0_TX_THR_EVENT_INT_ENA_W<'_>

Bit 24

pub fn ch7_err_int_ena(&mut self) -> CH7_ERR_INT_ENA_W<'_>

Bit 23

pub fn ch7_rx_end_int_ena(&mut self) -> CH7_RX_END_INT_ENA_W<'_>

Bit 22

pub fn ch7_tx_end_int_ena(&mut self) -> CH7_TX_END_INT_ENA_W<'_>

Bit 21

pub fn ch6_err_int_ena(&mut self) -> CH6_ERR_INT_ENA_W<'_>

Bit 20

pub fn ch6_rx_end_int_ena(&mut self) -> CH6_RX_END_INT_ENA_W<'_>

Bit 19

pub fn ch6_tx_end_int_ena(&mut self) -> CH6_TX_END_INT_ENA_W<'_>

Bit 18

pub fn ch5_err_int_ena(&mut self) -> CH5_ERR_INT_ENA_W<'_>

Bit 17

pub fn ch5_rx_end_int_ena(&mut self) -> CH5_RX_END_INT_ENA_W<'_>

Bit 16

pub fn ch5_tx_end_int_ena(&mut self) -> CH5_TX_END_INT_ENA_W<'_>

Bit 15

pub fn ch4_err_int_ena(&mut self) -> CH4_ERR_INT_ENA_W<'_>

Bit 14

pub fn ch4_rx_end_int_ena(&mut self) -> CH4_RX_END_INT_ENA_W<'_>

Bit 13

pub fn ch4_tx_end_int_ena(&mut self) -> CH4_TX_END_INT_ENA_W<'_>

Bit 12

pub fn ch3_err_int_ena(&mut self) -> CH3_ERR_INT_ENA_W<'_>

Bit 11

pub fn ch3_rx_end_int_ena(&mut self) -> CH3_RX_END_INT_ENA_W<'_>

Bit 10

pub fn ch3_tx_end_int_ena(&mut self) -> CH3_TX_END_INT_ENA_W<'_>

Bit 9

pub fn ch2_err_int_ena(&mut self) -> CH2_ERR_INT_ENA_W<'_>

Bit 8

pub fn ch2_rx_end_int_ena(&mut self) -> CH2_RX_END_INT_ENA_W<'_>

Bit 7

pub fn ch2_tx_end_int_ena(&mut self) -> CH2_TX_END_INT_ENA_W<'_>

Bit 6

pub fn ch1_err_int_ena(&mut self) -> CH1_ERR_INT_ENA_W<'_>

Bit 5

pub fn ch1_rx_end_int_ena(&mut self) -> CH1_RX_END_INT_ENA_W<'_>

Bit 4

pub fn ch1_tx_end_int_ena(&mut self) -> CH1_TX_END_INT_ENA_W<'_>

Bit 3

pub fn ch0_err_int_ena(&mut self) -> CH0_ERR_INT_ENA_W<'_>

Bit 2

pub fn ch0_rx_end_int_ena(&mut self) -> CH0_RX_END_INT_ENA_W<'_>

Bit 1

pub fn ch0_tx_end_int_ena(&mut self) -> CH0_TX_END_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_CLR>>

pub fn ch7_tx_thr_event_int_clr(&mut self) -> CH7_TX_THR_EVENT_INT_CLR_W<'_>

Bit 31

pub fn ch6_tx_thr_event_int_clr(&mut self) -> CH6_TX_THR_EVENT_INT_CLR_W<'_>

Bit 30

pub fn ch5_tx_thr_event_int_clr(&mut self) -> CH5_TX_THR_EVENT_INT_CLR_W<'_>

Bit 29

pub fn ch4_tx_thr_event_int_clr(&mut self) -> CH4_TX_THR_EVENT_INT_CLR_W<'_>

Bit 28

pub fn ch3_tx_thr_event_int_clr(&mut self) -> CH3_TX_THR_EVENT_INT_CLR_W<'_>

Bit 27

pub fn ch2_tx_thr_event_int_clr(&mut self) -> CH2_TX_THR_EVENT_INT_CLR_W<'_>

Bit 26

pub fn ch1_tx_thr_event_int_clr(&mut self) -> CH1_TX_THR_EVENT_INT_CLR_W<'_>

Bit 25

pub fn ch0_tx_thr_event_int_clr(&mut self) -> CH0_TX_THR_EVENT_INT_CLR_W<'_>

Bit 24

pub fn ch7_err_int_clr(&mut self) -> CH7_ERR_INT_CLR_W<'_>

Bit 23

pub fn ch7_rx_end_int_clr(&mut self) -> CH7_RX_END_INT_CLR_W<'_>

Bit 22

pub fn ch7_tx_end_int_clr(&mut self) -> CH7_TX_END_INT_CLR_W<'_>

Bit 21

pub fn ch6_err_int_clr(&mut self) -> CH6_ERR_INT_CLR_W<'_>

Bit 20

pub fn ch6_rx_end_int_clr(&mut self) -> CH6_RX_END_INT_CLR_W<'_>

Bit 19

pub fn ch6_tx_end_int_clr(&mut self) -> CH6_TX_END_INT_CLR_W<'_>

Bit 18

pub fn ch5_err_int_clr(&mut self) -> CH5_ERR_INT_CLR_W<'_>

Bit 17

pub fn ch5_rx_end_int_clr(&mut self) -> CH5_RX_END_INT_CLR_W<'_>

Bit 16

pub fn ch5_tx_end_int_clr(&mut self) -> CH5_TX_END_INT_CLR_W<'_>

Bit 15

pub fn ch4_err_int_clr(&mut self) -> CH4_ERR_INT_CLR_W<'_>

Bit 14

pub fn ch4_rx_end_int_clr(&mut self) -> CH4_RX_END_INT_CLR_W<'_>

Bit 13

pub fn ch4_tx_end_int_clr(&mut self) -> CH4_TX_END_INT_CLR_W<'_>

Bit 12

pub fn ch3_err_int_clr(&mut self) -> CH3_ERR_INT_CLR_W<'_>

Bit 11

pub fn ch3_rx_end_int_clr(&mut self) -> CH3_RX_END_INT_CLR_W<'_>

Bit 10

pub fn ch3_tx_end_int_clr(&mut self) -> CH3_TX_END_INT_CLR_W<'_>

Bit 9

pub fn ch2_err_int_clr(&mut self) -> CH2_ERR_INT_CLR_W<'_>

Bit 8

pub fn ch2_rx_end_int_clr(&mut self) -> CH2_RX_END_INT_CLR_W<'_>

Bit 7

pub fn ch2_tx_end_int_clr(&mut self) -> CH2_TX_END_INT_CLR_W<'_>

Bit 6

pub fn ch1_err_int_clr(&mut self) -> CH1_ERR_INT_CLR_W<'_>

Bit 5

pub fn ch1_rx_end_int_clr(&mut self) -> CH1_RX_END_INT_CLR_W<'_>

Bit 4

pub fn ch1_tx_end_int_clr(&mut self) -> CH1_TX_END_INT_CLR_W<'_>

Bit 3

pub fn ch0_err_int_clr(&mut self) -> CH0_ERR_INT_CLR_W<'_>

Bit 2

pub fn ch0_rx_end_int_clr(&mut self) -> CH0_RX_END_INT_CLR_W<'_>

Bit 1

pub fn ch0_tx_end_int_clr(&mut self) -> CH0_TX_END_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, _CH0CARRIER_DUTY>>

pub fn carrier_high_ch0(&mut self) -> CARRIER_HIGH_CH0_W<'_>

Bits 16:31

pub fn carrier_low_ch0(&mut self) -> CARRIER_LOW_CH0_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH1CARRIER_DUTY>>

pub fn carrier_high_ch1(&mut self) -> CARRIER_HIGH_CH1_W<'_>

Bits 16:31

pub fn carrier_low_ch1(&mut self) -> CARRIER_LOW_CH1_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH2CARRIER_DUTY>>

pub fn carrier_high_ch2(&mut self) -> CARRIER_HIGH_CH2_W<'_>

Bits 16:31

pub fn carrier_low_ch2(&mut self) -> CARRIER_LOW_CH2_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH3CARRIER_DUTY>>

pub fn carrier_high_ch3(&mut self) -> CARRIER_HIGH_CH3_W<'_>

Bits 16:31

pub fn carrier_low_ch3(&mut self) -> CARRIER_LOW_CH3_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH4CARRIER_DUTY>>

pub fn carrier_high_ch4(&mut self) -> CARRIER_HIGH_CH4_W<'_>

Bits 16:31

pub fn carrier_low_ch4(&mut self) -> CARRIER_LOW_CH4_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH5CARRIER_DUTY>>

pub fn carrier_high_ch5(&mut self) -> CARRIER_HIGH_CH5_W<'_>

Bits 16:31

pub fn carrier_low_ch5(&mut self) -> CARRIER_LOW_CH5_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH6CARRIER_DUTY>>

pub fn carrier_high_ch6(&mut self) -> CARRIER_HIGH_CH6_W<'_>

Bits 16:31

pub fn carrier_low_ch6(&mut self) -> CARRIER_LOW_CH6_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH7CARRIER_DUTY>>

pub fn carrier_high_ch7(&mut self) -> CARRIER_HIGH_CH7_W<'_>

Bits 16:31

pub fn carrier_low_ch7(&mut self) -> CARRIER_LOW_CH7_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CH0_TX_LIM>>

pub fn tx_lim_ch0(&mut self) -> TX_LIM_CH0_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _CH1_TX_LIM>>

pub fn tx_lim_ch1(&mut self) -> TX_LIM_CH1_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _CH2_TX_LIM>>

pub fn tx_lim_ch2(&mut self) -> TX_LIM_CH2_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _CH3_TX_LIM>>

pub fn tx_lim_ch3(&mut self) -> TX_LIM_CH3_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _CH4_TX_LIM>>

pub fn tx_lim_ch4(&mut self) -> TX_LIM_CH4_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _CH5_TX_LIM>>

pub fn tx_lim_ch5(&mut self) -> TX_LIM_CH5_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _CH6_TX_LIM>>

pub fn tx_lim_ch6(&mut self) -> TX_LIM_CH6_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _CH7_TX_LIM>>

pub fn tx_lim_ch7(&mut self) -> TX_LIM_CH7_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _APB_CONF>>

pub fn mem_tx_wrap_en(&mut self) -> MEM_TX_WRAP_EN_W<'_>

Bit 1

pub fn apb_fifo_mask(&mut self) -> APB_FIFO_MASK_W<'_>

Bit 0

impl W<u32, Reg<u32, _DATE>>

pub fn date(&mut self) -> DATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BT_SELECT>>

pub fn bt_sel(&mut self) -> BT_SEL_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _OUT>>

pub fn out_data(&mut self) -> OUT_DATA_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _OUT_W1TS>>

pub fn out_data_w1ts(&mut self) -> OUT_DATA_W1TS_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _OUT_W1TC>>

pub fn out_data_w1tc(&mut self) -> OUT_DATA_W1TC_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _OUT1>>

pub fn out1_data(&mut self) -> OUT1_DATA_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _OUT1_W1TS>>

pub fn out1_data_w1ts(&mut self) -> OUT1_DATA_W1TS_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _OUT1_W1TC>>

pub fn out1_data_w1tc(&mut self) -> OUT1_DATA_W1TC_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SDIO_SELECT>>

pub fn sdio_sel(&mut self) -> SDIO_SEL_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable_data(&mut self) -> ENABLE_DATA_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _ENABLE_W1TS>>

pub fn enable_data_w1ts(&mut self) -> ENABLE_DATA_W1TS_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _ENABLE_W1TC>>

pub fn enable_data_w1tc(&mut self) -> ENABLE_DATA_W1TC_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _ENABLE1>>

pub fn enable1_data(&mut self) -> ENABLE1_DATA_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _ENABLE1_W1TS>>

pub fn enable1_data_w1ts(&mut self) -> ENABLE1_DATA_W1TS_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _ENABLE1_W1TC>>

pub fn enable1_data_w1tc(&mut self) -> ENABLE1_DATA_W1TC_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _STRAP>>

pub fn strapping(&mut self) -> STRAPPING_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _IN>>

pub fn in_data(&mut self) -> IN_DATA_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _IN1>>

pub fn in1_data(&mut self) -> IN1_DATA_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _STATUS>>

pub fn status_int(&mut self) -> STATUS_INT_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _STATUS_W1TS>>

pub fn status_int_w1ts(&mut self) -> STATUS_INT_W1TS_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _STATUS_W1TC>>

pub fn status_int_w1tc(&mut self) -> STATUS_INT_W1TC_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _STATUS1>>

pub fn status1_int(&mut self) -> STATUS1_INT_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _STATUS1_W1TS>>

pub fn status1_int_w1ts(&mut self) -> STATUS1_INT_W1TS_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _STATUS1_W1TC>>

pub fn status1_int_w1tc(&mut self) -> STATUS1_INT_W1TC_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _ACPU_INT>>

pub fn appcpu_int(&mut self) -> APPCPU_INT_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _ACPU_NMI_INT>>

pub fn appcpu_nmi_int(&mut self) -> APPCPU_NMI_INT_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _PCPU_INT>>

pub fn procpu_int(&mut self) -> PROCPU_INT_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _PCPU_NMI_INT>>

pub fn procpu_nmi_int(&mut self) -> PROCPU_NMI_INT_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CPUSDIO_INT>>

pub fn sdio_int(&mut self) -> SDIO_INT_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _ACPU_INT1>>

pub fn appcpu_int_h(&mut self) -> APPCPU_INT_H_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _ACPU_NMI_INT1>>

pub fn appcpu_nmi_int_h(&mut self) -> APPCPU_NMI_INT_H_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _PCPU_INT1>>

pub fn procpu_int_h(&mut self) -> PROCPU_INT_H_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _PCPU_NMI_INT1>>

pub fn procpu_nmi_int_h(&mut self) -> PROCPU_NMI_INT_H_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CPUSDIO_INT1>>

pub fn sdio_int_h(&mut self) -> SDIO_INT_H_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _PIN>>

pub fn int_ena(&mut self) -> INT_ENA_W<'_>

Bits 13:17

pub fn config(&mut self) -> CONFIG_W<'_>

Bits 11:12

pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_>

Bit 10

pub fn int_type(&mut self) -> INT_TYPE_W<'_>

Bits 7:9

pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_>

Bit 2

impl W<u32, Reg<u32, _CALI_CONF>>

pub fn cali_start(&mut self) -> CALI_START_W<'_>

Bit 31

pub fn cali_rtc_max(&mut self) -> CALI_RTC_MAX_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _CALI_DATA>>

pub fn cali_rdy_sync2(&mut self) -> CALI_RDY_SYNC2_W<'_>

Bit 31

pub fn cali_rdy_real(&mut self) -> CALI_RDY_REAL_W<'_>

Bit 30

pub fn cali_value_sync2(&mut self) -> CALI_VALUE_SYNC2_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _FUNC_IN_SEL_CFG>>

pub fn sel(&mut self) -> SEL_W<'_>

Bit 7

pub fn in_inv_sel(&mut self) -> IN_INV_SEL_W<'_>

Bit 6

pub fn in_sel(&mut self) -> IN_SEL_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _FUNC_OUT_SEL_CFG>>

pub fn oen_inv_sel(&mut self) -> OEN_INV_SEL_W<'_>

Bit 11

pub fn oen_sel(&mut self) -> OEN_SEL_W<'_>

Bit 10

pub fn out_inv_sel(&mut self) -> OUT_INV_SEL_W<'_>

Bit 9

pub fn out_sel(&mut self) -> OUT_SEL_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _CONF0>>

pub fn uart_rx_brk_eof_en(&mut self) -> UART_RX_BRK_EOF_EN_W<'_>

Bit 23

pub fn clk_en(&mut self) -> CLK_EN_W<'_>

Bit 22

pub fn encode_crc_en(&mut self) -> ENCODE_CRC_EN_W<'_>

Bit 21

pub fn len_eof_en(&mut self) -> LEN_EOF_EN_W<'_>

Bit 20

pub fn uart_idle_eof_en(&mut self) -> UART_IDLE_EOF_EN_W<'_>

Bit 19

pub fn crc_rec_en(&mut self) -> CRC_REC_EN_W<'_>

Bit 18

pub fn head_en(&mut self) -> HEAD_EN_W<'_>

Bit 17

pub fn seper_en(&mut self) -> SEPER_EN_W<'_>

Bit 16

pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<'_>

Bit 15

pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<'_>

Bit 14

pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<'_>

Bit 13

pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<'_>

Bit 12

pub fn uart2_ce(&mut self) -> UART2_CE_W<'_>

Bit 11

pub fn uart1_ce(&mut self) -> UART1_CE_W<'_>

Bit 10

pub fn uart0_ce(&mut self) -> UART0_CE_W<'_>

Bit 9

pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<'_>

Bit 8

pub fn out_no_restart_clr(&mut self) -> OUT_NO_RESTART_CLR_W<'_>

Bit 7

pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<'_>

Bit 6

pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<'_>

Bit 5

pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<'_>

Bit 4

pub fn ahbm_rst(&mut self) -> AHBM_RST_W<'_>

Bit 3

pub fn ahbm_fifo_rst(&mut self) -> AHBM_FIFO_RST_W<'_>

Bit 2

pub fn out_rst(&mut self) -> OUT_RST_W<'_>

Bit 1

pub fn in_rst(&mut self) -> IN_RST_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_RAW>>

pub fn dma_infifo_full_wm_int_raw(&mut self) -> DMA_INFIFO_FULL_WM_INT_RAW_W<'_>

Bit 16

pub fn send_a_q_int_raw(&mut self) -> SEND_A_Q_INT_RAW_W<'_>

Bit 15

pub fn send_s_q_int_raw(&mut self) -> SEND_S_Q_INT_RAW_W<'_>

Bit 14

pub fn out_total_eof_int_raw(&mut self) -> OUT_TOTAL_EOF_INT_RAW_W<'_>

Bit 13

pub fn outlink_eof_err_int_raw(&mut self) -> OUTLINK_EOF_ERR_INT_RAW_W<'_>

Bit 12

pub fn in_dscr_empty_int_raw(&mut self) -> IN_DSCR_EMPTY_INT_RAW_W<'_>

Bit 11

pub fn out_dscr_err_int_raw(&mut self) -> OUT_DSCR_ERR_INT_RAW_W<'_>

Bit 10

pub fn in_dscr_err_int_raw(&mut self) -> IN_DSCR_ERR_INT_RAW_W<'_>

Bit 9

pub fn out_eof_int_raw(&mut self) -> OUT_EOF_INT_RAW_W<'_>

Bit 8

pub fn out_done_int_raw(&mut self) -> OUT_DONE_INT_RAW_W<'_>

Bit 7

pub fn in_err_eof_int_raw(&mut self) -> IN_ERR_EOF_INT_RAW_W<'_>

Bit 6

pub fn in_suc_eof_int_raw(&mut self) -> IN_SUC_EOF_INT_RAW_W<'_>

Bit 5

pub fn in_done_int_raw(&mut self) -> IN_DONE_INT_RAW_W<'_>

Bit 4

pub fn tx_hung_int_raw(&mut self) -> TX_HUNG_INT_RAW_W<'_>

Bit 3

pub fn rx_hung_int_raw(&mut self) -> RX_HUNG_INT_RAW_W<'_>

Bit 2

pub fn tx_start_int_raw(&mut self) -> TX_START_INT_RAW_W<'_>

Bit 1

pub fn rx_start_int_raw(&mut self) -> RX_START_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ST>>

pub fn dma_infifo_full_wm_int_st(&mut self) -> DMA_INFIFO_FULL_WM_INT_ST_W<'_>

Bit 16

pub fn send_a_q_int_st(&mut self) -> SEND_A_Q_INT_ST_W<'_>

Bit 15

pub fn send_s_q_int_st(&mut self) -> SEND_S_Q_INT_ST_W<'_>

Bit 14

pub fn out_total_eof_int_st(&mut self) -> OUT_TOTAL_EOF_INT_ST_W<'_>

Bit 13

pub fn outlink_eof_err_int_st(&mut self) -> OUTLINK_EOF_ERR_INT_ST_W<'_>

Bit 12

pub fn in_dscr_empty_int_st(&mut self) -> IN_DSCR_EMPTY_INT_ST_W<'_>

Bit 11

pub fn out_dscr_err_int_st(&mut self) -> OUT_DSCR_ERR_INT_ST_W<'_>

Bit 10

pub fn in_dscr_err_int_st(&mut self) -> IN_DSCR_ERR_INT_ST_W<'_>

Bit 9

pub fn out_eof_int_st(&mut self) -> OUT_EOF_INT_ST_W<'_>

Bit 8

pub fn out_done_int_st(&mut self) -> OUT_DONE_INT_ST_W<'_>

Bit 7

pub fn in_err_eof_int_st(&mut self) -> IN_ERR_EOF_INT_ST_W<'_>

Bit 6

pub fn in_suc_eof_int_st(&mut self) -> IN_SUC_EOF_INT_ST_W<'_>

Bit 5

pub fn in_done_int_st(&mut self) -> IN_DONE_INT_ST_W<'_>

Bit 4

pub fn tx_hung_int_st(&mut self) -> TX_HUNG_INT_ST_W<'_>

Bit 3

pub fn rx_hung_int_st(&mut self) -> RX_HUNG_INT_ST_W<'_>

Bit 2

pub fn tx_start_int_st(&mut self) -> TX_START_INT_ST_W<'_>

Bit 1

pub fn rx_start_int_st(&mut self) -> RX_START_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ENA>>

pub fn dma_infifo_full_wm_int_ena(&mut self) -> DMA_INFIFO_FULL_WM_INT_ENA_W<'_>

Bit 16

pub fn send_a_q_int_ena(&mut self) -> SEND_A_Q_INT_ENA_W<'_>

Bit 15

pub fn send_s_q_int_ena(&mut self) -> SEND_S_Q_INT_ENA_W<'_>

Bit 14

pub fn out_total_eof_int_ena(&mut self) -> OUT_TOTAL_EOF_INT_ENA_W<'_>

Bit 13

pub fn outlink_eof_err_int_ena(&mut self) -> OUTLINK_EOF_ERR_INT_ENA_W<'_>

Bit 12

pub fn in_dscr_empty_int_ena(&mut self) -> IN_DSCR_EMPTY_INT_ENA_W<'_>

Bit 11

pub fn out_dscr_err_int_ena(&mut self) -> OUT_DSCR_ERR_INT_ENA_W<'_>

Bit 10

pub fn in_dscr_err_int_ena(&mut self) -> IN_DSCR_ERR_INT_ENA_W<'_>

Bit 9

pub fn out_eof_int_ena(&mut self) -> OUT_EOF_INT_ENA_W<'_>

Bit 8

pub fn out_done_int_ena(&mut self) -> OUT_DONE_INT_ENA_W<'_>

Bit 7

pub fn in_err_eof_int_ena(&mut self) -> IN_ERR_EOF_INT_ENA_W<'_>

Bit 6

pub fn in_suc_eof_int_ena(&mut self) -> IN_SUC_EOF_INT_ENA_W<'_>

Bit 5

pub fn in_done_int_ena(&mut self) -> IN_DONE_INT_ENA_W<'_>

Bit 4

pub fn tx_hung_int_ena(&mut self) -> TX_HUNG_INT_ENA_W<'_>

Bit 3

pub fn rx_hung_int_ena(&mut self) -> RX_HUNG_INT_ENA_W<'_>

Bit 2

pub fn tx_start_int_ena(&mut self) -> TX_START_INT_ENA_W<'_>

Bit 1

pub fn rx_start_int_ena(&mut self) -> RX_START_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_CLR>>

pub fn dma_infifo_full_wm_int_clr(&mut self) -> DMA_INFIFO_FULL_WM_INT_CLR_W<'_>

Bit 16

pub fn send_a_q_int_clr(&mut self) -> SEND_A_Q_INT_CLR_W<'_>

Bit 15

pub fn send_s_q_int_clr(&mut self) -> SEND_S_Q_INT_CLR_W<'_>

Bit 14

pub fn out_total_eof_int_clr(&mut self) -> OUT_TOTAL_EOF_INT_CLR_W<'_>

Bit 13

pub fn outlink_eof_err_int_clr(&mut self) -> OUTLINK_EOF_ERR_INT_CLR_W<'_>

Bit 12

pub fn in_dscr_empty_int_clr(&mut self) -> IN_DSCR_EMPTY_INT_CLR_W<'_>

Bit 11

pub fn out_dscr_err_int_clr(&mut self) -> OUT_DSCR_ERR_INT_CLR_W<'_>

Bit 10

pub fn in_dscr_err_int_clr(&mut self) -> IN_DSCR_ERR_INT_CLR_W<'_>

Bit 9

pub fn out_eof_int_clr(&mut self) -> OUT_EOF_INT_CLR_W<'_>

Bit 8

pub fn out_done_int_clr(&mut self) -> OUT_DONE_INT_CLR_W<'_>

Bit 7

pub fn in_err_eof_int_clr(&mut self) -> IN_ERR_EOF_INT_CLR_W<'_>

Bit 6

pub fn in_suc_eof_int_clr(&mut self) -> IN_SUC_EOF_INT_CLR_W<'_>

Bit 5

pub fn in_done_int_clr(&mut self) -> IN_DONE_INT_CLR_W<'_>

Bit 4

pub fn tx_hung_int_clr(&mut self) -> TX_HUNG_INT_CLR_W<'_>

Bit 3

pub fn rx_hung_int_clr(&mut self) -> RX_HUNG_INT_CLR_W<'_>

Bit 2

pub fn tx_start_int_clr(&mut self) -> TX_START_INT_CLR_W<'_>

Bit 1

pub fn rx_start_int_clr(&mut self) -> RX_START_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, _DMA_OUT_STATUS>>

pub fn out_empty(&mut self) -> OUT_EMPTY_W<'_>

Bit 1

pub fn out_full(&mut self) -> OUT_FULL_W<'_>

Bit 0

impl W<u32, Reg<u32, _DMA_OUT_PUSH>>

pub fn outfifo_push(&mut self) -> OUTFIFO_PUSH_W<'_>

Bit 16

pub fn outfifo_wdata(&mut self) -> OUTFIFO_WDATA_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _DMA_IN_STATUS>>

pub fn rx_err_cause(&mut self) -> RX_ERR_CAUSE_W<'_>

Bits 4:6

pub fn in_empty(&mut self) -> IN_EMPTY_W<'_>

Bit 1

pub fn in_full(&mut self) -> IN_FULL_W<'_>

Bit 0

impl W<u32, Reg<u32, _DMA_IN_POP>>

pub fn infifo_pop(&mut self) -> INFIFO_POP_W<'_>

Bit 16

pub fn infifo_rdata(&mut self) -> INFIFO_RDATA_W<'_>

Bits 0:11

impl W<u32, Reg<u32, _DMA_OUT_LINK>>

pub fn outlink_park(&mut self) -> OUTLINK_PARK_W<'_>

Bit 31

pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<'_>

Bit 30

pub fn outlink_start(&mut self) -> OUTLINK_START_W<'_>

Bit 29

pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<'_>

Bit 28

pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _DMA_IN_LINK>>

pub fn inlink_park(&mut self) -> INLINK_PARK_W<'_>

Bit 31

pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<'_>

Bit 30

pub fn inlink_start(&mut self) -> INLINK_START_W<'_>

Bit 29

pub fn inlink_stop(&mut self) -> INLINK_STOP_W<'_>

Bit 28

pub fn inlink_auto_ret(&mut self) -> INLINK_AUTO_RET_W<'_>

Bit 20

pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _CONF1>>

pub fn dma_infifo_full_thrs(&mut self) -> DMA_INFIFO_FULL_THRS_W<'_>

Bits 9:20

pub fn sw_start(&mut self) -> SW_START_W<'_>

Bit 8

pub fn wait_sw_start(&mut self) -> WAIT_SW_START_W<'_>

Bit 7

pub fn check_owner(&mut self) -> CHECK_OWNER_W<'_>

Bit 6

pub fn tx_ack_num_re(&mut self) -> TX_ACK_NUM_RE_W<'_>

Bit 5

pub fn tx_check_sum_re(&mut self) -> TX_CHECK_SUM_RE_W<'_>

Bit 4

pub fn save_head(&mut self) -> SAVE_HEAD_W<'_>

Bit 3

pub fn crc_disable(&mut self) -> CRC_DISABLE_W<'_>

Bit 2

pub fn check_seq_en(&mut self) -> CHECK_SEQ_EN_W<'_>

Bit 1

pub fn check_sum_en(&mut self) -> CHECK_SUM_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _STATE0>>

pub fn state0(&mut self) -> STATE0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _STATE1>>

pub fn state1(&mut self) -> STATE1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DMA_OUT_EOF_DES_ADDR>>

pub fn out_eof_des_addr(&mut self) -> OUT_EOF_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DMA_IN_SUC_EOF_DES_ADDR>>

pub fn in_suc_eof_des_addr(&mut self) -> IN_SUC_EOF_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DMA_IN_ERR_EOF_DES_ADDR>>

pub fn in_err_eof_des_addr(&mut self) -> IN_ERR_EOF_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DMA_OUT_EOF_BFR_DES_ADDR>>

pub fn out_eof_bfr_des_addr(&mut self) -> OUT_EOF_BFR_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _AHB_TEST>>

pub fn ahb_testaddr(&mut self) -> AHB_TESTADDR_W<'_>

Bits 4:5

pub fn ahb_testmode(&mut self) -> AHB_TESTMODE_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _DMA_IN_DSCR>>

pub fn inlink_dscr(&mut self) -> INLINK_DSCR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DMA_IN_DSCR_BF0>>

pub fn inlink_dscr_bf0(&mut self) -> INLINK_DSCR_BF0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DMA_IN_DSCR_BF1>>

pub fn inlink_dscr_bf1(&mut self) -> INLINK_DSCR_BF1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DMA_OUT_DSCR>>

pub fn outlink_dscr(&mut self) -> OUTLINK_DSCR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DMA_OUT_DSCR_BF0>>

pub fn outlink_dscr_bf0(&mut self) -> OUTLINK_DSCR_BF0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DMA_OUT_DSCR_BF1>>

pub fn outlink_dscr_bf1(&mut self) -> OUTLINK_DSCR_BF1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _ESCAPE_CONF>>

pub fn rx_13_esc_en(&mut self) -> RX_13_ESC_EN_W<'_>

Bit 7

pub fn rx_11_esc_en(&mut self) -> RX_11_ESC_EN_W<'_>

Bit 6

pub fn rx_db_esc_en(&mut self) -> RX_DB_ESC_EN_W<'_>

Bit 5

pub fn rx_c0_esc_en(&mut self) -> RX_C0_ESC_EN_W<'_>

Bit 4

pub fn tx_13_esc_en(&mut self) -> TX_13_ESC_EN_W<'_>

Bit 3

pub fn tx_11_esc_en(&mut self) -> TX_11_ESC_EN_W<'_>

Bit 2

pub fn tx_db_esc_en(&mut self) -> TX_DB_ESC_EN_W<'_>

Bit 1

pub fn tx_c0_esc_en(&mut self) -> TX_C0_ESC_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _HUNG_CONF>>

pub fn rxfifo_timeout_ena(&mut self) -> RXFIFO_TIMEOUT_ENA_W<'_>

Bit 23

pub fn rxfifo_timeout_shift(&mut self) -> RXFIFO_TIMEOUT_SHIFT_W<'_>

Bits 20:22

pub fn rxfifo_timeout(&mut self) -> RXFIFO_TIMEOUT_W<'_>

Bits 12:19

pub fn txfifo_timeout_ena(&mut self) -> TXFIFO_TIMEOUT_ENA_W<'_>

Bit 11

pub fn txfifo_timeout_shift(&mut self) -> TXFIFO_TIMEOUT_SHIFT_W<'_>

Bits 8:10

pub fn txfifo_timeout(&mut self) -> TXFIFO_TIMEOUT_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _RX_HEAD>>

pub fn rx_head(&mut self) -> RX_HEAD_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _QUICK_SENT>>

pub fn always_send_en(&mut self) -> ALWAYS_SEND_EN_W<'_>

Bit 7

pub fn always_send_num(&mut self) -> ALWAYS_SEND_NUM_W<'_>

Bits 4:6

pub fn single_send_en(&mut self) -> SINGLE_SEND_EN_W<'_>

Bit 3

pub fn single_send_num(&mut self) -> SINGLE_SEND_NUM_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _Q0_WORD0>>

pub fn send_q0_word0(&mut self) -> SEND_Q0_WORD0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _Q0_WORD1>>

pub fn send_q0_word1(&mut self) -> SEND_Q0_WORD1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _Q1_WORD0>>

pub fn send_q1_word0(&mut self) -> SEND_Q1_WORD0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _Q1_WORD1>>

pub fn send_q1_word1(&mut self) -> SEND_Q1_WORD1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _Q2_WORD0>>

pub fn send_q2_word0(&mut self) -> SEND_Q2_WORD0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _Q2_WORD1>>

pub fn send_q2_word1(&mut self) -> SEND_Q2_WORD1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _Q3_WORD0>>

pub fn send_q3_word0(&mut self) -> SEND_Q3_WORD0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _Q3_WORD1>>

pub fn send_q3_word1(&mut self) -> SEND_Q3_WORD1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _Q4_WORD0>>

pub fn send_q4_word0(&mut self) -> SEND_Q4_WORD0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _Q4_WORD1>>

pub fn send_q4_word1(&mut self) -> SEND_Q4_WORD1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _Q5_WORD0>>

pub fn send_q5_word0(&mut self) -> SEND_Q5_WORD0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _Q5_WORD1>>

pub fn send_q5_word1(&mut self) -> SEND_Q5_WORD1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _Q6_WORD0>>

pub fn send_q6_word0(&mut self) -> SEND_Q6_WORD0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _Q6_WORD1>>

pub fn send_q6_word1(&mut self) -> SEND_Q6_WORD1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _ESC_CONF0>>

pub fn seper_esc_char1(&mut self) -> SEPER_ESC_CHAR1_W<'_>

Bits 16:23

pub fn seper_esc_char0(&mut self) -> SEPER_ESC_CHAR0_W<'_>

Bits 8:15

pub fn seper_char(&mut self) -> SEPER_CHAR_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _ESC_CONF1>>

pub fn esc_seq0_char1(&mut self) -> ESC_SEQ0_CHAR1_W<'_>

Bits 16:23

pub fn esc_seq0_char0(&mut self) -> ESC_SEQ0_CHAR0_W<'_>

Bits 8:15

pub fn esc_seq0(&mut self) -> ESC_SEQ0_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _ESC_CONF2>>

pub fn esc_seq1_char1(&mut self) -> ESC_SEQ1_CHAR1_W<'_>

Bits 16:23

pub fn esc_seq1_char0(&mut self) -> ESC_SEQ1_CHAR0_W<'_>

Bits 8:15

pub fn esc_seq1(&mut self) -> ESC_SEQ1_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _ESC_CONF3>>

pub fn esc_seq2_char1(&mut self) -> ESC_SEQ2_CHAR1_W<'_>

Bits 16:23

pub fn esc_seq2_char0(&mut self) -> ESC_SEQ2_CHAR0_W<'_>

Bits 8:15

pub fn esc_seq2(&mut self) -> ESC_SEQ2_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _PKT_THRES>>

pub fn pkt_thrs(&mut self) -> PKT_THRS_W<'_>

Bits 0:12

impl W<u32, Reg<u32, _DATE>>

pub fn date(&mut self) -> DATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _HOST_SLCHOST_FUNC2_0>>

pub fn host_slc_func2_int(&mut self) -> HOST_SLC_FUNC2_INT_W<'_>

Bit 24

impl W<u32, Reg<u32, _HOST_SLCHOST_FUNC2_1>>

pub fn host_slc_func2_int_en(&mut self) -> HOST_SLC_FUNC2_INT_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLCHOST_FUNC2_2>>

pub fn host_slc_func1_mdstat(&mut self) -> HOST_SLC_FUNC1_MDSTAT_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLCHOST_GPIO_STATUS0>>

pub fn host_gpio_sdio_int0(&mut self) -> HOST_GPIO_SDIO_INT0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _HOST_SLCHOST_GPIO_STATUS1>>

pub fn host_gpio_sdio_int1(&mut self) -> HOST_GPIO_SDIO_INT1_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_GPIO_IN0>>

pub fn host_gpio_sdio_in0(&mut self) -> HOST_GPIO_SDIO_IN0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _HOST_SLCHOST_GPIO_IN1>>

pub fn host_gpio_sdio_in1(&mut self) -> HOST_GPIO_SDIO_IN1_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLC0HOST_TOKEN_RDATA>>

pub fn host_slc0_rx_pf_eof(&mut self) -> HOST_SLC0_RX_PF_EOF_W<'_>

Bits 28:31

pub fn host_hostslc0_token1(&mut self) -> HOST_HOSTSLC0_TOKEN1_W<'_>

Bits 16:27

pub fn host_slc0_rx_pf_valid(&mut self) -> HOST_SLC0_RX_PF_VALID_W<'_>

Bit 12

pub fn host_slc0_token0(&mut self) -> HOST_SLC0_TOKEN0_W<'_>

Bits 0:11

impl W<u32, Reg<u32, _HOST_SLC0_HOST_PF>>

pub fn host_slc0_pf_data(&mut self) -> HOST_SLC0_PF_DATA_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _HOST_SLC1_HOST_PF>>

pub fn host_slc1_pf_data(&mut self) -> HOST_SLC1_PF_DATA_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _HOST_SLC0HOST_INT_RAW>>

pub fn host_gpio_sdio_int_raw(&mut self) -> HOST_GPIO_SDIO_INT_RAW_W<'_>

Bit 25

pub fn host_slc0_host_rd_retry_int_raw(
    &mut self
) -> HOST_SLC0_HOST_RD_RETRY_INT_RAW_W<'_>

Bit 24

pub fn host_slc0_rx_new_packet_int_raw(
    &mut self
) -> HOST_SLC0_RX_NEW_PACKET_INT_RAW_W<'_>

Bit 23

pub fn host_slc0_ext_bit3_int_raw(&mut self) -> HOST_SLC0_EXT_BIT3_INT_RAW_W<'_>

Bit 22

pub fn host_slc0_ext_bit2_int_raw(&mut self) -> HOST_SLC0_EXT_BIT2_INT_RAW_W<'_>

Bit 21

pub fn host_slc0_ext_bit1_int_raw(&mut self) -> HOST_SLC0_EXT_BIT1_INT_RAW_W<'_>

Bit 20

pub fn host_slc0_ext_bit0_int_raw(&mut self) -> HOST_SLC0_EXT_BIT0_INT_RAW_W<'_>

Bit 19

pub fn host_slc0_rx_pf_valid_int_raw(
    &mut self
) -> HOST_SLC0_RX_PF_VALID_INT_RAW_W<'_>

Bit 18

pub fn host_slc0_tx_ovf_int_raw(&mut self) -> HOST_SLC0_TX_OVF_INT_RAW_W<'_>

Bit 17

pub fn host_slc0_rx_udf_int_raw(&mut self) -> HOST_SLC0_RX_UDF_INT_RAW_W<'_>

Bit 16

pub fn host_slc0host_tx_start_int_raw(
    &mut self
) -> HOST_SLC0HOST_TX_START_INT_RAW_W<'_>

Bit 15

pub fn host_slc0host_rx_start_int_raw(
    &mut self
) -> HOST_SLC0HOST_RX_START_INT_RAW_W<'_>

Bit 14

pub fn host_slc0host_rx_eof_int_raw(
    &mut self
) -> HOST_SLC0HOST_RX_EOF_INT_RAW_W<'_>

Bit 13

pub fn host_slc0host_rx_sof_int_raw(
    &mut self
) -> HOST_SLC0HOST_RX_SOF_INT_RAW_W<'_>

Bit 12

pub fn host_slc0_token1_0to1_int_raw(
    &mut self
) -> HOST_SLC0_TOKEN1_0TO1_INT_RAW_W<'_>

Bit 11

pub fn host_slc0_token0_0to1_int_raw(
    &mut self
) -> HOST_SLC0_TOKEN0_0TO1_INT_RAW_W<'_>

Bit 10

pub fn host_slc0_token1_1to0_int_raw(
    &mut self
) -> HOST_SLC0_TOKEN1_1TO0_INT_RAW_W<'_>

Bit 9

pub fn host_slc0_token0_1to0_int_raw(
    &mut self
) -> HOST_SLC0_TOKEN0_1TO0_INT_RAW_W<'_>

Bit 8

pub fn host_slc0_tohost_bit7_int_raw(
    &mut self
) -> HOST_SLC0_TOHOST_BIT7_INT_RAW_W<'_>

Bit 7

pub fn host_slc0_tohost_bit6_int_raw(
    &mut self
) -> HOST_SLC0_TOHOST_BIT6_INT_RAW_W<'_>

Bit 6

pub fn host_slc0_tohost_bit5_int_raw(
    &mut self
) -> HOST_SLC0_TOHOST_BIT5_INT_RAW_W<'_>

Bit 5

pub fn host_slc0_tohost_bit4_int_raw(
    &mut self
) -> HOST_SLC0_TOHOST_BIT4_INT_RAW_W<'_>

Bit 4

pub fn host_slc0_tohost_bit3_int_raw(
    &mut self
) -> HOST_SLC0_TOHOST_BIT3_INT_RAW_W<'_>

Bit 3

pub fn host_slc0_tohost_bit2_int_raw(
    &mut self
) -> HOST_SLC0_TOHOST_BIT2_INT_RAW_W<'_>

Bit 2

pub fn host_slc0_tohost_bit1_int_raw(
    &mut self
) -> HOST_SLC0_TOHOST_BIT1_INT_RAW_W<'_>

Bit 1

pub fn host_slc0_tohost_bit0_int_raw(
    &mut self
) -> HOST_SLC0_TOHOST_BIT0_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLC1HOST_INT_RAW>>

pub fn host_slc1_bt_rx_new_packet_int_raw(
    &mut self
) -> HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_W<'_>

Bit 25

pub fn host_slc1_host_rd_retry_int_raw(
    &mut self
) -> HOST_SLC1_HOST_RD_RETRY_INT_RAW_W<'_>

Bit 24

pub fn host_slc1_wifi_rx_new_packet_int_raw(
    &mut self
) -> HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_W<'_>

Bit 23

pub fn host_slc1_ext_bit3_int_raw(&mut self) -> HOST_SLC1_EXT_BIT3_INT_RAW_W<'_>

Bit 22

pub fn host_slc1_ext_bit2_int_raw(&mut self) -> HOST_SLC1_EXT_BIT2_INT_RAW_W<'_>

Bit 21

pub fn host_slc1_ext_bit1_int_raw(&mut self) -> HOST_SLC1_EXT_BIT1_INT_RAW_W<'_>

Bit 20

pub fn host_slc1_ext_bit0_int_raw(&mut self) -> HOST_SLC1_EXT_BIT0_INT_RAW_W<'_>

Bit 19

pub fn host_slc1_rx_pf_valid_int_raw(
    &mut self
) -> HOST_SLC1_RX_PF_VALID_INT_RAW_W<'_>

Bit 18

pub fn host_slc1_tx_ovf_int_raw(&mut self) -> HOST_SLC1_TX_OVF_INT_RAW_W<'_>

Bit 17

pub fn host_slc1_rx_udf_int_raw(&mut self) -> HOST_SLC1_RX_UDF_INT_RAW_W<'_>

Bit 16

pub fn host_slc1host_tx_start_int_raw(
    &mut self
) -> HOST_SLC1HOST_TX_START_INT_RAW_W<'_>

Bit 15

pub fn host_slc1host_rx_start_int_raw(
    &mut self
) -> HOST_SLC1HOST_RX_START_INT_RAW_W<'_>

Bit 14

pub fn host_slc1host_rx_eof_int_raw(
    &mut self
) -> HOST_SLC1HOST_RX_EOF_INT_RAW_W<'_>

Bit 13

pub fn host_slc1host_rx_sof_int_raw(
    &mut self
) -> HOST_SLC1HOST_RX_SOF_INT_RAW_W<'_>

Bit 12

pub fn host_slc1_token1_0to1_int_raw(
    &mut self
) -> HOST_SLC1_TOKEN1_0TO1_INT_RAW_W<'_>

Bit 11

pub fn host_slc1_token0_0to1_int_raw(
    &mut self
) -> HOST_SLC1_TOKEN0_0TO1_INT_RAW_W<'_>

Bit 10

pub fn host_slc1_token1_1to0_int_raw(
    &mut self
) -> HOST_SLC1_TOKEN1_1TO0_INT_RAW_W<'_>

Bit 9

pub fn host_slc1_token0_1to0_int_raw(
    &mut self
) -> HOST_SLC1_TOKEN0_1TO0_INT_RAW_W<'_>

Bit 8

pub fn host_slc1_tohost_bit7_int_raw(
    &mut self
) -> HOST_SLC1_TOHOST_BIT7_INT_RAW_W<'_>

Bit 7

pub fn host_slc1_tohost_bit6_int_raw(
    &mut self
) -> HOST_SLC1_TOHOST_BIT6_INT_RAW_W<'_>

Bit 6

pub fn host_slc1_tohost_bit5_int_raw(
    &mut self
) -> HOST_SLC1_TOHOST_BIT5_INT_RAW_W<'_>

Bit 5

pub fn host_slc1_tohost_bit4_int_raw(
    &mut self
) -> HOST_SLC1_TOHOST_BIT4_INT_RAW_W<'_>

Bit 4

pub fn host_slc1_tohost_bit3_int_raw(
    &mut self
) -> HOST_SLC1_TOHOST_BIT3_INT_RAW_W<'_>

Bit 3

pub fn host_slc1_tohost_bit2_int_raw(
    &mut self
) -> HOST_SLC1_TOHOST_BIT2_INT_RAW_W<'_>

Bit 2

pub fn host_slc1_tohost_bit1_int_raw(
    &mut self
) -> HOST_SLC1_TOHOST_BIT1_INT_RAW_W<'_>

Bit 1

pub fn host_slc1_tohost_bit0_int_raw(
    &mut self
) -> HOST_SLC1_TOHOST_BIT0_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLC0HOST_INT_ST>>

pub fn host_gpio_sdio_int_st(&mut self) -> HOST_GPIO_SDIO_INT_ST_W<'_>

Bit 25

pub fn host_slc0_host_rd_retry_int_st(
    &mut self
) -> HOST_SLC0_HOST_RD_RETRY_INT_ST_W<'_>

Bit 24

pub fn host_slc0_rx_new_packet_int_st(
    &mut self
) -> HOST_SLC0_RX_NEW_PACKET_INT_ST_W<'_>

Bit 23

pub fn host_slc0_ext_bit3_int_st(&mut self) -> HOST_SLC0_EXT_BIT3_INT_ST_W<'_>

Bit 22

pub fn host_slc0_ext_bit2_int_st(&mut self) -> HOST_SLC0_EXT_BIT2_INT_ST_W<'_>

Bit 21

pub fn host_slc0_ext_bit1_int_st(&mut self) -> HOST_SLC0_EXT_BIT1_INT_ST_W<'_>

Bit 20

pub fn host_slc0_ext_bit0_int_st(&mut self) -> HOST_SLC0_EXT_BIT0_INT_ST_W<'_>

Bit 19

pub fn host_slc0_rx_pf_valid_int_st(
    &mut self
) -> HOST_SLC0_RX_PF_VALID_INT_ST_W<'_>

Bit 18

pub fn host_slc0_tx_ovf_int_st(&mut self) -> HOST_SLC0_TX_OVF_INT_ST_W<'_>

Bit 17

pub fn host_slc0_rx_udf_int_st(&mut self) -> HOST_SLC0_RX_UDF_INT_ST_W<'_>

Bit 16

pub fn host_slc0host_tx_start_int_st(
    &mut self
) -> HOST_SLC0HOST_TX_START_INT_ST_W<'_>

Bit 15

pub fn host_slc0host_rx_start_int_st(
    &mut self
) -> HOST_SLC0HOST_RX_START_INT_ST_W<'_>

Bit 14

pub fn host_slc0host_rx_eof_int_st(
    &mut self
) -> HOST_SLC0HOST_RX_EOF_INT_ST_W<'_>

Bit 13

pub fn host_slc0host_rx_sof_int_st(
    &mut self
) -> HOST_SLC0HOST_RX_SOF_INT_ST_W<'_>

Bit 12

pub fn host_slc0_token1_0to1_int_st(
    &mut self
) -> HOST_SLC0_TOKEN1_0TO1_INT_ST_W<'_>

Bit 11

pub fn host_slc0_token0_0to1_int_st(
    &mut self
) -> HOST_SLC0_TOKEN0_0TO1_INT_ST_W<'_>

Bit 10

pub fn host_slc0_token1_1to0_int_st(
    &mut self
) -> HOST_SLC0_TOKEN1_1TO0_INT_ST_W<'_>

Bit 9

pub fn host_slc0_token0_1to0_int_st(
    &mut self
) -> HOST_SLC0_TOKEN0_1TO0_INT_ST_W<'_>

Bit 8

pub fn host_slc0_tohost_bit7_int_st(
    &mut self
) -> HOST_SLC0_TOHOST_BIT7_INT_ST_W<'_>

Bit 7

pub fn host_slc0_tohost_bit6_int_st(
    &mut self
) -> HOST_SLC0_TOHOST_BIT6_INT_ST_W<'_>

Bit 6

pub fn host_slc0_tohost_bit5_int_st(
    &mut self
) -> HOST_SLC0_TOHOST_BIT5_INT_ST_W<'_>

Bit 5

pub fn host_slc0_tohost_bit4_int_st(
    &mut self
) -> HOST_SLC0_TOHOST_BIT4_INT_ST_W<'_>

Bit 4

pub fn host_slc0_tohost_bit3_int_st(
    &mut self
) -> HOST_SLC0_TOHOST_BIT3_INT_ST_W<'_>

Bit 3

pub fn host_slc0_tohost_bit2_int_st(
    &mut self
) -> HOST_SLC0_TOHOST_BIT2_INT_ST_W<'_>

Bit 2

pub fn host_slc0_tohost_bit1_int_st(
    &mut self
) -> HOST_SLC0_TOHOST_BIT1_INT_ST_W<'_>

Bit 1

pub fn host_slc0_tohost_bit0_int_st(
    &mut self
) -> HOST_SLC0_TOHOST_BIT0_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLC1HOST_INT_ST>>

pub fn host_slc1_bt_rx_new_packet_int_st(
    &mut self
) -> HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_W<'_>

Bit 25

pub fn host_slc1_host_rd_retry_int_st(
    &mut self
) -> HOST_SLC1_HOST_RD_RETRY_INT_ST_W<'_>

Bit 24

pub fn host_slc1_wifi_rx_new_packet_int_st(
    &mut self
) -> HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_W<'_>

Bit 23

pub fn host_slc1_ext_bit3_int_st(&mut self) -> HOST_SLC1_EXT_BIT3_INT_ST_W<'_>

Bit 22

pub fn host_slc1_ext_bit2_int_st(&mut self) -> HOST_SLC1_EXT_BIT2_INT_ST_W<'_>

Bit 21

pub fn host_slc1_ext_bit1_int_st(&mut self) -> HOST_SLC1_EXT_BIT1_INT_ST_W<'_>

Bit 20

pub fn host_slc1_ext_bit0_int_st(&mut self) -> HOST_SLC1_EXT_BIT0_INT_ST_W<'_>

Bit 19

pub fn host_slc1_rx_pf_valid_int_st(
    &mut self
) -> HOST_SLC1_RX_PF_VALID_INT_ST_W<'_>

Bit 18

pub fn host_slc1_tx_ovf_int_st(&mut self) -> HOST_SLC1_TX_OVF_INT_ST_W<'_>

Bit 17

pub fn host_slc1_rx_udf_int_st(&mut self) -> HOST_SLC1_RX_UDF_INT_ST_W<'_>

Bit 16

pub fn host_slc1host_tx_start_int_st(
    &mut self
) -> HOST_SLC1HOST_TX_START_INT_ST_W<'_>

Bit 15

pub fn host_slc1host_rx_start_int_st(
    &mut self
) -> HOST_SLC1HOST_RX_START_INT_ST_W<'_>

Bit 14

pub fn host_slc1host_rx_eof_int_st(
    &mut self
) -> HOST_SLC1HOST_RX_EOF_INT_ST_W<'_>

Bit 13

pub fn host_slc1host_rx_sof_int_st(
    &mut self
) -> HOST_SLC1HOST_RX_SOF_INT_ST_W<'_>

Bit 12

pub fn host_slc1_token1_0to1_int_st(
    &mut self
) -> HOST_SLC1_TOKEN1_0TO1_INT_ST_W<'_>

Bit 11

pub fn host_slc1_token0_0to1_int_st(
    &mut self
) -> HOST_SLC1_TOKEN0_0TO1_INT_ST_W<'_>

Bit 10

pub fn host_slc1_token1_1to0_int_st(
    &mut self
) -> HOST_SLC1_TOKEN1_1TO0_INT_ST_W<'_>

Bit 9

pub fn host_slc1_token0_1to0_int_st(
    &mut self
) -> HOST_SLC1_TOKEN0_1TO0_INT_ST_W<'_>

Bit 8

pub fn host_slc1_tohost_bit7_int_st(
    &mut self
) -> HOST_SLC1_TOHOST_BIT7_INT_ST_W<'_>

Bit 7

pub fn host_slc1_tohost_bit6_int_st(
    &mut self
) -> HOST_SLC1_TOHOST_BIT6_INT_ST_W<'_>

Bit 6

pub fn host_slc1_tohost_bit5_int_st(
    &mut self
) -> HOST_SLC1_TOHOST_BIT5_INT_ST_W<'_>

Bit 5

pub fn host_slc1_tohost_bit4_int_st(
    &mut self
) -> HOST_SLC1_TOHOST_BIT4_INT_ST_W<'_>

Bit 4

pub fn host_slc1_tohost_bit3_int_st(
    &mut self
) -> HOST_SLC1_TOHOST_BIT3_INT_ST_W<'_>

Bit 3

pub fn host_slc1_tohost_bit2_int_st(
    &mut self
) -> HOST_SLC1_TOHOST_BIT2_INT_ST_W<'_>

Bit 2

pub fn host_slc1_tohost_bit1_int_st(
    &mut self
) -> HOST_SLC1_TOHOST_BIT1_INT_ST_W<'_>

Bit 1

pub fn host_slc1_tohost_bit0_int_st(
    &mut self
) -> HOST_SLC1_TOHOST_BIT0_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLCHOST_PKT_LEN>>

pub fn host_hostslc0_len_check(&mut self) -> HOST_HOSTSLC0_LEN_CHECK_W<'_>

Bits 20:31

pub fn host_hostslc0_len(&mut self) -> HOST_HOSTSLC0_LEN_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HOST_SLCHOST_STATE_W0>>

pub fn host_slchost_state3(&mut self) -> HOST_SLCHOST_STATE3_W<'_>

Bits 24:31

pub fn host_slchost_state2(&mut self) -> HOST_SLCHOST_STATE2_W<'_>

Bits 16:23

pub fn host_slchost_state1(&mut self) -> HOST_SLCHOST_STATE1_W<'_>

Bits 8:15

pub fn host_slchost_state0(&mut self) -> HOST_SLCHOST_STATE0_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_STATE_W1>>

pub fn host_slchost_state7(&mut self) -> HOST_SLCHOST_STATE7_W<'_>

Bits 24:31

pub fn host_slchost_state6(&mut self) -> HOST_SLCHOST_STATE6_W<'_>

Bits 16:23

pub fn host_slchost_state5(&mut self) -> HOST_SLCHOST_STATE5_W<'_>

Bits 8:15

pub fn host_slchost_state4(&mut self) -> HOST_SLCHOST_STATE4_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W0>>

pub fn host_slchost_conf3(&mut self) -> HOST_SLCHOST_CONF3_W<'_>

Bits 24:31

pub fn host_slchost_conf2(&mut self) -> HOST_SLCHOST_CONF2_W<'_>

Bits 16:23

pub fn host_slchost_conf1(&mut self) -> HOST_SLCHOST_CONF1_W<'_>

Bits 8:15

pub fn host_slchost_conf0(&mut self) -> HOST_SLCHOST_CONF0_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W1>>

pub fn host_slchost_conf7(&mut self) -> HOST_SLCHOST_CONF7_W<'_>

Bits 24:31

pub fn host_slchost_conf6(&mut self) -> HOST_SLCHOST_CONF6_W<'_>

Bits 16:23

pub fn host_slchost_conf5(&mut self) -> HOST_SLCHOST_CONF5_W<'_>

Bits 8:15

pub fn host_slchost_conf4(&mut self) -> HOST_SLCHOST_CONF4_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W2>>

pub fn host_slchost_conf11(&mut self) -> HOST_SLCHOST_CONF11_W<'_>

Bits 24:31

pub fn host_slchost_conf10(&mut self) -> HOST_SLCHOST_CONF10_W<'_>

Bits 16:23

pub fn host_slchost_conf9(&mut self) -> HOST_SLCHOST_CONF9_W<'_>

Bits 8:15

pub fn host_slchost_conf8(&mut self) -> HOST_SLCHOST_CONF8_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W3>>

pub fn host_slchost_conf15(&mut self) -> HOST_SLCHOST_CONF15_W<'_>

Bits 24:31

pub fn host_slchost_conf14(&mut self) -> HOST_SLCHOST_CONF14_W<'_>

Bits 16:23

pub fn host_slchost_conf13(&mut self) -> HOST_SLCHOST_CONF13_W<'_>

Bits 8:15

pub fn host_slchost_conf12(&mut self) -> HOST_SLCHOST_CONF12_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W4>>

pub fn host_slchost_conf19(&mut self) -> HOST_SLCHOST_CONF19_W<'_>

Bits 24:31

pub fn host_slchost_conf18(&mut self) -> HOST_SLCHOST_CONF18_W<'_>

Bits 16:23

pub fn host_slchost_conf17(&mut self) -> HOST_SLCHOST_CONF17_W<'_>

Bits 8:15

pub fn host_slchost_conf16(&mut self) -> HOST_SLCHOST_CONF16_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W5>>

pub fn host_slchost_conf23(&mut self) -> HOST_SLCHOST_CONF23_W<'_>

Bits 24:31

pub fn host_slchost_conf22(&mut self) -> HOST_SLCHOST_CONF22_W<'_>

Bits 16:23

pub fn host_slchost_conf21(&mut self) -> HOST_SLCHOST_CONF21_W<'_>

Bits 8:15

pub fn host_slchost_conf20(&mut self) -> HOST_SLCHOST_CONF20_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W6>>

pub fn host_slchost_conf27(&mut self) -> HOST_SLCHOST_CONF27_W<'_>

Bits 24:31

pub fn host_slchost_conf26(&mut self) -> HOST_SLCHOST_CONF26_W<'_>

Bits 16:23

pub fn host_slchost_conf25(&mut self) -> HOST_SLCHOST_CONF25_W<'_>

Bits 8:15

pub fn host_slchost_conf24(&mut self) -> HOST_SLCHOST_CONF24_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W7>>

pub fn host_slchost_conf31(&mut self) -> HOST_SLCHOST_CONF31_W<'_>

Bits 24:31

pub fn host_slchost_conf30(&mut self) -> HOST_SLCHOST_CONF30_W<'_>

Bits 16:23

pub fn host_slchost_conf29(&mut self) -> HOST_SLCHOST_CONF29_W<'_>

Bits 8:15

pub fn host_slchost_conf28(&mut self) -> HOST_SLCHOST_CONF28_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_PKT_LEN0>>

pub fn host_hostslc0_len0(&mut self) -> HOST_HOSTSLC0_LEN0_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HOST_SLCHOST_PKT_LEN1>>

pub fn host_hostslc0_len1(&mut self) -> HOST_HOSTSLC0_LEN1_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HOST_SLCHOST_PKT_LEN2>>

pub fn host_hostslc0_len2(&mut self) -> HOST_HOSTSLC0_LEN2_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W8>>

pub fn host_slchost_conf35(&mut self) -> HOST_SLCHOST_CONF35_W<'_>

Bits 24:31

pub fn host_slchost_conf34(&mut self) -> HOST_SLCHOST_CONF34_W<'_>

Bits 16:23

pub fn host_slchost_conf33(&mut self) -> HOST_SLCHOST_CONF33_W<'_>

Bits 8:15

pub fn host_slchost_conf32(&mut self) -> HOST_SLCHOST_CONF32_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W9>>

pub fn host_slchost_conf39(&mut self) -> HOST_SLCHOST_CONF39_W<'_>

Bits 24:31

pub fn host_slchost_conf38(&mut self) -> HOST_SLCHOST_CONF38_W<'_>

Bits 16:23

pub fn host_slchost_conf37(&mut self) -> HOST_SLCHOST_CONF37_W<'_>

Bits 8:15

pub fn host_slchost_conf36(&mut self) -> HOST_SLCHOST_CONF36_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W10>>

pub fn host_slchost_conf43(&mut self) -> HOST_SLCHOST_CONF43_W<'_>

Bits 24:31

pub fn host_slchost_conf42(&mut self) -> HOST_SLCHOST_CONF42_W<'_>

Bits 16:23

pub fn host_slchost_conf41(&mut self) -> HOST_SLCHOST_CONF41_W<'_>

Bits 8:15

pub fn host_slchost_conf40(&mut self) -> HOST_SLCHOST_CONF40_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W11>>

pub fn host_slchost_conf47(&mut self) -> HOST_SLCHOST_CONF47_W<'_>

Bits 24:31

pub fn host_slchost_conf46(&mut self) -> HOST_SLCHOST_CONF46_W<'_>

Bits 16:23

pub fn host_slchost_conf45(&mut self) -> HOST_SLCHOST_CONF45_W<'_>

Bits 8:15

pub fn host_slchost_conf44(&mut self) -> HOST_SLCHOST_CONF44_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W12>>

pub fn host_slchost_conf51(&mut self) -> HOST_SLCHOST_CONF51_W<'_>

Bits 24:31

pub fn host_slchost_conf50(&mut self) -> HOST_SLCHOST_CONF50_W<'_>

Bits 16:23

pub fn host_slchost_conf49(&mut self) -> HOST_SLCHOST_CONF49_W<'_>

Bits 8:15

pub fn host_slchost_conf48(&mut self) -> HOST_SLCHOST_CONF48_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W13>>

pub fn host_slchost_conf55(&mut self) -> HOST_SLCHOST_CONF55_W<'_>

Bits 24:31

pub fn host_slchost_conf54(&mut self) -> HOST_SLCHOST_CONF54_W<'_>

Bits 16:23

pub fn host_slchost_conf53(&mut self) -> HOST_SLCHOST_CONF53_W<'_>

Bits 8:15

pub fn host_slchost_conf52(&mut self) -> HOST_SLCHOST_CONF52_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W14>>

pub fn host_slchost_conf59(&mut self) -> HOST_SLCHOST_CONF59_W<'_>

Bits 24:31

pub fn host_slchost_conf58(&mut self) -> HOST_SLCHOST_CONF58_W<'_>

Bits 16:23

pub fn host_slchost_conf57(&mut self) -> HOST_SLCHOST_CONF57_W<'_>

Bits 8:15

pub fn host_slchost_conf56(&mut self) -> HOST_SLCHOST_CONF56_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF_W15>>

pub fn host_slchost_conf63(&mut self) -> HOST_SLCHOST_CONF63_W<'_>

Bits 24:31

pub fn host_slchost_conf62(&mut self) -> HOST_SLCHOST_CONF62_W<'_>

Bits 16:23

pub fn host_slchost_conf61(&mut self) -> HOST_SLCHOST_CONF61_W<'_>

Bits 8:15

pub fn host_slchost_conf60(&mut self) -> HOST_SLCHOST_CONF60_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _HOST_SLCHOST_CHECK_SUM0>>

pub fn host_slchost_check_sum0(&mut self) -> HOST_SLCHOST_CHECK_SUM0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _HOST_SLCHOST_CHECK_SUM1>>

pub fn host_slchost_check_sum1(&mut self) -> HOST_SLCHOST_CHECK_SUM1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _HOST_SLC1HOST_TOKEN_RDATA>>

pub fn host_slc1_rx_pf_eof(&mut self) -> HOST_SLC1_RX_PF_EOF_W<'_>

Bits 28:31

pub fn host_hostslc1_token1(&mut self) -> HOST_HOSTSLC1_TOKEN1_W<'_>

Bits 16:27

pub fn host_slc1_rx_pf_valid(&mut self) -> HOST_SLC1_RX_PF_VALID_W<'_>

Bit 12

pub fn host_slc1_token0(&mut self) -> HOST_SLC1_TOKEN0_W<'_>

Bits 0:11

impl W<u32, Reg<u32, _HOST_SLC0HOST_TOKEN_WDATA>>

pub fn host_slc0host_token1_wd(&mut self) -> HOST_SLC0HOST_TOKEN1_WD_W<'_>

Bits 16:27

pub fn host_slc0host_token0_wd(&mut self) -> HOST_SLC0HOST_TOKEN0_WD_W<'_>

Bits 0:11

impl W<u32, Reg<u32, _HOST_SLC1HOST_TOKEN_WDATA>>

pub fn host_slc1host_token1_wd(&mut self) -> HOST_SLC1HOST_TOKEN1_WD_W<'_>

Bits 16:27

pub fn host_slc1host_token0_wd(&mut self) -> HOST_SLC1HOST_TOKEN0_WD_W<'_>

Bits 0:11

impl W<u32, Reg<u32, _HOST_SLCHOST_TOKEN_CON>>

pub fn host_slc0host_len_wr(&mut self) -> HOST_SLC0HOST_LEN_WR_W<'_>

Bit 8

pub fn host_slc1host_token1_wr(&mut self) -> HOST_SLC1HOST_TOKEN1_WR_W<'_>

Bit 7

pub fn host_slc1host_token0_wr(&mut self) -> HOST_SLC1HOST_TOKEN0_WR_W<'_>

Bit 6

pub fn host_slc1host_token1_dec(&mut self) -> HOST_SLC1HOST_TOKEN1_DEC_W<'_>

Bit 5

pub fn host_slc1host_token0_dec(&mut self) -> HOST_SLC1HOST_TOKEN0_DEC_W<'_>

Bit 4

pub fn host_slc0host_token1_wr(&mut self) -> HOST_SLC0HOST_TOKEN1_WR_W<'_>

Bit 3

pub fn host_slc0host_token0_wr(&mut self) -> HOST_SLC0HOST_TOKEN0_WR_W<'_>

Bit 2

pub fn host_slc0host_token1_dec(&mut self) -> HOST_SLC0HOST_TOKEN1_DEC_W<'_>

Bit 1

pub fn host_slc0host_token0_dec(&mut self) -> HOST_SLC0HOST_TOKEN0_DEC_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLC0HOST_INT_CLR>>

pub fn host_gpio_sdio_int_clr(&mut self) -> HOST_GPIO_SDIO_INT_CLR_W<'_>

Bit 25

pub fn host_slc0_host_rd_retry_int_clr(
    &mut self
) -> HOST_SLC0_HOST_RD_RETRY_INT_CLR_W<'_>

Bit 24

pub fn host_slc0_rx_new_packet_int_clr(
    &mut self
) -> HOST_SLC0_RX_NEW_PACKET_INT_CLR_W<'_>

Bit 23

pub fn host_slc0_ext_bit3_int_clr(&mut self) -> HOST_SLC0_EXT_BIT3_INT_CLR_W<'_>

Bit 22

pub fn host_slc0_ext_bit2_int_clr(&mut self) -> HOST_SLC0_EXT_BIT2_INT_CLR_W<'_>

Bit 21

pub fn host_slc0_ext_bit1_int_clr(&mut self) -> HOST_SLC0_EXT_BIT1_INT_CLR_W<'_>

Bit 20

pub fn host_slc0_ext_bit0_int_clr(&mut self) -> HOST_SLC0_EXT_BIT0_INT_CLR_W<'_>

Bit 19

pub fn host_slc0_rx_pf_valid_int_clr(
    &mut self
) -> HOST_SLC0_RX_PF_VALID_INT_CLR_W<'_>

Bit 18

pub fn host_slc0_tx_ovf_int_clr(&mut self) -> HOST_SLC0_TX_OVF_INT_CLR_W<'_>

Bit 17

pub fn host_slc0_rx_udf_int_clr(&mut self) -> HOST_SLC0_RX_UDF_INT_CLR_W<'_>

Bit 16

pub fn host_slc0host_tx_start_int_clr(
    &mut self
) -> HOST_SLC0HOST_TX_START_INT_CLR_W<'_>

Bit 15

pub fn host_slc0host_rx_start_int_clr(
    &mut self
) -> HOST_SLC0HOST_RX_START_INT_CLR_W<'_>

Bit 14

pub fn host_slc0host_rx_eof_int_clr(
    &mut self
) -> HOST_SLC0HOST_RX_EOF_INT_CLR_W<'_>

Bit 13

pub fn host_slc0host_rx_sof_int_clr(
    &mut self
) -> HOST_SLC0HOST_RX_SOF_INT_CLR_W<'_>

Bit 12

pub fn host_slc0_token1_0to1_int_clr(
    &mut self
) -> HOST_SLC0_TOKEN1_0TO1_INT_CLR_W<'_>

Bit 11

pub fn host_slc0_token0_0to1_int_clr(
    &mut self
) -> HOST_SLC0_TOKEN0_0TO1_INT_CLR_W<'_>

Bit 10

pub fn host_slc0_token1_1to0_int_clr(
    &mut self
) -> HOST_SLC0_TOKEN1_1TO0_INT_CLR_W<'_>

Bit 9

pub fn host_slc0_token0_1to0_int_clr(
    &mut self
) -> HOST_SLC0_TOKEN0_1TO0_INT_CLR_W<'_>

Bit 8

pub fn host_slc0_tohost_bit7_int_clr(
    &mut self
) -> HOST_SLC0_TOHOST_BIT7_INT_CLR_W<'_>

Bit 7

pub fn host_slc0_tohost_bit6_int_clr(
    &mut self
) -> HOST_SLC0_TOHOST_BIT6_INT_CLR_W<'_>

Bit 6

pub fn host_slc0_tohost_bit5_int_clr(
    &mut self
) -> HOST_SLC0_TOHOST_BIT5_INT_CLR_W<'_>

Bit 5

pub fn host_slc0_tohost_bit4_int_clr(
    &mut self
) -> HOST_SLC0_TOHOST_BIT4_INT_CLR_W<'_>

Bit 4

pub fn host_slc0_tohost_bit3_int_clr(
    &mut self
) -> HOST_SLC0_TOHOST_BIT3_INT_CLR_W<'_>

Bit 3

pub fn host_slc0_tohost_bit2_int_clr(
    &mut self
) -> HOST_SLC0_TOHOST_BIT2_INT_CLR_W<'_>

Bit 2

pub fn host_slc0_tohost_bit1_int_clr(
    &mut self
) -> HOST_SLC0_TOHOST_BIT1_INT_CLR_W<'_>

Bit 1

pub fn host_slc0_tohost_bit0_int_clr(
    &mut self
) -> HOST_SLC0_TOHOST_BIT0_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLC1HOST_INT_CLR>>

pub fn host_slc1_bt_rx_new_packet_int_clr(
    &mut self
) -> HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_W<'_>

Bit 25

pub fn host_slc1_host_rd_retry_int_clr(
    &mut self
) -> HOST_SLC1_HOST_RD_RETRY_INT_CLR_W<'_>

Bit 24

pub fn host_slc1_wifi_rx_new_packet_int_clr(
    &mut self
) -> HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_W<'_>

Bit 23

pub fn host_slc1_ext_bit3_int_clr(&mut self) -> HOST_SLC1_EXT_BIT3_INT_CLR_W<'_>

Bit 22

pub fn host_slc1_ext_bit2_int_clr(&mut self) -> HOST_SLC1_EXT_BIT2_INT_CLR_W<'_>

Bit 21

pub fn host_slc1_ext_bit1_int_clr(&mut self) -> HOST_SLC1_EXT_BIT1_INT_CLR_W<'_>

Bit 20

pub fn host_slc1_ext_bit0_int_clr(&mut self) -> HOST_SLC1_EXT_BIT0_INT_CLR_W<'_>

Bit 19

pub fn host_slc1_rx_pf_valid_int_clr(
    &mut self
) -> HOST_SLC1_RX_PF_VALID_INT_CLR_W<'_>

Bit 18

pub fn host_slc1_tx_ovf_int_clr(&mut self) -> HOST_SLC1_TX_OVF_INT_CLR_W<'_>

Bit 17

pub fn host_slc1_rx_udf_int_clr(&mut self) -> HOST_SLC1_RX_UDF_INT_CLR_W<'_>

Bit 16

pub fn host_slc1host_tx_start_int_clr(
    &mut self
) -> HOST_SLC1HOST_TX_START_INT_CLR_W<'_>

Bit 15

pub fn host_slc1host_rx_start_int_clr(
    &mut self
) -> HOST_SLC1HOST_RX_START_INT_CLR_W<'_>

Bit 14

pub fn host_slc1host_rx_eof_int_clr(
    &mut self
) -> HOST_SLC1HOST_RX_EOF_INT_CLR_W<'_>

Bit 13

pub fn host_slc1host_rx_sof_int_clr(
    &mut self
) -> HOST_SLC1HOST_RX_SOF_INT_CLR_W<'_>

Bit 12

pub fn host_slc1_token1_0to1_int_clr(
    &mut self
) -> HOST_SLC1_TOKEN1_0TO1_INT_CLR_W<'_>

Bit 11

pub fn host_slc1_token0_0to1_int_clr(
    &mut self
) -> HOST_SLC1_TOKEN0_0TO1_INT_CLR_W<'_>

Bit 10

pub fn host_slc1_token1_1to0_int_clr(
    &mut self
) -> HOST_SLC1_TOKEN1_1TO0_INT_CLR_W<'_>

Bit 9

pub fn host_slc1_token0_1to0_int_clr(
    &mut self
) -> HOST_SLC1_TOKEN0_1TO0_INT_CLR_W<'_>

Bit 8

pub fn host_slc1_tohost_bit7_int_clr(
    &mut self
) -> HOST_SLC1_TOHOST_BIT7_INT_CLR_W<'_>

Bit 7

pub fn host_slc1_tohost_bit6_int_clr(
    &mut self
) -> HOST_SLC1_TOHOST_BIT6_INT_CLR_W<'_>

Bit 6

pub fn host_slc1_tohost_bit5_int_clr(
    &mut self
) -> HOST_SLC1_TOHOST_BIT5_INT_CLR_W<'_>

Bit 5

pub fn host_slc1_tohost_bit4_int_clr(
    &mut self
) -> HOST_SLC1_TOHOST_BIT4_INT_CLR_W<'_>

Bit 4

pub fn host_slc1_tohost_bit3_int_clr(
    &mut self
) -> HOST_SLC1_TOHOST_BIT3_INT_CLR_W<'_>

Bit 3

pub fn host_slc1_tohost_bit2_int_clr(
    &mut self
) -> HOST_SLC1_TOHOST_BIT2_INT_CLR_W<'_>

Bit 2

pub fn host_slc1_tohost_bit1_int_clr(
    &mut self
) -> HOST_SLC1_TOHOST_BIT1_INT_CLR_W<'_>

Bit 1

pub fn host_slc1_tohost_bit0_int_clr(
    &mut self
) -> HOST_SLC1_TOHOST_BIT0_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLC0HOST_FUNC1_INT_ENA>>

pub fn host_fn1_gpio_sdio_int_ena(&mut self) -> HOST_FN1_GPIO_SDIO_INT_ENA_W<'_>

Bit 25

pub fn host_fn1_slc0_host_rd_retry_int_ena(
    &mut self
) -> HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_W<'_>

Bit 24

pub fn host_fn1_slc0_rx_new_packet_int_ena(
    &mut self
) -> HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_W<'_>

Bit 23

pub fn host_fn1_slc0_ext_bit3_int_ena(
    &mut self
) -> HOST_FN1_SLC0_EXT_BIT3_INT_ENA_W<'_>

Bit 22

pub fn host_fn1_slc0_ext_bit2_int_ena(
    &mut self
) -> HOST_FN1_SLC0_EXT_BIT2_INT_ENA_W<'_>

Bit 21

pub fn host_fn1_slc0_ext_bit1_int_ena(
    &mut self
) -> HOST_FN1_SLC0_EXT_BIT1_INT_ENA_W<'_>

Bit 20

pub fn host_fn1_slc0_ext_bit0_int_ena(
    &mut self
) -> HOST_FN1_SLC0_EXT_BIT0_INT_ENA_W<'_>

Bit 19

pub fn host_fn1_slc0_rx_pf_valid_int_ena(
    &mut self
) -> HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_W<'_>

Bit 18

pub fn host_fn1_slc0_tx_ovf_int_ena(
    &mut self
) -> HOST_FN1_SLC0_TX_OVF_INT_ENA_W<'_>

Bit 17

pub fn host_fn1_slc0_rx_udf_int_ena(
    &mut self
) -> HOST_FN1_SLC0_RX_UDF_INT_ENA_W<'_>

Bit 16

pub fn host_fn1_slc0host_tx_start_int_ena(
    &mut self
) -> HOST_FN1_SLC0HOST_TX_START_INT_ENA_W<'_>

Bit 15

pub fn host_fn1_slc0host_rx_start_int_ena(
    &mut self
) -> HOST_FN1_SLC0HOST_RX_START_INT_ENA_W<'_>

Bit 14

pub fn host_fn1_slc0host_rx_eof_int_ena(
    &mut self
) -> HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_W<'_>

Bit 13

pub fn host_fn1_slc0host_rx_sof_int_ena(
    &mut self
) -> HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_W<'_>

Bit 12

pub fn host_fn1_slc0_token1_0to1_int_ena(
    &mut self
) -> HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_W<'_>

Bit 11

pub fn host_fn1_slc0_token0_0to1_int_ena(
    &mut self
) -> HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_W<'_>

Bit 10

pub fn host_fn1_slc0_token1_1to0_int_ena(
    &mut self
) -> HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_W<'_>

Bit 9

pub fn host_fn1_slc0_token0_1to0_int_ena(
    &mut self
) -> HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_W<'_>

Bit 8

pub fn host_fn1_slc0_tohost_bit7_int_ena(
    &mut self
) -> HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_W<'_>

Bit 7

pub fn host_fn1_slc0_tohost_bit6_int_ena(
    &mut self
) -> HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_W<'_>

Bit 6

pub fn host_fn1_slc0_tohost_bit5_int_ena(
    &mut self
) -> HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_W<'_>

Bit 5

pub fn host_fn1_slc0_tohost_bit4_int_ena(
    &mut self
) -> HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_W<'_>

Bit 4

pub fn host_fn1_slc0_tohost_bit3_int_ena(
    &mut self
) -> HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_W<'_>

Bit 3

pub fn host_fn1_slc0_tohost_bit2_int_ena(
    &mut self
) -> HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_W<'_>

Bit 2

pub fn host_fn1_slc0_tohost_bit1_int_ena(
    &mut self
) -> HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_W<'_>

Bit 1

pub fn host_fn1_slc0_tohost_bit0_int_ena(
    &mut self
) -> HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLC1HOST_FUNC1_INT_ENA>>

pub fn host_fn1_slc1_bt_rx_new_packet_int_ena(
    &mut self
) -> HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_W<'_>

Bit 25

pub fn host_fn1_slc1_host_rd_retry_int_ena(
    &mut self
) -> HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_W<'_>

Bit 24

pub fn host_fn1_slc1_wifi_rx_new_packet_int_ena(
    &mut self
) -> HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_W<'_>

Bit 23

pub fn host_fn1_slc1_ext_bit3_int_ena(
    &mut self
) -> HOST_FN1_SLC1_EXT_BIT3_INT_ENA_W<'_>

Bit 22

pub fn host_fn1_slc1_ext_bit2_int_ena(
    &mut self
) -> HOST_FN1_SLC1_EXT_BIT2_INT_ENA_W<'_>

Bit 21

pub fn host_fn1_slc1_ext_bit1_int_ena(
    &mut self
) -> HOST_FN1_SLC1_EXT_BIT1_INT_ENA_W<'_>

Bit 20

pub fn host_fn1_slc1_ext_bit0_int_ena(
    &mut self
) -> HOST_FN1_SLC1_EXT_BIT0_INT_ENA_W<'_>

Bit 19

pub fn host_fn1_slc1_rx_pf_valid_int_ena(
    &mut self
) -> HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_W<'_>

Bit 18

pub fn host_fn1_slc1_tx_ovf_int_ena(
    &mut self
) -> HOST_FN1_SLC1_TX_OVF_INT_ENA_W<'_>

Bit 17

pub fn host_fn1_slc1_rx_udf_int_ena(
    &mut self
) -> HOST_FN1_SLC1_RX_UDF_INT_ENA_W<'_>

Bit 16

pub fn host_fn1_slc1host_tx_start_int_ena(
    &mut self
) -> HOST_FN1_SLC1HOST_TX_START_INT_ENA_W<'_>

Bit 15

pub fn host_fn1_slc1host_rx_start_int_ena(
    &mut self
) -> HOST_FN1_SLC1HOST_RX_START_INT_ENA_W<'_>

Bit 14

pub fn host_fn1_slc1host_rx_eof_int_ena(
    &mut self
) -> HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_W<'_>

Bit 13

pub fn host_fn1_slc1host_rx_sof_int_ena(
    &mut self
) -> HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_W<'_>

Bit 12

pub fn host_fn1_slc1_token1_0to1_int_ena(
    &mut self
) -> HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_W<'_>

Bit 11

pub fn host_fn1_slc1_token0_0to1_int_ena(
    &mut self
) -> HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_W<'_>

Bit 10

pub fn host_fn1_slc1_token1_1to0_int_ena(
    &mut self
) -> HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_W<'_>

Bit 9

pub fn host_fn1_slc1_token0_1to0_int_ena(
    &mut self
) -> HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_W<'_>

Bit 8

pub fn host_fn1_slc1_tohost_bit7_int_ena(
    &mut self
) -> HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_W<'_>

Bit 7

pub fn host_fn1_slc1_tohost_bit6_int_ena(
    &mut self
) -> HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_W<'_>

Bit 6

pub fn host_fn1_slc1_tohost_bit5_int_ena(
    &mut self
) -> HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_W<'_>

Bit 5

pub fn host_fn1_slc1_tohost_bit4_int_ena(
    &mut self
) -> HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_W<'_>

Bit 4

pub fn host_fn1_slc1_tohost_bit3_int_ena(
    &mut self
) -> HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_W<'_>

Bit 3

pub fn host_fn1_slc1_tohost_bit2_int_ena(
    &mut self
) -> HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_W<'_>

Bit 2

pub fn host_fn1_slc1_tohost_bit1_int_ena(
    &mut self
) -> HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_W<'_>

Bit 1

pub fn host_fn1_slc1_tohost_bit0_int_ena(
    &mut self
) -> HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLC0HOST_FUNC2_INT_ENA>>

pub fn host_fn2_gpio_sdio_int_ena(&mut self) -> HOST_FN2_GPIO_SDIO_INT_ENA_W<'_>

Bit 25

pub fn host_fn2_slc0_host_rd_retry_int_ena(
    &mut self
) -> HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_W<'_>

Bit 24

pub fn host_fn2_slc0_rx_new_packet_int_ena(
    &mut self
) -> HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_W<'_>

Bit 23

pub fn host_fn2_slc0_ext_bit3_int_ena(
    &mut self
) -> HOST_FN2_SLC0_EXT_BIT3_INT_ENA_W<'_>

Bit 22

pub fn host_fn2_slc0_ext_bit2_int_ena(
    &mut self
) -> HOST_FN2_SLC0_EXT_BIT2_INT_ENA_W<'_>

Bit 21

pub fn host_fn2_slc0_ext_bit1_int_ena(
    &mut self
) -> HOST_FN2_SLC0_EXT_BIT1_INT_ENA_W<'_>

Bit 20

pub fn host_fn2_slc0_ext_bit0_int_ena(
    &mut self
) -> HOST_FN2_SLC0_EXT_BIT0_INT_ENA_W<'_>

Bit 19

pub fn host_fn2_slc0_rx_pf_valid_int_ena(
    &mut self
) -> HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_W<'_>

Bit 18

pub fn host_fn2_slc0_tx_ovf_int_ena(
    &mut self
) -> HOST_FN2_SLC0_TX_OVF_INT_ENA_W<'_>

Bit 17

pub fn host_fn2_slc0_rx_udf_int_ena(
    &mut self
) -> HOST_FN2_SLC0_RX_UDF_INT_ENA_W<'_>

Bit 16

pub fn host_fn2_slc0host_tx_start_int_ena(
    &mut self
) -> HOST_FN2_SLC0HOST_TX_START_INT_ENA_W<'_>

Bit 15

pub fn host_fn2_slc0host_rx_start_int_ena(
    &mut self
) -> HOST_FN2_SLC0HOST_RX_START_INT_ENA_W<'_>

Bit 14

pub fn host_fn2_slc0host_rx_eof_int_ena(
    &mut self
) -> HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_W<'_>

Bit 13

pub fn host_fn2_slc0host_rx_sof_int_ena(
    &mut self
) -> HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_W<'_>

Bit 12

pub fn host_fn2_slc0_token1_0to1_int_ena(
    &mut self
) -> HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_W<'_>

Bit 11

pub fn host_fn2_slc0_token0_0to1_int_ena(
    &mut self
) -> HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_W<'_>

Bit 10

pub fn host_fn2_slc0_token1_1to0_int_ena(
    &mut self
) -> HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_W<'_>

Bit 9

pub fn host_fn2_slc0_token0_1to0_int_ena(
    &mut self
) -> HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_W<'_>

Bit 8

pub fn host_fn2_slc0_tohost_bit7_int_ena(
    &mut self
) -> HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_W<'_>

Bit 7

pub fn host_fn2_slc0_tohost_bit6_int_ena(
    &mut self
) -> HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_W<'_>

Bit 6

pub fn host_fn2_slc0_tohost_bit5_int_ena(
    &mut self
) -> HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_W<'_>

Bit 5

pub fn host_fn2_slc0_tohost_bit4_int_ena(
    &mut self
) -> HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_W<'_>

Bit 4

pub fn host_fn2_slc0_tohost_bit3_int_ena(
    &mut self
) -> HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_W<'_>

Bit 3

pub fn host_fn2_slc0_tohost_bit2_int_ena(
    &mut self
) -> HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_W<'_>

Bit 2

pub fn host_fn2_slc0_tohost_bit1_int_ena(
    &mut self
) -> HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_W<'_>

Bit 1

pub fn host_fn2_slc0_tohost_bit0_int_ena(
    &mut self
) -> HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLC1HOST_FUNC2_INT_ENA>>

pub fn host_fn2_slc1_bt_rx_new_packet_int_ena(
    &mut self
) -> HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_W<'_>

Bit 25

pub fn host_fn2_slc1_host_rd_retry_int_ena(
    &mut self
) -> HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_W<'_>

Bit 24

pub fn host_fn2_slc1_wifi_rx_new_packet_int_ena(
    &mut self
) -> HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_W<'_>

Bit 23

pub fn host_fn2_slc1_ext_bit3_int_ena(
    &mut self
) -> HOST_FN2_SLC1_EXT_BIT3_INT_ENA_W<'_>

Bit 22

pub fn host_fn2_slc1_ext_bit2_int_ena(
    &mut self
) -> HOST_FN2_SLC1_EXT_BIT2_INT_ENA_W<'_>

Bit 21

pub fn host_fn2_slc1_ext_bit1_int_ena(
    &mut self
) -> HOST_FN2_SLC1_EXT_BIT1_INT_ENA_W<'_>

Bit 20

pub fn host_fn2_slc1_ext_bit0_int_ena(
    &mut self
) -> HOST_FN2_SLC1_EXT_BIT0_INT_ENA_W<'_>

Bit 19

pub fn host_fn2_slc1_rx_pf_valid_int_ena(
    &mut self
) -> HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_W<'_>

Bit 18

pub fn host_fn2_slc1_tx_ovf_int_ena(
    &mut self
) -> HOST_FN2_SLC1_TX_OVF_INT_ENA_W<'_>

Bit 17

pub fn host_fn2_slc1_rx_udf_int_ena(
    &mut self
) -> HOST_FN2_SLC1_RX_UDF_INT_ENA_W<'_>

Bit 16

pub fn host_fn2_slc1host_tx_start_int_ena(
    &mut self
) -> HOST_FN2_SLC1HOST_TX_START_INT_ENA_W<'_>

Bit 15

pub fn host_fn2_slc1host_rx_start_int_ena(
    &mut self
) -> HOST_FN2_SLC1HOST_RX_START_INT_ENA_W<'_>

Bit 14

pub fn host_fn2_slc1host_rx_eof_int_ena(
    &mut self
) -> HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_W<'_>

Bit 13

pub fn host_fn2_slc1host_rx_sof_int_ena(
    &mut self
) -> HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_W<'_>

Bit 12

pub fn host_fn2_slc1_token1_0to1_int_ena(
    &mut self
) -> HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_W<'_>

Bit 11

pub fn host_fn2_slc1_token0_0to1_int_ena(
    &mut self
) -> HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_W<'_>

Bit 10

pub fn host_fn2_slc1_token1_1to0_int_ena(
    &mut self
) -> HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_W<'_>

Bit 9

pub fn host_fn2_slc1_token0_1to0_int_ena(
    &mut self
) -> HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_W<'_>

Bit 8

pub fn host_fn2_slc1_tohost_bit7_int_ena(
    &mut self
) -> HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_W<'_>

Bit 7

pub fn host_fn2_slc1_tohost_bit6_int_ena(
    &mut self
) -> HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_W<'_>

Bit 6

pub fn host_fn2_slc1_tohost_bit5_int_ena(
    &mut self
) -> HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_W<'_>

Bit 5

pub fn host_fn2_slc1_tohost_bit4_int_ena(
    &mut self
) -> HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_W<'_>

Bit 4

pub fn host_fn2_slc1_tohost_bit3_int_ena(
    &mut self
) -> HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_W<'_>

Bit 3

pub fn host_fn2_slc1_tohost_bit2_int_ena(
    &mut self
) -> HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_W<'_>

Bit 2

pub fn host_fn2_slc1_tohost_bit1_int_ena(
    &mut self
) -> HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_W<'_>

Bit 1

pub fn host_fn2_slc1_tohost_bit0_int_ena(
    &mut self
) -> HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLC0HOST_INT_ENA>>

pub fn host_gpio_sdio_int_ena(&mut self) -> HOST_GPIO_SDIO_INT_ENA_W<'_>

Bit 25

pub fn host_slc0_host_rd_retry_int_ena(
    &mut self
) -> HOST_SLC0_HOST_RD_RETRY_INT_ENA_W<'_>

Bit 24

pub fn host_slc0_rx_new_packet_int_ena(
    &mut self
) -> HOST_SLC0_RX_NEW_PACKET_INT_ENA_W<'_>

Bit 23

pub fn host_slc0_ext_bit3_int_ena(&mut self) -> HOST_SLC0_EXT_BIT3_INT_ENA_W<'_>

Bit 22

pub fn host_slc0_ext_bit2_int_ena(&mut self) -> HOST_SLC0_EXT_BIT2_INT_ENA_W<'_>

Bit 21

pub fn host_slc0_ext_bit1_int_ena(&mut self) -> HOST_SLC0_EXT_BIT1_INT_ENA_W<'_>

Bit 20

pub fn host_slc0_ext_bit0_int_ena(&mut self) -> HOST_SLC0_EXT_BIT0_INT_ENA_W<'_>

Bit 19

pub fn host_slc0_rx_pf_valid_int_ena(
    &mut self
) -> HOST_SLC0_RX_PF_VALID_INT_ENA_W<'_>

Bit 18

pub fn host_slc0_tx_ovf_int_ena(&mut self) -> HOST_SLC0_TX_OVF_INT_ENA_W<'_>

Bit 17

pub fn host_slc0_rx_udf_int_ena(&mut self) -> HOST_SLC0_RX_UDF_INT_ENA_W<'_>

Bit 16

pub fn host_slc0host_tx_start_int_ena(
    &mut self
) -> HOST_SLC0HOST_TX_START_INT_ENA_W<'_>

Bit 15

pub fn host_slc0host_rx_start_int_ena(
    &mut self
) -> HOST_SLC0HOST_RX_START_INT_ENA_W<'_>

Bit 14

pub fn host_slc0host_rx_eof_int_ena(
    &mut self
) -> HOST_SLC0HOST_RX_EOF_INT_ENA_W<'_>

Bit 13

pub fn host_slc0host_rx_sof_int_ena(
    &mut self
) -> HOST_SLC0HOST_RX_SOF_INT_ENA_W<'_>

Bit 12

pub fn host_slc0_token1_0to1_int_ena(
    &mut self
) -> HOST_SLC0_TOKEN1_0TO1_INT_ENA_W<'_>

Bit 11

pub fn host_slc0_token0_0to1_int_ena(
    &mut self
) -> HOST_SLC0_TOKEN0_0TO1_INT_ENA_W<'_>

Bit 10

pub fn host_slc0_token1_1to0_int_ena(
    &mut self
) -> HOST_SLC0_TOKEN1_1TO0_INT_ENA_W<'_>

Bit 9

pub fn host_slc0_token0_1to0_int_ena(
    &mut self
) -> HOST_SLC0_TOKEN0_1TO0_INT_ENA_W<'_>

Bit 8

pub fn host_slc0_tohost_bit7_int_ena(
    &mut self
) -> HOST_SLC0_TOHOST_BIT7_INT_ENA_W<'_>

Bit 7

pub fn host_slc0_tohost_bit6_int_ena(
    &mut self
) -> HOST_SLC0_TOHOST_BIT6_INT_ENA_W<'_>

Bit 6

pub fn host_slc0_tohost_bit5_int_ena(
    &mut self
) -> HOST_SLC0_TOHOST_BIT5_INT_ENA_W<'_>

Bit 5

pub fn host_slc0_tohost_bit4_int_ena(
    &mut self
) -> HOST_SLC0_TOHOST_BIT4_INT_ENA_W<'_>

Bit 4

pub fn host_slc0_tohost_bit3_int_ena(
    &mut self
) -> HOST_SLC0_TOHOST_BIT3_INT_ENA_W<'_>

Bit 3

pub fn host_slc0_tohost_bit2_int_ena(
    &mut self
) -> HOST_SLC0_TOHOST_BIT2_INT_ENA_W<'_>

Bit 2

pub fn host_slc0_tohost_bit1_int_ena(
    &mut self
) -> HOST_SLC0_TOHOST_BIT1_INT_ENA_W<'_>

Bit 1

pub fn host_slc0_tohost_bit0_int_ena(
    &mut self
) -> HOST_SLC0_TOHOST_BIT0_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLC1HOST_INT_ENA>>

pub fn host_slc1_bt_rx_new_packet_int_ena(
    &mut self
) -> HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_W<'_>

Bit 25

pub fn host_slc1_host_rd_retry_int_ena(
    &mut self
) -> HOST_SLC1_HOST_RD_RETRY_INT_ENA_W<'_>

Bit 24

pub fn host_slc1_wifi_rx_new_packet_int_ena(
    &mut self
) -> HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_W<'_>

Bit 23

pub fn host_slc1_ext_bit3_int_ena(&mut self) -> HOST_SLC1_EXT_BIT3_INT_ENA_W<'_>

Bit 22

pub fn host_slc1_ext_bit2_int_ena(&mut self) -> HOST_SLC1_EXT_BIT2_INT_ENA_W<'_>

Bit 21

pub fn host_slc1_ext_bit1_int_ena(&mut self) -> HOST_SLC1_EXT_BIT1_INT_ENA_W<'_>

Bit 20

pub fn host_slc1_ext_bit0_int_ena(&mut self) -> HOST_SLC1_EXT_BIT0_INT_ENA_W<'_>

Bit 19

pub fn host_slc1_rx_pf_valid_int_ena(
    &mut self
) -> HOST_SLC1_RX_PF_VALID_INT_ENA_W<'_>

Bit 18

pub fn host_slc1_tx_ovf_int_ena(&mut self) -> HOST_SLC1_TX_OVF_INT_ENA_W<'_>

Bit 17

pub fn host_slc1_rx_udf_int_ena(&mut self) -> HOST_SLC1_RX_UDF_INT_ENA_W<'_>

Bit 16

pub fn host_slc1host_tx_start_int_ena(
    &mut self
) -> HOST_SLC1HOST_TX_START_INT_ENA_W<'_>

Bit 15

pub fn host_slc1host_rx_start_int_ena(
    &mut self
) -> HOST_SLC1HOST_RX_START_INT_ENA_W<'_>

Bit 14

pub fn host_slc1host_rx_eof_int_ena(
    &mut self
) -> HOST_SLC1HOST_RX_EOF_INT_ENA_W<'_>

Bit 13

pub fn host_slc1host_rx_sof_int_ena(
    &mut self
) -> HOST_SLC1HOST_RX_SOF_INT_ENA_W<'_>

Bit 12

pub fn host_slc1_token1_0to1_int_ena(
    &mut self
) -> HOST_SLC1_TOKEN1_0TO1_INT_ENA_W<'_>

Bit 11

pub fn host_slc1_token0_0to1_int_ena(
    &mut self
) -> HOST_SLC1_TOKEN0_0TO1_INT_ENA_W<'_>

Bit 10

pub fn host_slc1_token1_1to0_int_ena(
    &mut self
) -> HOST_SLC1_TOKEN1_1TO0_INT_ENA_W<'_>

Bit 9

pub fn host_slc1_token0_1to0_int_ena(
    &mut self
) -> HOST_SLC1_TOKEN0_1TO0_INT_ENA_W<'_>

Bit 8

pub fn host_slc1_tohost_bit7_int_ena(
    &mut self
) -> HOST_SLC1_TOHOST_BIT7_INT_ENA_W<'_>

Bit 7

pub fn host_slc1_tohost_bit6_int_ena(
    &mut self
) -> HOST_SLC1_TOHOST_BIT6_INT_ENA_W<'_>

Bit 6

pub fn host_slc1_tohost_bit5_int_ena(
    &mut self
) -> HOST_SLC1_TOHOST_BIT5_INT_ENA_W<'_>

Bit 5

pub fn host_slc1_tohost_bit4_int_ena(
    &mut self
) -> HOST_SLC1_TOHOST_BIT4_INT_ENA_W<'_>

Bit 4

pub fn host_slc1_tohost_bit3_int_ena(
    &mut self
) -> HOST_SLC1_TOHOST_BIT3_INT_ENA_W<'_>

Bit 3

pub fn host_slc1_tohost_bit2_int_ena(
    &mut self
) -> HOST_SLC1_TOHOST_BIT2_INT_ENA_W<'_>

Bit 2

pub fn host_slc1_tohost_bit1_int_ena(
    &mut self
) -> HOST_SLC1_TOHOST_BIT1_INT_ENA_W<'_>

Bit 1

pub fn host_slc1_tohost_bit0_int_ena(
    &mut self
) -> HOST_SLC1_TOHOST_BIT0_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLC0HOST_RX_INFOR>>

pub fn host_slc0host_rx_infor(&mut self) -> HOST_SLC0HOST_RX_INFOR_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HOST_SLC1HOST_RX_INFOR>>

pub fn host_slc1host_rx_infor(&mut self) -> HOST_SLC1HOST_RX_INFOR_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HOST_SLC0HOST_LEN_WD>>

pub fn host_slc0host_len_wd(&mut self) -> HOST_SLC0HOST_LEN_WD_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _HOST_SLC_APBWIN_WDATA>>

pub fn host_slc_apbwin_wdata(&mut self) -> HOST_SLC_APBWIN_WDATA_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _HOST_SLC_APBWIN_CONF>>

pub fn host_slc_apbwin_start(&mut self) -> HOST_SLC_APBWIN_START_W<'_>

Bit 29

pub fn host_slc_apbwin_wr(&mut self) -> HOST_SLC_APBWIN_WR_W<'_>

Bit 28

pub fn host_slc_apbwin_addr(&mut self) -> HOST_SLC_APBWIN_ADDR_W<'_>

Bits 0:27

impl W<u32, Reg<u32, _HOST_SLC_APBWIN_RDATA>>

pub fn host_slc_apbwin_rdata(&mut self) -> HOST_SLC_APBWIN_RDATA_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _HOST_SLCHOST_RDCLR0>>

pub fn host_slchost_slc0_bit6_clraddr(
    &mut self
) -> HOST_SLCHOST_SLC0_BIT6_CLRADDR_W<'_>

Bits 9:17

pub fn host_slchost_slc0_bit7_clraddr(
    &mut self
) -> HOST_SLCHOST_SLC0_BIT7_CLRADDR_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _HOST_SLCHOST_RDCLR1>>

pub fn host_slchost_slc1_bit6_clraddr(
    &mut self
) -> HOST_SLCHOST_SLC1_BIT6_CLRADDR_W<'_>

Bits 9:17

pub fn host_slchost_slc1_bit7_clraddr(
    &mut self
) -> HOST_SLCHOST_SLC1_BIT7_CLRADDR_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _HOST_SLC0HOST_INT_ENA1>>

pub fn host_gpio_sdio_int_ena1(&mut self) -> HOST_GPIO_SDIO_INT_ENA1_W<'_>

Bit 25

pub fn host_slc0_host_rd_retry_int_ena1(
    &mut self
) -> HOST_SLC0_HOST_RD_RETRY_INT_ENA1_W<'_>

Bit 24

pub fn host_slc0_rx_new_packet_int_ena1(
    &mut self
) -> HOST_SLC0_RX_NEW_PACKET_INT_ENA1_W<'_>

Bit 23

pub fn host_slc0_ext_bit3_int_ena1(
    &mut self
) -> HOST_SLC0_EXT_BIT3_INT_ENA1_W<'_>

Bit 22

pub fn host_slc0_ext_bit2_int_ena1(
    &mut self
) -> HOST_SLC0_EXT_BIT2_INT_ENA1_W<'_>

Bit 21

pub fn host_slc0_ext_bit1_int_ena1(
    &mut self
) -> HOST_SLC0_EXT_BIT1_INT_ENA1_W<'_>

Bit 20

pub fn host_slc0_ext_bit0_int_ena1(
    &mut self
) -> HOST_SLC0_EXT_BIT0_INT_ENA1_W<'_>

Bit 19

pub fn host_slc0_rx_pf_valid_int_ena1(
    &mut self
) -> HOST_SLC0_RX_PF_VALID_INT_ENA1_W<'_>

Bit 18

pub fn host_slc0_tx_ovf_int_ena1(&mut self) -> HOST_SLC0_TX_OVF_INT_ENA1_W<'_>

Bit 17

pub fn host_slc0_rx_udf_int_ena1(&mut self) -> HOST_SLC0_RX_UDF_INT_ENA1_W<'_>

Bit 16

pub fn host_slc0host_tx_start_int_ena1(
    &mut self
) -> HOST_SLC0HOST_TX_START_INT_ENA1_W<'_>

Bit 15

pub fn host_slc0host_rx_start_int_ena1(
    &mut self
) -> HOST_SLC0HOST_RX_START_INT_ENA1_W<'_>

Bit 14

pub fn host_slc0host_rx_eof_int_ena1(
    &mut self
) -> HOST_SLC0HOST_RX_EOF_INT_ENA1_W<'_>

Bit 13

pub fn host_slc0host_rx_sof_int_ena1(
    &mut self
) -> HOST_SLC0HOST_RX_SOF_INT_ENA1_W<'_>

Bit 12

pub fn host_slc0_token1_0to1_int_ena1(
    &mut self
) -> HOST_SLC0_TOKEN1_0TO1_INT_ENA1_W<'_>

Bit 11

pub fn host_slc0_token0_0to1_int_ena1(
    &mut self
) -> HOST_SLC0_TOKEN0_0TO1_INT_ENA1_W<'_>

Bit 10

pub fn host_slc0_token1_1to0_int_ena1(
    &mut self
) -> HOST_SLC0_TOKEN1_1TO0_INT_ENA1_W<'_>

Bit 9

pub fn host_slc0_token0_1to0_int_ena1(
    &mut self
) -> HOST_SLC0_TOKEN0_1TO0_INT_ENA1_W<'_>

Bit 8

pub fn host_slc0_tohost_bit7_int_ena1(
    &mut self
) -> HOST_SLC0_TOHOST_BIT7_INT_ENA1_W<'_>

Bit 7

pub fn host_slc0_tohost_bit6_int_ena1(
    &mut self
) -> HOST_SLC0_TOHOST_BIT6_INT_ENA1_W<'_>

Bit 6

pub fn host_slc0_tohost_bit5_int_ena1(
    &mut self
) -> HOST_SLC0_TOHOST_BIT5_INT_ENA1_W<'_>

Bit 5

pub fn host_slc0_tohost_bit4_int_ena1(
    &mut self
) -> HOST_SLC0_TOHOST_BIT4_INT_ENA1_W<'_>

Bit 4

pub fn host_slc0_tohost_bit3_int_ena1(
    &mut self
) -> HOST_SLC0_TOHOST_BIT3_INT_ENA1_W<'_>

Bit 3

pub fn host_slc0_tohost_bit2_int_ena1(
    &mut self
) -> HOST_SLC0_TOHOST_BIT2_INT_ENA1_W<'_>

Bit 2

pub fn host_slc0_tohost_bit1_int_ena1(
    &mut self
) -> HOST_SLC0_TOHOST_BIT1_INT_ENA1_W<'_>

Bit 1

pub fn host_slc0_tohost_bit0_int_ena1(
    &mut self
) -> HOST_SLC0_TOHOST_BIT0_INT_ENA1_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLC1HOST_INT_ENA1>>

pub fn host_slc1_bt_rx_new_packet_int_ena1(
    &mut self
) -> HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_W<'_>

Bit 25

pub fn host_slc1_host_rd_retry_int_ena1(
    &mut self
) -> HOST_SLC1_HOST_RD_RETRY_INT_ENA1_W<'_>

Bit 24

pub fn host_slc1_wifi_rx_new_packet_int_ena1(
    &mut self
) -> HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_W<'_>

Bit 23

pub fn host_slc1_ext_bit3_int_ena1(
    &mut self
) -> HOST_SLC1_EXT_BIT3_INT_ENA1_W<'_>

Bit 22

pub fn host_slc1_ext_bit2_int_ena1(
    &mut self
) -> HOST_SLC1_EXT_BIT2_INT_ENA1_W<'_>

Bit 21

pub fn host_slc1_ext_bit1_int_ena1(
    &mut self
) -> HOST_SLC1_EXT_BIT1_INT_ENA1_W<'_>

Bit 20

pub fn host_slc1_ext_bit0_int_ena1(
    &mut self
) -> HOST_SLC1_EXT_BIT0_INT_ENA1_W<'_>

Bit 19

pub fn host_slc1_rx_pf_valid_int_ena1(
    &mut self
) -> HOST_SLC1_RX_PF_VALID_INT_ENA1_W<'_>

Bit 18

pub fn host_slc1_tx_ovf_int_ena1(&mut self) -> HOST_SLC1_TX_OVF_INT_ENA1_W<'_>

Bit 17

pub fn host_slc1_rx_udf_int_ena1(&mut self) -> HOST_SLC1_RX_UDF_INT_ENA1_W<'_>

Bit 16

pub fn host_slc1host_tx_start_int_ena1(
    &mut self
) -> HOST_SLC1HOST_TX_START_INT_ENA1_W<'_>

Bit 15

pub fn host_slc1host_rx_start_int_ena1(
    &mut self
) -> HOST_SLC1HOST_RX_START_INT_ENA1_W<'_>

Bit 14

pub fn host_slc1host_rx_eof_int_ena1(
    &mut self
) -> HOST_SLC1HOST_RX_EOF_INT_ENA1_W<'_>

Bit 13

pub fn host_slc1host_rx_sof_int_ena1(
    &mut self
) -> HOST_SLC1HOST_RX_SOF_INT_ENA1_W<'_>

Bit 12

pub fn host_slc1_token1_0to1_int_ena1(
    &mut self
) -> HOST_SLC1_TOKEN1_0TO1_INT_ENA1_W<'_>

Bit 11

pub fn host_slc1_token0_0to1_int_ena1(
    &mut self
) -> HOST_SLC1_TOKEN0_0TO1_INT_ENA1_W<'_>

Bit 10

pub fn host_slc1_token1_1to0_int_ena1(
    &mut self
) -> HOST_SLC1_TOKEN1_1TO0_INT_ENA1_W<'_>

Bit 9

pub fn host_slc1_token0_1to0_int_ena1(
    &mut self
) -> HOST_SLC1_TOKEN0_1TO0_INT_ENA1_W<'_>

Bit 8

pub fn host_slc1_tohost_bit7_int_ena1(
    &mut self
) -> HOST_SLC1_TOHOST_BIT7_INT_ENA1_W<'_>

Bit 7

pub fn host_slc1_tohost_bit6_int_ena1(
    &mut self
) -> HOST_SLC1_TOHOST_BIT6_INT_ENA1_W<'_>

Bit 6

pub fn host_slc1_tohost_bit5_int_ena1(
    &mut self
) -> HOST_SLC1_TOHOST_BIT5_INT_ENA1_W<'_>

Bit 5

pub fn host_slc1_tohost_bit4_int_ena1(
    &mut self
) -> HOST_SLC1_TOHOST_BIT4_INT_ENA1_W<'_>

Bit 4

pub fn host_slc1_tohost_bit3_int_ena1(
    &mut self
) -> HOST_SLC1_TOHOST_BIT3_INT_ENA1_W<'_>

Bit 3

pub fn host_slc1_tohost_bit2_int_ena1(
    &mut self
) -> HOST_SLC1_TOHOST_BIT2_INT_ENA1_W<'_>

Bit 2

pub fn host_slc1_tohost_bit1_int_ena1(
    &mut self
) -> HOST_SLC1_TOHOST_BIT1_INT_ENA1_W<'_>

Bit 1

pub fn host_slc1_tohost_bit0_int_ena1(
    &mut self
) -> HOST_SLC1_TOHOST_BIT0_INT_ENA1_W<'_>

Bit 0

impl W<u32, Reg<u32, _HOST_SLCHOSTDATE>>

pub fn host_slchost_date(&mut self) -> HOST_SLCHOST_DATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _HOST_SLCHOSTID>>

pub fn host_slchost_id(&mut self) -> HOST_SLCHOST_ID_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _HOST_SLCHOST_CONF>>

pub fn host_hspeed_con_en(&mut self) -> HOST_HSPEED_CON_EN_W<'_>

Bit 27

pub fn host_sdio_pad_pullup(&mut self) -> HOST_SDIO_PAD_PULLUP_W<'_>

Bit 26

pub fn host_sdio20_int_delay(&mut self) -> HOST_SDIO20_INT_DELAY_W<'_>

Bit 25

pub fn host_frc_quick_in(&mut self) -> HOST_FRC_QUICK_IN_W<'_>

Bits 20:24

pub fn host_frc_pos_samp(&mut self) -> HOST_FRC_POS_SAMP_W<'_>

Bits 15:19

pub fn host_frc_neg_samp(&mut self) -> HOST_FRC_NEG_SAMP_W<'_>

Bits 10:14

pub fn host_frc_sdio20(&mut self) -> HOST_FRC_SDIO20_W<'_>

Bits 5:9

pub fn host_frc_sdio11(&mut self) -> HOST_FRC_SDIO11_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _HOST_SLCHOST_INF_ST>>

pub fn host_sdio_quick_in(&mut self) -> HOST_SDIO_QUICK_IN_W<'_>

Bits 10:14

pub fn host_sdio_neg_samp(&mut self) -> HOST_SDIO_NEG_SAMP_W<'_>

Bits 5:9

pub fn host_sdio20_mode(&mut self) -> HOST_SDIO20_MODE_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _CONF0>>

pub fn slc1_token_sel(&mut self) -> SLC1_TOKEN_SEL_W<'_>

Bit 31

pub fn slc1_token_auto_clr(&mut self) -> SLC1_TOKEN_AUTO_CLR_W<'_>

Bit 30

pub fn slc1_txdata_burst_en(&mut self) -> SLC1_TXDATA_BURST_EN_W<'_>

Bit 29

pub fn slc1_txdscr_burst_en(&mut self) -> SLC1_TXDSCR_BURST_EN_W<'_>

Bit 28

pub fn slc1_txlink_auto_ret(&mut self) -> SLC1_TXLINK_AUTO_RET_W<'_>

Bit 27

pub fn slc1_rxlink_auto_ret(&mut self) -> SLC1_RXLINK_AUTO_RET_W<'_>

Bit 26

pub fn slc1_rxdata_burst_en(&mut self) -> SLC1_RXDATA_BURST_EN_W<'_>

Bit 25

pub fn slc1_rxdscr_burst_en(&mut self) -> SLC1_RXDSCR_BURST_EN_W<'_>

Bit 24

pub fn slc1_rx_no_restart_clr(&mut self) -> SLC1_RX_NO_RESTART_CLR_W<'_>

Bit 23

pub fn slc1_rx_auto_wrback(&mut self) -> SLC1_RX_AUTO_WRBACK_W<'_>

Bit 22

pub fn slc1_rx_loop_test(&mut self) -> SLC1_RX_LOOP_TEST_W<'_>

Bit 21

pub fn slc1_tx_loop_test(&mut self) -> SLC1_TX_LOOP_TEST_W<'_>

Bit 20

pub fn slc1_wr_retry_mask_en(&mut self) -> SLC1_WR_RETRY_MASK_EN_W<'_>

Bit 19

pub fn slc0_wr_retry_mask_en(&mut self) -> SLC0_WR_RETRY_MASK_EN_W<'_>

Bit 18

pub fn slc1_rx_rst(&mut self) -> SLC1_RX_RST_W<'_>

Bit 17

pub fn slc1_tx_rst(&mut self) -> SLC1_TX_RST_W<'_>

Bit 16

pub fn slc0_token_sel(&mut self) -> SLC0_TOKEN_SEL_W<'_>

Bit 15

pub fn slc0_token_auto_clr(&mut self) -> SLC0_TOKEN_AUTO_CLR_W<'_>

Bit 14

pub fn slc0_txdata_burst_en(&mut self) -> SLC0_TXDATA_BURST_EN_W<'_>

Bit 13

pub fn slc0_txdscr_burst_en(&mut self) -> SLC0_TXDSCR_BURST_EN_W<'_>

Bit 12

pub fn slc0_txlink_auto_ret(&mut self) -> SLC0_TXLINK_AUTO_RET_W<'_>

Bit 11

pub fn slc0_rxlink_auto_ret(&mut self) -> SLC0_RXLINK_AUTO_RET_W<'_>

Bit 10

pub fn slc0_rxdata_burst_en(&mut self) -> SLC0_RXDATA_BURST_EN_W<'_>

Bit 9

pub fn slc0_rxdscr_burst_en(&mut self) -> SLC0_RXDSCR_BURST_EN_W<'_>

Bit 8

pub fn slc0_rx_no_restart_clr(&mut self) -> SLC0_RX_NO_RESTART_CLR_W<'_>

Bit 7

pub fn slc0_rx_auto_wrback(&mut self) -> SLC0_RX_AUTO_WRBACK_W<'_>

Bit 6

pub fn slc0_rx_loop_test(&mut self) -> SLC0_RX_LOOP_TEST_W<'_>

Bit 5

pub fn slc0_tx_loop_test(&mut self) -> SLC0_TX_LOOP_TEST_W<'_>

Bit 4

pub fn ahbm_rst(&mut self) -> AHBM_RST_W<'_>

Bit 3

pub fn ahbm_fifo_rst(&mut self) -> AHBM_FIFO_RST_W<'_>

Bit 2

pub fn slc0_rx_rst(&mut self) -> SLC0_RX_RST_W<'_>

Bit 1

pub fn slc0_tx_rst(&mut self) -> SLC0_TX_RST_W<'_>

Bit 0

impl W<u32, Reg<u32, __0INT_RAW>>

pub fn slc0_rx_quick_eof_int_raw(&mut self) -> SLC0_RX_QUICK_EOF_INT_RAW_W<'_>

Bit 26

pub fn cmd_dtc_int_raw(&mut self) -> CMD_DTC_INT_RAW_W<'_>

Bit 25

pub fn slc0_tx_err_eof_int_raw(&mut self) -> SLC0_TX_ERR_EOF_INT_RAW_W<'_>

Bit 24

pub fn slc0_wr_retry_done_int_raw(&mut self) -> SLC0_WR_RETRY_DONE_INT_RAW_W<'_>

Bit 23

pub fn slc0_host_rd_ack_int_raw(&mut self) -> SLC0_HOST_RD_ACK_INT_RAW_W<'_>

Bit 22

pub fn slc0_tx_dscr_empty_int_raw(&mut self) -> SLC0_TX_DSCR_EMPTY_INT_RAW_W<'_>

Bit 21

pub fn slc0_rx_dscr_err_int_raw(&mut self) -> SLC0_RX_DSCR_ERR_INT_RAW_W<'_>

Bit 20

pub fn slc0_tx_dscr_err_int_raw(&mut self) -> SLC0_TX_DSCR_ERR_INT_RAW_W<'_>

Bit 19

pub fn slc0_tohost_int_raw(&mut self) -> SLC0_TOHOST_INT_RAW_W<'_>

Bit 18

pub fn slc0_rx_eof_int_raw(&mut self) -> SLC0_RX_EOF_INT_RAW_W<'_>

Bit 17

pub fn slc0_rx_done_int_raw(&mut self) -> SLC0_RX_DONE_INT_RAW_W<'_>

Bit 16

pub fn slc0_tx_suc_eof_int_raw(&mut self) -> SLC0_TX_SUC_EOF_INT_RAW_W<'_>

Bit 15

pub fn slc0_tx_done_int_raw(&mut self) -> SLC0_TX_DONE_INT_RAW_W<'_>

Bit 14

pub fn slc0_token1_1to0_int_raw(&mut self) -> SLC0_TOKEN1_1TO0_INT_RAW_W<'_>

Bit 13

pub fn slc0_token0_1to0_int_raw(&mut self) -> SLC0_TOKEN0_1TO0_INT_RAW_W<'_>

Bit 12

pub fn slc0_tx_ovf_int_raw(&mut self) -> SLC0_TX_OVF_INT_RAW_W<'_>

Bit 11

pub fn slc0_rx_udf_int_raw(&mut self) -> SLC0_RX_UDF_INT_RAW_W<'_>

Bit 10

pub fn slc0_tx_start_int_raw(&mut self) -> SLC0_TX_START_INT_RAW_W<'_>

Bit 9

pub fn slc0_rx_start_int_raw(&mut self) -> SLC0_RX_START_INT_RAW_W<'_>

Bit 8

pub fn frhost_bit7_int_raw(&mut self) -> FRHOST_BIT7_INT_RAW_W<'_>

Bit 7

pub fn frhost_bit6_int_raw(&mut self) -> FRHOST_BIT6_INT_RAW_W<'_>

Bit 6

pub fn frhost_bit5_int_raw(&mut self) -> FRHOST_BIT5_INT_RAW_W<'_>

Bit 5

pub fn frhost_bit4_int_raw(&mut self) -> FRHOST_BIT4_INT_RAW_W<'_>

Bit 4

pub fn frhost_bit3_int_raw(&mut self) -> FRHOST_BIT3_INT_RAW_W<'_>

Bit 3

pub fn frhost_bit2_int_raw(&mut self) -> FRHOST_BIT2_INT_RAW_W<'_>

Bit 2

pub fn frhost_bit1_int_raw(&mut self) -> FRHOST_BIT1_INT_RAW_W<'_>

Bit 1

pub fn frhost_bit0_int_raw(&mut self) -> FRHOST_BIT0_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, __0INT_ST>>

pub fn slc0_rx_quick_eof_int_st(&mut self) -> SLC0_RX_QUICK_EOF_INT_ST_W<'_>

Bit 26

pub fn cmd_dtc_int_st(&mut self) -> CMD_DTC_INT_ST_W<'_>

Bit 25

pub fn slc0_tx_err_eof_int_st(&mut self) -> SLC0_TX_ERR_EOF_INT_ST_W<'_>

Bit 24

pub fn slc0_wr_retry_done_int_st(&mut self) -> SLC0_WR_RETRY_DONE_INT_ST_W<'_>

Bit 23

pub fn slc0_host_rd_ack_int_st(&mut self) -> SLC0_HOST_RD_ACK_INT_ST_W<'_>

Bit 22

pub fn slc0_tx_dscr_empty_int_st(&mut self) -> SLC0_TX_DSCR_EMPTY_INT_ST_W<'_>

Bit 21

pub fn slc0_rx_dscr_err_int_st(&mut self) -> SLC0_RX_DSCR_ERR_INT_ST_W<'_>

Bit 20

pub fn slc0_tx_dscr_err_int_st(&mut self) -> SLC0_TX_DSCR_ERR_INT_ST_W<'_>

Bit 19

pub fn slc0_tohost_int_st(&mut self) -> SLC0_TOHOST_INT_ST_W<'_>

Bit 18

pub fn slc0_rx_eof_int_st(&mut self) -> SLC0_RX_EOF_INT_ST_W<'_>

Bit 17

pub fn slc0_rx_done_int_st(&mut self) -> SLC0_RX_DONE_INT_ST_W<'_>

Bit 16

pub fn slc0_tx_suc_eof_int_st(&mut self) -> SLC0_TX_SUC_EOF_INT_ST_W<'_>

Bit 15

pub fn slc0_tx_done_int_st(&mut self) -> SLC0_TX_DONE_INT_ST_W<'_>

Bit 14

pub fn slc0_token1_1to0_int_st(&mut self) -> SLC0_TOKEN1_1TO0_INT_ST_W<'_>

Bit 13

pub fn slc0_token0_1to0_int_st(&mut self) -> SLC0_TOKEN0_1TO0_INT_ST_W<'_>

Bit 12

pub fn slc0_tx_ovf_int_st(&mut self) -> SLC0_TX_OVF_INT_ST_W<'_>

Bit 11

pub fn slc0_rx_udf_int_st(&mut self) -> SLC0_RX_UDF_INT_ST_W<'_>

Bit 10

pub fn slc0_tx_start_int_st(&mut self) -> SLC0_TX_START_INT_ST_W<'_>

Bit 9

pub fn slc0_rx_start_int_st(&mut self) -> SLC0_RX_START_INT_ST_W<'_>

Bit 8

pub fn frhost_bit7_int_st(&mut self) -> FRHOST_BIT7_INT_ST_W<'_>

Bit 7

pub fn frhost_bit6_int_st(&mut self) -> FRHOST_BIT6_INT_ST_W<'_>

Bit 6

pub fn frhost_bit5_int_st(&mut self) -> FRHOST_BIT5_INT_ST_W<'_>

Bit 5

pub fn frhost_bit4_int_st(&mut self) -> FRHOST_BIT4_INT_ST_W<'_>

Bit 4

pub fn frhost_bit3_int_st(&mut self) -> FRHOST_BIT3_INT_ST_W<'_>

Bit 3

pub fn frhost_bit2_int_st(&mut self) -> FRHOST_BIT2_INT_ST_W<'_>

Bit 2

pub fn frhost_bit1_int_st(&mut self) -> FRHOST_BIT1_INT_ST_W<'_>

Bit 1

pub fn frhost_bit0_int_st(&mut self) -> FRHOST_BIT0_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, __0INT_ENA>>

pub fn slc0_rx_quick_eof_int_ena(&mut self) -> SLC0_RX_QUICK_EOF_INT_ENA_W<'_>

Bit 26

pub fn cmd_dtc_int_ena(&mut self) -> CMD_DTC_INT_ENA_W<'_>

Bit 25

pub fn slc0_tx_err_eof_int_ena(&mut self) -> SLC0_TX_ERR_EOF_INT_ENA_W<'_>

Bit 24

pub fn slc0_wr_retry_done_int_ena(&mut self) -> SLC0_WR_RETRY_DONE_INT_ENA_W<'_>

Bit 23

pub fn slc0_host_rd_ack_int_ena(&mut self) -> SLC0_HOST_RD_ACK_INT_ENA_W<'_>

Bit 22

pub fn slc0_tx_dscr_empty_int_ena(&mut self) -> SLC0_TX_DSCR_EMPTY_INT_ENA_W<'_>

Bit 21

pub fn slc0_rx_dscr_err_int_ena(&mut self) -> SLC0_RX_DSCR_ERR_INT_ENA_W<'_>

Bit 20

pub fn slc0_tx_dscr_err_int_ena(&mut self) -> SLC0_TX_DSCR_ERR_INT_ENA_W<'_>

Bit 19

pub fn slc0_tohost_int_ena(&mut self) -> SLC0_TOHOST_INT_ENA_W<'_>

Bit 18

pub fn slc0_rx_eof_int_ena(&mut self) -> SLC0_RX_EOF_INT_ENA_W<'_>

Bit 17

pub fn slc0_rx_done_int_ena(&mut self) -> SLC0_RX_DONE_INT_ENA_W<'_>

Bit 16

pub fn slc0_tx_suc_eof_int_ena(&mut self) -> SLC0_TX_SUC_EOF_INT_ENA_W<'_>

Bit 15

pub fn slc0_tx_done_int_ena(&mut self) -> SLC0_TX_DONE_INT_ENA_W<'_>

Bit 14

pub fn slc0_token1_1to0_int_ena(&mut self) -> SLC0_TOKEN1_1TO0_INT_ENA_W<'_>

Bit 13

pub fn slc0_token0_1to0_int_ena(&mut self) -> SLC0_TOKEN0_1TO0_INT_ENA_W<'_>

Bit 12

pub fn slc0_tx_ovf_int_ena(&mut self) -> SLC0_TX_OVF_INT_ENA_W<'_>

Bit 11

pub fn slc0_rx_udf_int_ena(&mut self) -> SLC0_RX_UDF_INT_ENA_W<'_>

Bit 10

pub fn slc0_tx_start_int_ena(&mut self) -> SLC0_TX_START_INT_ENA_W<'_>

Bit 9

pub fn slc0_rx_start_int_ena(&mut self) -> SLC0_RX_START_INT_ENA_W<'_>

Bit 8

pub fn frhost_bit7_int_ena(&mut self) -> FRHOST_BIT7_INT_ENA_W<'_>

Bit 7

pub fn frhost_bit6_int_ena(&mut self) -> FRHOST_BIT6_INT_ENA_W<'_>

Bit 6

pub fn frhost_bit5_int_ena(&mut self) -> FRHOST_BIT5_INT_ENA_W<'_>

Bit 5

pub fn frhost_bit4_int_ena(&mut self) -> FRHOST_BIT4_INT_ENA_W<'_>

Bit 4

pub fn frhost_bit3_int_ena(&mut self) -> FRHOST_BIT3_INT_ENA_W<'_>

Bit 3

pub fn frhost_bit2_int_ena(&mut self) -> FRHOST_BIT2_INT_ENA_W<'_>

Bit 2

pub fn frhost_bit1_int_ena(&mut self) -> FRHOST_BIT1_INT_ENA_W<'_>

Bit 1

pub fn frhost_bit0_int_ena(&mut self) -> FRHOST_BIT0_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, __0INT_CLR>>

pub fn slc0_rx_quick_eof_int_clr(&mut self) -> SLC0_RX_QUICK_EOF_INT_CLR_W<'_>

Bit 26

pub fn cmd_dtc_int_clr(&mut self) -> CMD_DTC_INT_CLR_W<'_>

Bit 25

pub fn slc0_tx_err_eof_int_clr(&mut self) -> SLC0_TX_ERR_EOF_INT_CLR_W<'_>

Bit 24

pub fn slc0_wr_retry_done_int_clr(&mut self) -> SLC0_WR_RETRY_DONE_INT_CLR_W<'_>

Bit 23

pub fn slc0_host_rd_ack_int_clr(&mut self) -> SLC0_HOST_RD_ACK_INT_CLR_W<'_>

Bit 22

pub fn slc0_tx_dscr_empty_int_clr(&mut self) -> SLC0_TX_DSCR_EMPTY_INT_CLR_W<'_>

Bit 21

pub fn slc0_rx_dscr_err_int_clr(&mut self) -> SLC0_RX_DSCR_ERR_INT_CLR_W<'_>

Bit 20

pub fn slc0_tx_dscr_err_int_clr(&mut self) -> SLC0_TX_DSCR_ERR_INT_CLR_W<'_>

Bit 19

pub fn slc0_tohost_int_clr(&mut self) -> SLC0_TOHOST_INT_CLR_W<'_>

Bit 18

pub fn slc0_rx_eof_int_clr(&mut self) -> SLC0_RX_EOF_INT_CLR_W<'_>

Bit 17

pub fn slc0_rx_done_int_clr(&mut self) -> SLC0_RX_DONE_INT_CLR_W<'_>

Bit 16

pub fn slc0_tx_suc_eof_int_clr(&mut self) -> SLC0_TX_SUC_EOF_INT_CLR_W<'_>

Bit 15

pub fn slc0_tx_done_int_clr(&mut self) -> SLC0_TX_DONE_INT_CLR_W<'_>

Bit 14

pub fn slc0_token1_1to0_int_clr(&mut self) -> SLC0_TOKEN1_1TO0_INT_CLR_W<'_>

Bit 13

pub fn slc0_token0_1to0_int_clr(&mut self) -> SLC0_TOKEN0_1TO0_INT_CLR_W<'_>

Bit 12

pub fn slc0_tx_ovf_int_clr(&mut self) -> SLC0_TX_OVF_INT_CLR_W<'_>

Bit 11

pub fn slc0_rx_udf_int_clr(&mut self) -> SLC0_RX_UDF_INT_CLR_W<'_>

Bit 10

pub fn slc0_tx_start_int_clr(&mut self) -> SLC0_TX_START_INT_CLR_W<'_>

Bit 9

pub fn slc0_rx_start_int_clr(&mut self) -> SLC0_RX_START_INT_CLR_W<'_>

Bit 8

pub fn frhost_bit7_int_clr(&mut self) -> FRHOST_BIT7_INT_CLR_W<'_>

Bit 7

pub fn frhost_bit6_int_clr(&mut self) -> FRHOST_BIT6_INT_CLR_W<'_>

Bit 6

pub fn frhost_bit5_int_clr(&mut self) -> FRHOST_BIT5_INT_CLR_W<'_>

Bit 5

pub fn frhost_bit4_int_clr(&mut self) -> FRHOST_BIT4_INT_CLR_W<'_>

Bit 4

pub fn frhost_bit3_int_clr(&mut self) -> FRHOST_BIT3_INT_CLR_W<'_>

Bit 3

pub fn frhost_bit2_int_clr(&mut self) -> FRHOST_BIT2_INT_CLR_W<'_>

Bit 2

pub fn frhost_bit1_int_clr(&mut self) -> FRHOST_BIT1_INT_CLR_W<'_>

Bit 1

pub fn frhost_bit0_int_clr(&mut self) -> FRHOST_BIT0_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, __1INT_RAW>>

pub fn slc1_tx_err_eof_int_raw(&mut self) -> SLC1_TX_ERR_EOF_INT_RAW_W<'_>

Bit 24

pub fn slc1_wr_retry_done_int_raw(&mut self) -> SLC1_WR_RETRY_DONE_INT_RAW_W<'_>

Bit 23

pub fn slc1_host_rd_ack_int_raw(&mut self) -> SLC1_HOST_RD_ACK_INT_RAW_W<'_>

Bit 22

pub fn slc1_tx_dscr_empty_int_raw(&mut self) -> SLC1_TX_DSCR_EMPTY_INT_RAW_W<'_>

Bit 21

pub fn slc1_rx_dscr_err_int_raw(&mut self) -> SLC1_RX_DSCR_ERR_INT_RAW_W<'_>

Bit 20

pub fn slc1_tx_dscr_err_int_raw(&mut self) -> SLC1_TX_DSCR_ERR_INT_RAW_W<'_>

Bit 19

pub fn slc1_tohost_int_raw(&mut self) -> SLC1_TOHOST_INT_RAW_W<'_>

Bit 18

pub fn slc1_rx_eof_int_raw(&mut self) -> SLC1_RX_EOF_INT_RAW_W<'_>

Bit 17

pub fn slc1_rx_done_int_raw(&mut self) -> SLC1_RX_DONE_INT_RAW_W<'_>

Bit 16

pub fn slc1_tx_suc_eof_int_raw(&mut self) -> SLC1_TX_SUC_EOF_INT_RAW_W<'_>

Bit 15

pub fn slc1_tx_done_int_raw(&mut self) -> SLC1_TX_DONE_INT_RAW_W<'_>

Bit 14

pub fn slc1_token1_1to0_int_raw(&mut self) -> SLC1_TOKEN1_1TO0_INT_RAW_W<'_>

Bit 13

pub fn slc1_token0_1to0_int_raw(&mut self) -> SLC1_TOKEN0_1TO0_INT_RAW_W<'_>

Bit 12

pub fn slc1_tx_ovf_int_raw(&mut self) -> SLC1_TX_OVF_INT_RAW_W<'_>

Bit 11

pub fn slc1_rx_udf_int_raw(&mut self) -> SLC1_RX_UDF_INT_RAW_W<'_>

Bit 10

pub fn slc1_tx_start_int_raw(&mut self) -> SLC1_TX_START_INT_RAW_W<'_>

Bit 9

pub fn slc1_rx_start_int_raw(&mut self) -> SLC1_RX_START_INT_RAW_W<'_>

Bit 8

pub fn frhost_bit15_int_raw(&mut self) -> FRHOST_BIT15_INT_RAW_W<'_>

Bit 7

pub fn frhost_bit14_int_raw(&mut self) -> FRHOST_BIT14_INT_RAW_W<'_>

Bit 6

pub fn frhost_bit13_int_raw(&mut self) -> FRHOST_BIT13_INT_RAW_W<'_>

Bit 5

pub fn frhost_bit12_int_raw(&mut self) -> FRHOST_BIT12_INT_RAW_W<'_>

Bit 4

pub fn frhost_bit11_int_raw(&mut self) -> FRHOST_BIT11_INT_RAW_W<'_>

Bit 3

pub fn frhost_bit10_int_raw(&mut self) -> FRHOST_BIT10_INT_RAW_W<'_>

Bit 2

pub fn frhost_bit9_int_raw(&mut self) -> FRHOST_BIT9_INT_RAW_W<'_>

Bit 1

pub fn frhost_bit8_int_raw(&mut self) -> FRHOST_BIT8_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, __1INT_ST>>

pub fn slc1_tx_err_eof_int_st(&mut self) -> SLC1_TX_ERR_EOF_INT_ST_W<'_>

Bit 24

pub fn slc1_wr_retry_done_int_st(&mut self) -> SLC1_WR_RETRY_DONE_INT_ST_W<'_>

Bit 23

pub fn slc1_host_rd_ack_int_st(&mut self) -> SLC1_HOST_RD_ACK_INT_ST_W<'_>

Bit 22

pub fn slc1_tx_dscr_empty_int_st(&mut self) -> SLC1_TX_DSCR_EMPTY_INT_ST_W<'_>

Bit 21

pub fn slc1_rx_dscr_err_int_st(&mut self) -> SLC1_RX_DSCR_ERR_INT_ST_W<'_>

Bit 20

pub fn slc1_tx_dscr_err_int_st(&mut self) -> SLC1_TX_DSCR_ERR_INT_ST_W<'_>

Bit 19

pub fn slc1_tohost_int_st(&mut self) -> SLC1_TOHOST_INT_ST_W<'_>

Bit 18

pub fn slc1_rx_eof_int_st(&mut self) -> SLC1_RX_EOF_INT_ST_W<'_>

Bit 17

pub fn slc1_rx_done_int_st(&mut self) -> SLC1_RX_DONE_INT_ST_W<'_>

Bit 16

pub fn slc1_tx_suc_eof_int_st(&mut self) -> SLC1_TX_SUC_EOF_INT_ST_W<'_>

Bit 15

pub fn slc1_tx_done_int_st(&mut self) -> SLC1_TX_DONE_INT_ST_W<'_>

Bit 14

pub fn slc1_token1_1to0_int_st(&mut self) -> SLC1_TOKEN1_1TO0_INT_ST_W<'_>

Bit 13

pub fn slc1_token0_1to0_int_st(&mut self) -> SLC1_TOKEN0_1TO0_INT_ST_W<'_>

Bit 12

pub fn slc1_tx_ovf_int_st(&mut self) -> SLC1_TX_OVF_INT_ST_W<'_>

Bit 11

pub fn slc1_rx_udf_int_st(&mut self) -> SLC1_RX_UDF_INT_ST_W<'_>

Bit 10

pub fn slc1_tx_start_int_st(&mut self) -> SLC1_TX_START_INT_ST_W<'_>

Bit 9

pub fn slc1_rx_start_int_st(&mut self) -> SLC1_RX_START_INT_ST_W<'_>

Bit 8

pub fn frhost_bit15_int_st(&mut self) -> FRHOST_BIT15_INT_ST_W<'_>

Bit 7

pub fn frhost_bit14_int_st(&mut self) -> FRHOST_BIT14_INT_ST_W<'_>

Bit 6

pub fn frhost_bit13_int_st(&mut self) -> FRHOST_BIT13_INT_ST_W<'_>

Bit 5

pub fn frhost_bit12_int_st(&mut self) -> FRHOST_BIT12_INT_ST_W<'_>

Bit 4

pub fn frhost_bit11_int_st(&mut self) -> FRHOST_BIT11_INT_ST_W<'_>

Bit 3

pub fn frhost_bit10_int_st(&mut self) -> FRHOST_BIT10_INT_ST_W<'_>

Bit 2

pub fn frhost_bit9_int_st(&mut self) -> FRHOST_BIT9_INT_ST_W<'_>

Bit 1

pub fn frhost_bit8_int_st(&mut self) -> FRHOST_BIT8_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, __1INT_ENA>>

pub fn slc1_tx_err_eof_int_ena(&mut self) -> SLC1_TX_ERR_EOF_INT_ENA_W<'_>

Bit 24

pub fn slc1_wr_retry_done_int_ena(&mut self) -> SLC1_WR_RETRY_DONE_INT_ENA_W<'_>

Bit 23

pub fn slc1_host_rd_ack_int_ena(&mut self) -> SLC1_HOST_RD_ACK_INT_ENA_W<'_>

Bit 22

pub fn slc1_tx_dscr_empty_int_ena(&mut self) -> SLC1_TX_DSCR_EMPTY_INT_ENA_W<'_>

Bit 21

pub fn slc1_rx_dscr_err_int_ena(&mut self) -> SLC1_RX_DSCR_ERR_INT_ENA_W<'_>

Bit 20

pub fn slc1_tx_dscr_err_int_ena(&mut self) -> SLC1_TX_DSCR_ERR_INT_ENA_W<'_>

Bit 19

pub fn slc1_tohost_int_ena(&mut self) -> SLC1_TOHOST_INT_ENA_W<'_>

Bit 18

pub fn slc1_rx_eof_int_ena(&mut self) -> SLC1_RX_EOF_INT_ENA_W<'_>

Bit 17

pub fn slc1_rx_done_int_ena(&mut self) -> SLC1_RX_DONE_INT_ENA_W<'_>

Bit 16

pub fn slc1_tx_suc_eof_int_ena(&mut self) -> SLC1_TX_SUC_EOF_INT_ENA_W<'_>

Bit 15

pub fn slc1_tx_done_int_ena(&mut self) -> SLC1_TX_DONE_INT_ENA_W<'_>

Bit 14

pub fn slc1_token1_1to0_int_ena(&mut self) -> SLC1_TOKEN1_1TO0_INT_ENA_W<'_>

Bit 13

pub fn slc1_token0_1to0_int_ena(&mut self) -> SLC1_TOKEN0_1TO0_INT_ENA_W<'_>

Bit 12

pub fn slc1_tx_ovf_int_ena(&mut self) -> SLC1_TX_OVF_INT_ENA_W<'_>

Bit 11

pub fn slc1_rx_udf_int_ena(&mut self) -> SLC1_RX_UDF_INT_ENA_W<'_>

Bit 10

pub fn slc1_tx_start_int_ena(&mut self) -> SLC1_TX_START_INT_ENA_W<'_>

Bit 9

pub fn slc1_rx_start_int_ena(&mut self) -> SLC1_RX_START_INT_ENA_W<'_>

Bit 8

pub fn frhost_bit15_int_ena(&mut self) -> FRHOST_BIT15_INT_ENA_W<'_>

Bit 7

pub fn frhost_bit14_int_ena(&mut self) -> FRHOST_BIT14_INT_ENA_W<'_>

Bit 6

pub fn frhost_bit13_int_ena(&mut self) -> FRHOST_BIT13_INT_ENA_W<'_>

Bit 5

pub fn frhost_bit12_int_ena(&mut self) -> FRHOST_BIT12_INT_ENA_W<'_>

Bit 4

pub fn frhost_bit11_int_ena(&mut self) -> FRHOST_BIT11_INT_ENA_W<'_>

Bit 3

pub fn frhost_bit10_int_ena(&mut self) -> FRHOST_BIT10_INT_ENA_W<'_>

Bit 2

pub fn frhost_bit9_int_ena(&mut self) -> FRHOST_BIT9_INT_ENA_W<'_>

Bit 1

pub fn frhost_bit8_int_ena(&mut self) -> FRHOST_BIT8_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, __1INT_CLR>>

pub fn slc1_tx_err_eof_int_clr(&mut self) -> SLC1_TX_ERR_EOF_INT_CLR_W<'_>

Bit 24

pub fn slc1_wr_retry_done_int_clr(&mut self) -> SLC1_WR_RETRY_DONE_INT_CLR_W<'_>

Bit 23

pub fn slc1_host_rd_ack_int_clr(&mut self) -> SLC1_HOST_RD_ACK_INT_CLR_W<'_>

Bit 22

pub fn slc1_tx_dscr_empty_int_clr(&mut self) -> SLC1_TX_DSCR_EMPTY_INT_CLR_W<'_>

Bit 21

pub fn slc1_rx_dscr_err_int_clr(&mut self) -> SLC1_RX_DSCR_ERR_INT_CLR_W<'_>

Bit 20

pub fn slc1_tx_dscr_err_int_clr(&mut self) -> SLC1_TX_DSCR_ERR_INT_CLR_W<'_>

Bit 19

pub fn slc1_tohost_int_clr(&mut self) -> SLC1_TOHOST_INT_CLR_W<'_>

Bit 18

pub fn slc1_rx_eof_int_clr(&mut self) -> SLC1_RX_EOF_INT_CLR_W<'_>

Bit 17

pub fn slc1_rx_done_int_clr(&mut self) -> SLC1_RX_DONE_INT_CLR_W<'_>

Bit 16

pub fn slc1_tx_suc_eof_int_clr(&mut self) -> SLC1_TX_SUC_EOF_INT_CLR_W<'_>

Bit 15

pub fn slc1_tx_done_int_clr(&mut self) -> SLC1_TX_DONE_INT_CLR_W<'_>

Bit 14

pub fn slc1_token1_1to0_int_clr(&mut self) -> SLC1_TOKEN1_1TO0_INT_CLR_W<'_>

Bit 13

pub fn slc1_token0_1to0_int_clr(&mut self) -> SLC1_TOKEN0_1TO0_INT_CLR_W<'_>

Bit 12

pub fn slc1_tx_ovf_int_clr(&mut self) -> SLC1_TX_OVF_INT_CLR_W<'_>

Bit 11

pub fn slc1_rx_udf_int_clr(&mut self) -> SLC1_RX_UDF_INT_CLR_W<'_>

Bit 10

pub fn slc1_tx_start_int_clr(&mut self) -> SLC1_TX_START_INT_CLR_W<'_>

Bit 9

pub fn slc1_rx_start_int_clr(&mut self) -> SLC1_RX_START_INT_CLR_W<'_>

Bit 8

pub fn frhost_bit15_int_clr(&mut self) -> FRHOST_BIT15_INT_CLR_W<'_>

Bit 7

pub fn frhost_bit14_int_clr(&mut self) -> FRHOST_BIT14_INT_CLR_W<'_>

Bit 6

pub fn frhost_bit13_int_clr(&mut self) -> FRHOST_BIT13_INT_CLR_W<'_>

Bit 5

pub fn frhost_bit12_int_clr(&mut self) -> FRHOST_BIT12_INT_CLR_W<'_>

Bit 4

pub fn frhost_bit11_int_clr(&mut self) -> FRHOST_BIT11_INT_CLR_W<'_>

Bit 3

pub fn frhost_bit10_int_clr(&mut self) -> FRHOST_BIT10_INT_CLR_W<'_>

Bit 2

pub fn frhost_bit9_int_clr(&mut self) -> FRHOST_BIT9_INT_CLR_W<'_>

Bit 1

pub fn frhost_bit8_int_clr(&mut self) -> FRHOST_BIT8_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, _RX_STATUS>>

pub fn slc1_rx_empty(&mut self) -> SLC1_RX_EMPTY_W<'_>

Bit 17

pub fn slc1_rx_full(&mut self) -> SLC1_RX_FULL_W<'_>

Bit 16

pub fn slc0_rx_empty(&mut self) -> SLC0_RX_EMPTY_W<'_>

Bit 1

pub fn slc0_rx_full(&mut self) -> SLC0_RX_FULL_W<'_>

Bit 0

impl W<u32, Reg<u32, __0RXFIFO_PUSH>>

pub fn slc0_rxfifo_push(&mut self) -> SLC0_RXFIFO_PUSH_W<'_>

Bit 16

pub fn slc0_rxfifo_wdata(&mut self) -> SLC0_RXFIFO_WDATA_W<'_>

Bits 0:8

impl W<u32, Reg<u32, __1RXFIFO_PUSH>>

pub fn slc1_rxfifo_push(&mut self) -> SLC1_RXFIFO_PUSH_W<'_>

Bit 16

pub fn slc1_rxfifo_wdata(&mut self) -> SLC1_RXFIFO_WDATA_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _TX_STATUS>>

pub fn slc1_tx_empty(&mut self) -> SLC1_TX_EMPTY_W<'_>

Bit 17

pub fn slc1_tx_full(&mut self) -> SLC1_TX_FULL_W<'_>

Bit 16

pub fn slc0_tx_empty(&mut self) -> SLC0_TX_EMPTY_W<'_>

Bit 1

pub fn slc0_tx_full(&mut self) -> SLC0_TX_FULL_W<'_>

Bit 0

impl W<u32, Reg<u32, __0TXFIFO_POP>>

pub fn slc0_txfifo_pop(&mut self) -> SLC0_TXFIFO_POP_W<'_>

Bit 16

pub fn slc0_txfifo_rdata(&mut self) -> SLC0_TXFIFO_RDATA_W<'_>

Bits 0:10

impl W<u32, Reg<u32, __1TXFIFO_POP>>

pub fn slc1_txfifo_pop(&mut self) -> SLC1_TXFIFO_POP_W<'_>

Bit 16

pub fn slc1_txfifo_rdata(&mut self) -> SLC1_TXFIFO_RDATA_W<'_>

Bits 0:10

impl W<u32, Reg<u32, __0RX_LINK>>

pub fn slc0_rxlink_park(&mut self) -> SLC0_RXLINK_PARK_W<'_>

Bit 31

pub fn slc0_rxlink_restart(&mut self) -> SLC0_RXLINK_RESTART_W<'_>

Bit 30

pub fn slc0_rxlink_start(&mut self) -> SLC0_RXLINK_START_W<'_>

Bit 29

pub fn slc0_rxlink_stop(&mut self) -> SLC0_RXLINK_STOP_W<'_>

Bit 28

pub fn slc0_rxlink_addr(&mut self) -> SLC0_RXLINK_ADDR_W<'_>

Bits 0:19

impl W<u32, Reg<u32, __0TX_LINK>>

pub fn slc0_txlink_park(&mut self) -> SLC0_TXLINK_PARK_W<'_>

Bit 31

pub fn slc0_txlink_restart(&mut self) -> SLC0_TXLINK_RESTART_W<'_>

Bit 30

pub fn slc0_txlink_start(&mut self) -> SLC0_TXLINK_START_W<'_>

Bit 29

pub fn slc0_txlink_stop(&mut self) -> SLC0_TXLINK_STOP_W<'_>

Bit 28

pub fn slc0_txlink_addr(&mut self) -> SLC0_TXLINK_ADDR_W<'_>

Bits 0:19

impl W<u32, Reg<u32, __1RX_LINK>>

pub fn slc1_rxlink_park(&mut self) -> SLC1_RXLINK_PARK_W<'_>

Bit 31

pub fn slc1_rxlink_restart(&mut self) -> SLC1_RXLINK_RESTART_W<'_>

Bit 30

pub fn slc1_rxlink_start(&mut self) -> SLC1_RXLINK_START_W<'_>

Bit 29

pub fn slc1_rxlink_stop(&mut self) -> SLC1_RXLINK_STOP_W<'_>

Bit 28

pub fn slc1_bt_packet(&mut self) -> SLC1_BT_PACKET_W<'_>

Bit 20

pub fn slc1_rxlink_addr(&mut self) -> SLC1_RXLINK_ADDR_W<'_>

Bits 0:19

impl W<u32, Reg<u32, __1TX_LINK>>

pub fn slc1_txlink_park(&mut self) -> SLC1_TXLINK_PARK_W<'_>

Bit 31

pub fn slc1_txlink_restart(&mut self) -> SLC1_TXLINK_RESTART_W<'_>

Bit 30

pub fn slc1_txlink_start(&mut self) -> SLC1_TXLINK_START_W<'_>

Bit 29

pub fn slc1_txlink_stop(&mut self) -> SLC1_TXLINK_STOP_W<'_>

Bit 28

pub fn slc1_txlink_addr(&mut self) -> SLC1_TXLINK_ADDR_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _INTVEC_TOHOST>>

pub fn slc1_tohost_intvec(&mut self) -> SLC1_TOHOST_INTVEC_W<'_>

Bits 16:23

pub fn slc0_tohost_intvec(&mut self) -> SLC0_TOHOST_INTVEC_W<'_>

Bits 0:7

impl W<u32, Reg<u32, __0TOKEN0>>

pub fn slc0_token0(&mut self) -> SLC0_TOKEN0_W<'_>

Bits 16:27

pub fn slc0_token0_inc_more(&mut self) -> SLC0_TOKEN0_INC_MORE_W<'_>

Bit 14

pub fn slc0_token0_inc(&mut self) -> SLC0_TOKEN0_INC_W<'_>

Bit 13

pub fn slc0_token0_wr(&mut self) -> SLC0_TOKEN0_WR_W<'_>

Bit 12

pub fn slc0_token0_wdata(&mut self) -> SLC0_TOKEN0_WDATA_W<'_>

Bits 0:11

impl W<u32, Reg<u32, __0TOKEN1>>

pub fn slc0_token1(&mut self) -> SLC0_TOKEN1_W<'_>

Bits 16:27

pub fn slc0_token1_inc_more(&mut self) -> SLC0_TOKEN1_INC_MORE_W<'_>

Bit 14

pub fn slc0_token1_inc(&mut self) -> SLC0_TOKEN1_INC_W<'_>

Bit 13

pub fn slc0_token1_wr(&mut self) -> SLC0_TOKEN1_WR_W<'_>

Bit 12

pub fn slc0_token1_wdata(&mut self) -> SLC0_TOKEN1_WDATA_W<'_>

Bits 0:11

impl W<u32, Reg<u32, __1TOKEN0>>

pub fn slc1_token0(&mut self) -> SLC1_TOKEN0_W<'_>

Bits 16:27

pub fn slc1_token0_inc_more(&mut self) -> SLC1_TOKEN0_INC_MORE_W<'_>

Bit 14

pub fn slc1_token0_inc(&mut self) -> SLC1_TOKEN0_INC_W<'_>

Bit 13

pub fn slc1_token0_wr(&mut self) -> SLC1_TOKEN0_WR_W<'_>

Bit 12

pub fn slc1_token0_wdata(&mut self) -> SLC1_TOKEN0_WDATA_W<'_>

Bits 0:11

impl W<u32, Reg<u32, __1TOKEN1>>

pub fn slc1_token1(&mut self) -> SLC1_TOKEN1_W<'_>

Bits 16:27

pub fn slc1_token1_inc_more(&mut self) -> SLC1_TOKEN1_INC_MORE_W<'_>

Bit 14

pub fn slc1_token1_inc(&mut self) -> SLC1_TOKEN1_INC_W<'_>

Bit 13

pub fn slc1_token1_wr(&mut self) -> SLC1_TOKEN1_WR_W<'_>

Bit 12

pub fn slc1_token1_wdata(&mut self) -> SLC1_TOKEN1_WDATA_W<'_>

Bits 0:11

impl W<u32, Reg<u32, _CONF1>>

pub fn clk_en(&mut self) -> CLK_EN_W<'_>

Bit 22

pub fn slc1_rx_stitch_en(&mut self) -> SLC1_RX_STITCH_EN_W<'_>

Bit 21

pub fn slc1_tx_stitch_en(&mut self) -> SLC1_TX_STITCH_EN_W<'_>

Bit 20

pub fn host_int_level_sel(&mut self) -> HOST_INT_LEVEL_SEL_W<'_>

Bit 19

pub fn slc1_rx_check_sum_en(&mut self) -> SLC1_RX_CHECK_SUM_EN_W<'_>

Bit 18

pub fn slc1_tx_check_sum_en(&mut self) -> SLC1_TX_CHECK_SUM_EN_W<'_>

Bit 17

pub fn slc1_check_owner(&mut self) -> SLC1_CHECK_OWNER_W<'_>

Bit 16

pub fn slc0_rx_stitch_en(&mut self) -> SLC0_RX_STITCH_EN_W<'_>

Bit 6

pub fn slc0_tx_stitch_en(&mut self) -> SLC0_TX_STITCH_EN_W<'_>

Bit 5

pub fn slc0_len_auto_clr(&mut self) -> SLC0_LEN_AUTO_CLR_W<'_>

Bit 4

pub fn cmd_hold_en(&mut self) -> CMD_HOLD_EN_W<'_>

Bit 3

pub fn slc0_rx_check_sum_en(&mut self) -> SLC0_RX_CHECK_SUM_EN_W<'_>

Bit 2

pub fn slc0_tx_check_sum_en(&mut self) -> SLC0_TX_CHECK_SUM_EN_W<'_>

Bit 1

pub fn slc0_check_owner(&mut self) -> SLC0_CHECK_OWNER_W<'_>

Bit 0

impl W<u32, Reg<u32, __0_STATE0>>

pub fn slc0_state0(&mut self) -> SLC0_STATE0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_STATE1>>

pub fn slc0_state1(&mut self) -> SLC0_STATE1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __1_STATE0>>

pub fn slc1_state0(&mut self) -> SLC1_STATE0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __1_STATE1>>

pub fn slc1_state1(&mut self) -> SLC1_STATE1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BRIDGE_CONF>>

pub fn tx_push_idle_num(&mut self) -> TX_PUSH_IDLE_NUM_W<'_>

Bits 16:31

pub fn slc1_tx_dummy_mode(&mut self) -> SLC1_TX_DUMMY_MODE_W<'_>

Bit 14

pub fn hda_map_128k(&mut self) -> HDA_MAP_128K_W<'_>

Bit 13

pub fn slc0_tx_dummy_mode(&mut self) -> SLC0_TX_DUMMY_MODE_W<'_>

Bit 12

pub fn fifo_map_ena(&mut self) -> FIFO_MAP_ENA_W<'_>

Bits 8:11

pub fn txeof_ena(&mut self) -> TXEOF_ENA_W<'_>

Bits 0:5

impl W<u32, Reg<u32, __0_TO_EOF_DES_ADDR>>

pub fn slc0_to_eof_des_addr(&mut self) -> SLC0_TO_EOF_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_TX_EOF_DES_ADDR>>

pub fn slc0_tx_suc_eof_des_addr(&mut self) -> SLC0_TX_SUC_EOF_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_TO_EOF_BFR_DES_ADDR>>

pub fn slc0_to_eof_bfr_des_addr(&mut self) -> SLC0_TO_EOF_BFR_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __1_TO_EOF_DES_ADDR>>

pub fn slc1_to_eof_des_addr(&mut self) -> SLC1_TO_EOF_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __1_TX_EOF_DES_ADDR>>

pub fn slc1_tx_suc_eof_des_addr(&mut self) -> SLC1_TX_SUC_EOF_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __1_TO_EOF_BFR_DES_ADDR>>

pub fn slc1_to_eof_bfr_des_addr(&mut self) -> SLC1_TO_EOF_BFR_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _AHB_TEST>>

pub fn ahb_testaddr(&mut self) -> AHB_TESTADDR_W<'_>

Bits 4:5

pub fn ahb_testmode(&mut self) -> AHB_TESTMODE_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _SDIO_ST>>

pub fn func2_acc_state(&mut self) -> FUNC2_ACC_STATE_W<'_>

Bits 24:28

pub fn func1_acc_state(&mut self) -> FUNC1_ACC_STATE_W<'_>

Bits 16:20

pub fn bus_st(&mut self) -> BUS_ST_W<'_>

Bits 12:14

pub fn sdio_wakeup(&mut self) -> SDIO_WAKEUP_W<'_>

Bit 8

pub fn func_st(&mut self) -> FUNC_ST_W<'_>

Bits 4:7

pub fn cmd_st(&mut self) -> CMD_ST_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _RX_DSCR_CONF>>

pub fn slc1_rd_retry_threshold(&mut self) -> SLC1_RD_RETRY_THRESHOLD_W<'_>

Bits 21:31

pub fn slc1_rx_fill_en(&mut self) -> SLC1_RX_FILL_EN_W<'_>

Bit 20

pub fn slc1_rx_eof_mode(&mut self) -> SLC1_RX_EOF_MODE_W<'_>

Bit 19

pub fn slc1_rx_fill_mode(&mut self) -> SLC1_RX_FILL_MODE_W<'_>

Bit 18

pub fn slc1_infor_no_replace(&mut self) -> SLC1_INFOR_NO_REPLACE_W<'_>

Bit 17

pub fn slc1_token_no_replace(&mut self) -> SLC1_TOKEN_NO_REPLACE_W<'_>

Bit 16

pub fn slc0_rd_retry_threshold(&mut self) -> SLC0_RD_RETRY_THRESHOLD_W<'_>

Bits 5:15

pub fn slc0_rx_fill_en(&mut self) -> SLC0_RX_FILL_EN_W<'_>

Bit 4

pub fn slc0_rx_eof_mode(&mut self) -> SLC0_RX_EOF_MODE_W<'_>

Bit 3

pub fn slc0_rx_fill_mode(&mut self) -> SLC0_RX_FILL_MODE_W<'_>

Bit 2

pub fn slc0_infor_no_replace(&mut self) -> SLC0_INFOR_NO_REPLACE_W<'_>

Bit 1

pub fn slc0_token_no_replace(&mut self) -> SLC0_TOKEN_NO_REPLACE_W<'_>

Bit 0

impl W<u32, Reg<u32, __0_TXLINK_DSCR>>

pub fn slc0_txlink_dscr(&mut self) -> SLC0_TXLINK_DSCR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_TXLINK_DSCR_BF0>>

pub fn slc0_txlink_dscr_bf0(&mut self) -> SLC0_TXLINK_DSCR_BF0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_TXLINK_DSCR_BF1>>

pub fn slc0_txlink_dscr_bf1(&mut self) -> SLC0_TXLINK_DSCR_BF1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_RXLINK_DSCR>>

pub fn slc0_rxlink_dscr(&mut self) -> SLC0_RXLINK_DSCR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_RXLINK_DSCR_BF0>>

pub fn slc0_rxlink_dscr_bf0(&mut self) -> SLC0_RXLINK_DSCR_BF0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_RXLINK_DSCR_BF1>>

pub fn slc0_rxlink_dscr_bf1(&mut self) -> SLC0_RXLINK_DSCR_BF1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __1_TXLINK_DSCR>>

pub fn slc1_txlink_dscr(&mut self) -> SLC1_TXLINK_DSCR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __1_TXLINK_DSCR_BF0>>

pub fn slc1_txlink_dscr_bf0(&mut self) -> SLC1_TXLINK_DSCR_BF0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __1_TXLINK_DSCR_BF1>>

pub fn slc1_txlink_dscr_bf1(&mut self) -> SLC1_TXLINK_DSCR_BF1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __1_RXLINK_DSCR>>

pub fn slc1_rxlink_dscr(&mut self) -> SLC1_RXLINK_DSCR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __1_RXLINK_DSCR_BF0>>

pub fn slc1_rxlink_dscr_bf0(&mut self) -> SLC1_RXLINK_DSCR_BF0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __1_RXLINK_DSCR_BF1>>

pub fn slc1_rxlink_dscr_bf1(&mut self) -> SLC1_RXLINK_DSCR_BF1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_TX_ERREOF_DES_ADDR>>

pub fn slc0_tx_err_eof_des_addr(&mut self) -> SLC0_TX_ERR_EOF_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __1_TX_ERREOF_DES_ADDR>>

pub fn slc1_tx_err_eof_des_addr(&mut self) -> SLC1_TX_ERR_EOF_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _TOKEN_LAT>>

pub fn slc1_token(&mut self) -> SLC1_TOKEN_W<'_>

Bits 16:27

pub fn slc0_token(&mut self) -> SLC0_TOKEN_W<'_>

Bits 0:11

impl W<u32, Reg<u32, _TX_DSCR_CONF>>

pub fn wr_retry_threshold(&mut self) -> WR_RETRY_THRESHOLD_W<'_>

Bits 0:10

impl W<u32, Reg<u32, _CMD_INFOR0>>

pub fn cmd_content0(&mut self) -> CMD_CONTENT0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CMD_INFOR1>>

pub fn cmd_content1(&mut self) -> CMD_CONTENT1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_LEN_CONF>>

pub fn slc0_tx_new_pkt_ind(&mut self) -> SLC0_TX_NEW_PKT_IND_W<'_>

Bit 28

pub fn slc0_rx_new_pkt_ind(&mut self) -> SLC0_RX_NEW_PKT_IND_W<'_>

Bit 27

pub fn slc0_tx_get_used_dscr(&mut self) -> SLC0_TX_GET_USED_DSCR_W<'_>

Bit 26

pub fn slc0_rx_get_used_dscr(&mut self) -> SLC0_RX_GET_USED_DSCR_W<'_>

Bit 25

pub fn slc0_tx_packet_load_en(&mut self) -> SLC0_TX_PACKET_LOAD_EN_W<'_>

Bit 24

pub fn slc0_rx_packet_load_en(&mut self) -> SLC0_RX_PACKET_LOAD_EN_W<'_>

Bit 23

pub fn slc0_len_inc_more(&mut self) -> SLC0_LEN_INC_MORE_W<'_>

Bit 22

pub fn slc0_len_inc(&mut self) -> SLC0_LEN_INC_W<'_>

Bit 21

pub fn slc0_len_wr(&mut self) -> SLC0_LEN_WR_W<'_>

Bit 20

pub fn slc0_len_wdata(&mut self) -> SLC0_LEN_WDATA_W<'_>

Bits 0:19

impl W<u32, Reg<u32, __0_LENGTH>>

pub fn slc0_len(&mut self) -> SLC0_LEN_W<'_>

Bits 0:19

impl W<u32, Reg<u32, __0_TXPKT_H_DSCR>>

pub fn slc0_tx_pkt_h_dscr_addr(&mut self) -> SLC0_TX_PKT_H_DSCR_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_TXPKT_E_DSCR>>

pub fn slc0_tx_pkt_e_dscr_addr(&mut self) -> SLC0_TX_PKT_E_DSCR_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_RXPKT_H_DSCR>>

pub fn slc0_rx_pkt_h_dscr_addr(&mut self) -> SLC0_RX_PKT_H_DSCR_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_RXPKT_E_DSCR>>

pub fn slc0_rx_pkt_e_dscr_addr(&mut self) -> SLC0_RX_PKT_E_DSCR_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_TXPKTU_H_DSCR>>

pub fn slc0_tx_pkt_start_dscr_addr(
    &mut self
) -> SLC0_TX_PKT_START_DSCR_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_TXPKTU_E_DSCR>>

pub fn slc0_tx_pkt_end_dscr_addr(&mut self) -> SLC0_TX_PKT_END_DSCR_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_RXPKTU_H_DSCR>>

pub fn slc0_rx_pkt_start_dscr_addr(
    &mut self
) -> SLC0_RX_PKT_START_DSCR_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_RXPKTU_E_DSCR>>

pub fn slc0_rx_pkt_end_dscr_addr(&mut self) -> SLC0_RX_PKT_END_DSCR_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SEQ_POSITION>>

pub fn slc1_seq_position(&mut self) -> SLC1_SEQ_POSITION_W<'_>

Bits 8:15

pub fn slc0_seq_position(&mut self) -> SLC0_SEQ_POSITION_W<'_>

Bits 0:7

impl W<u32, Reg<u32, __0_DSCR_REC_CONF>>

pub fn slc0_rx_dscr_rec_lim(&mut self) -> SLC0_RX_DSCR_REC_LIM_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _SDIO_CRC_ST0>>

pub fn dat3_crc_err_cnt(&mut self) -> DAT3_CRC_ERR_CNT_W<'_>

Bits 24:31

pub fn dat2_crc_err_cnt(&mut self) -> DAT2_CRC_ERR_CNT_W<'_>

Bits 16:23

pub fn dat1_crc_err_cnt(&mut self) -> DAT1_CRC_ERR_CNT_W<'_>

Bits 8:15

pub fn dat0_crc_err_cnt(&mut self) -> DAT0_CRC_ERR_CNT_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SDIO_CRC_ST1>>

pub fn err_cnt_clr(&mut self) -> ERR_CNT_CLR_W<'_>

Bit 31

pub fn cmd_crc_err_cnt(&mut self) -> CMD_CRC_ERR_CNT_W<'_>

Bits 0:7

impl W<u32, Reg<u32, __0_EOF_START_DES>>

pub fn slc0_eof_start_des_addr(&mut self) -> SLC0_EOF_START_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_PUSH_DSCR_ADDR>>

pub fn slc0_rx_push_dscr_addr(&mut self) -> SLC0_RX_PUSH_DSCR_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_DONE_DSCR_ADDR>>

pub fn slc0_rx_done_dscr_addr(&mut self) -> SLC0_RX_DONE_DSCR_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_SUB_START_DES>>

pub fn slc0_sub_pac_start_dscr_addr(
    &mut self
) -> SLC0_SUB_PAC_START_DSCR_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, __0_DSCR_CNT>>

pub fn slc0_rx_get_eof_occ(&mut self) -> SLC0_RX_GET_EOF_OCC_W<'_>

Bit 16

pub fn slc0_rx_dscr_cnt_lat(&mut self) -> SLC0_RX_DSCR_CNT_LAT_W<'_>

Bits 0:9

impl W<u32, Reg<u32, __0_LEN_LIM_CONF>>

pub fn slc0_len_lim(&mut self) -> SLC0_LEN_LIM_W<'_>

Bits 0:19

impl W<u32, Reg<u32, __0INT_ST1>>

pub fn slc0_rx_quick_eof_int_st1(&mut self) -> SLC0_RX_QUICK_EOF_INT_ST1_W<'_>

Bit 26

pub fn cmd_dtc_int_st1(&mut self) -> CMD_DTC_INT_ST1_W<'_>

Bit 25

pub fn slc0_tx_err_eof_int_st1(&mut self) -> SLC0_TX_ERR_EOF_INT_ST1_W<'_>

Bit 24

pub fn slc0_wr_retry_done_int_st1(&mut self) -> SLC0_WR_RETRY_DONE_INT_ST1_W<'_>

Bit 23

pub fn slc0_host_rd_ack_int_st1(&mut self) -> SLC0_HOST_RD_ACK_INT_ST1_W<'_>

Bit 22

pub fn slc0_tx_dscr_empty_int_st1(&mut self) -> SLC0_TX_DSCR_EMPTY_INT_ST1_W<'_>

Bit 21

pub fn slc0_rx_dscr_err_int_st1(&mut self) -> SLC0_RX_DSCR_ERR_INT_ST1_W<'_>

Bit 20

pub fn slc0_tx_dscr_err_int_st1(&mut self) -> SLC0_TX_DSCR_ERR_INT_ST1_W<'_>

Bit 19

pub fn slc0_tohost_int_st1(&mut self) -> SLC0_TOHOST_INT_ST1_W<'_>

Bit 18

pub fn slc0_rx_eof_int_st1(&mut self) -> SLC0_RX_EOF_INT_ST1_W<'_>

Bit 17

pub fn slc0_rx_done_int_st1(&mut self) -> SLC0_RX_DONE_INT_ST1_W<'_>

Bit 16

pub fn slc0_tx_suc_eof_int_st1(&mut self) -> SLC0_TX_SUC_EOF_INT_ST1_W<'_>

Bit 15

pub fn slc0_tx_done_int_st1(&mut self) -> SLC0_TX_DONE_INT_ST1_W<'_>

Bit 14

pub fn slc0_token1_1to0_int_st1(&mut self) -> SLC0_TOKEN1_1TO0_INT_ST1_W<'_>

Bit 13

pub fn slc0_token0_1to0_int_st1(&mut self) -> SLC0_TOKEN0_1TO0_INT_ST1_W<'_>

Bit 12

pub fn slc0_tx_ovf_int_st1(&mut self) -> SLC0_TX_OVF_INT_ST1_W<'_>

Bit 11

pub fn slc0_rx_udf_int_st1(&mut self) -> SLC0_RX_UDF_INT_ST1_W<'_>

Bit 10

pub fn slc0_tx_start_int_st1(&mut self) -> SLC0_TX_START_INT_ST1_W<'_>

Bit 9

pub fn slc0_rx_start_int_st1(&mut self) -> SLC0_RX_START_INT_ST1_W<'_>

Bit 8

pub fn frhost_bit7_int_st1(&mut self) -> FRHOST_BIT7_INT_ST1_W<'_>

Bit 7

pub fn frhost_bit6_int_st1(&mut self) -> FRHOST_BIT6_INT_ST1_W<'_>

Bit 6

pub fn frhost_bit5_int_st1(&mut self) -> FRHOST_BIT5_INT_ST1_W<'_>

Bit 5

pub fn frhost_bit4_int_st1(&mut self) -> FRHOST_BIT4_INT_ST1_W<'_>

Bit 4

pub fn frhost_bit3_int_st1(&mut self) -> FRHOST_BIT3_INT_ST1_W<'_>

Bit 3

pub fn frhost_bit2_int_st1(&mut self) -> FRHOST_BIT2_INT_ST1_W<'_>

Bit 2

pub fn frhost_bit1_int_st1(&mut self) -> FRHOST_BIT1_INT_ST1_W<'_>

Bit 1

pub fn frhost_bit0_int_st1(&mut self) -> FRHOST_BIT0_INT_ST1_W<'_>

Bit 0

impl W<u32, Reg<u32, __0INT_ENA1>>

pub fn slc0_rx_quick_eof_int_ena1(&mut self) -> SLC0_RX_QUICK_EOF_INT_ENA1_W<'_>

Bit 26

pub fn cmd_dtc_int_ena1(&mut self) -> CMD_DTC_INT_ENA1_W<'_>

Bit 25

pub fn slc0_tx_err_eof_int_ena1(&mut self) -> SLC0_TX_ERR_EOF_INT_ENA1_W<'_>

Bit 24

pub fn slc0_wr_retry_done_int_ena1(
    &mut self
) -> SLC0_WR_RETRY_DONE_INT_ENA1_W<'_>

Bit 23

pub fn slc0_host_rd_ack_int_ena1(&mut self) -> SLC0_HOST_RD_ACK_INT_ENA1_W<'_>

Bit 22

pub fn slc0_tx_dscr_empty_int_ena1(
    &mut self
) -> SLC0_TX_DSCR_EMPTY_INT_ENA1_W<'_>

Bit 21

pub fn slc0_rx_dscr_err_int_ena1(&mut self) -> SLC0_RX_DSCR_ERR_INT_ENA1_W<'_>

Bit 20

pub fn slc0_tx_dscr_err_int_ena1(&mut self) -> SLC0_TX_DSCR_ERR_INT_ENA1_W<'_>

Bit 19

pub fn slc0_tohost_int_ena1(&mut self) -> SLC0_TOHOST_INT_ENA1_W<'_>

Bit 18

pub fn slc0_rx_eof_int_ena1(&mut self) -> SLC0_RX_EOF_INT_ENA1_W<'_>

Bit 17

pub fn slc0_rx_done_int_ena1(&mut self) -> SLC0_RX_DONE_INT_ENA1_W<'_>

Bit 16

pub fn slc0_tx_suc_eof_int_ena1(&mut self) -> SLC0_TX_SUC_EOF_INT_ENA1_W<'_>

Bit 15

pub fn slc0_tx_done_int_ena1(&mut self) -> SLC0_TX_DONE_INT_ENA1_W<'_>

Bit 14

pub fn slc0_token1_1to0_int_ena1(&mut self) -> SLC0_TOKEN1_1TO0_INT_ENA1_W<'_>

Bit 13

pub fn slc0_token0_1to0_int_ena1(&mut self) -> SLC0_TOKEN0_1TO0_INT_ENA1_W<'_>

Bit 12

pub fn slc0_tx_ovf_int_ena1(&mut self) -> SLC0_TX_OVF_INT_ENA1_W<'_>

Bit 11

pub fn slc0_rx_udf_int_ena1(&mut self) -> SLC0_RX_UDF_INT_ENA1_W<'_>

Bit 10

pub fn slc0_tx_start_int_ena1(&mut self) -> SLC0_TX_START_INT_ENA1_W<'_>

Bit 9

pub fn slc0_rx_start_int_ena1(&mut self) -> SLC0_RX_START_INT_ENA1_W<'_>

Bit 8

pub fn frhost_bit7_int_ena1(&mut self) -> FRHOST_BIT7_INT_ENA1_W<'_>

Bit 7

pub fn frhost_bit6_int_ena1(&mut self) -> FRHOST_BIT6_INT_ENA1_W<'_>

Bit 6

pub fn frhost_bit5_int_ena1(&mut self) -> FRHOST_BIT5_INT_ENA1_W<'_>

Bit 5

pub fn frhost_bit4_int_ena1(&mut self) -> FRHOST_BIT4_INT_ENA1_W<'_>

Bit 4

pub fn frhost_bit3_int_ena1(&mut self) -> FRHOST_BIT3_INT_ENA1_W<'_>

Bit 3

pub fn frhost_bit2_int_ena1(&mut self) -> FRHOST_BIT2_INT_ENA1_W<'_>

Bit 2

pub fn frhost_bit1_int_ena1(&mut self) -> FRHOST_BIT1_INT_ENA1_W<'_>

Bit 1

pub fn frhost_bit0_int_ena1(&mut self) -> FRHOST_BIT0_INT_ENA1_W<'_>

Bit 0

impl W<u32, Reg<u32, __1INT_ST1>>

pub fn slc1_tx_err_eof_int_st1(&mut self) -> SLC1_TX_ERR_EOF_INT_ST1_W<'_>

Bit 24

pub fn slc1_wr_retry_done_int_st1(&mut self) -> SLC1_WR_RETRY_DONE_INT_ST1_W<'_>

Bit 23

pub fn slc1_host_rd_ack_int_st1(&mut self) -> SLC1_HOST_RD_ACK_INT_ST1_W<'_>

Bit 22

pub fn slc1_tx_dscr_empty_int_st1(&mut self) -> SLC1_TX_DSCR_EMPTY_INT_ST1_W<'_>

Bit 21

pub fn slc1_rx_dscr_err_int_st1(&mut self) -> SLC1_RX_DSCR_ERR_INT_ST1_W<'_>

Bit 20

pub fn slc1_tx_dscr_err_int_st1(&mut self) -> SLC1_TX_DSCR_ERR_INT_ST1_W<'_>

Bit 19

pub fn slc1_tohost_int_st1(&mut self) -> SLC1_TOHOST_INT_ST1_W<'_>

Bit 18

pub fn slc1_rx_eof_int_st1(&mut self) -> SLC1_RX_EOF_INT_ST1_W<'_>

Bit 17

pub fn slc1_rx_done_int_st1(&mut self) -> SLC1_RX_DONE_INT_ST1_W<'_>

Bit 16

pub fn slc1_tx_suc_eof_int_st1(&mut self) -> SLC1_TX_SUC_EOF_INT_ST1_W<'_>

Bit 15

pub fn slc1_tx_done_int_st1(&mut self) -> SLC1_TX_DONE_INT_ST1_W<'_>

Bit 14

pub fn slc1_token1_1to0_int_st1(&mut self) -> SLC1_TOKEN1_1TO0_INT_ST1_W<'_>

Bit 13

pub fn slc1_token0_1to0_int_st1(&mut self) -> SLC1_TOKEN0_1TO0_INT_ST1_W<'_>

Bit 12

pub fn slc1_tx_ovf_int_st1(&mut self) -> SLC1_TX_OVF_INT_ST1_W<'_>

Bit 11

pub fn slc1_rx_udf_int_st1(&mut self) -> SLC1_RX_UDF_INT_ST1_W<'_>

Bit 10

pub fn slc1_tx_start_int_st1(&mut self) -> SLC1_TX_START_INT_ST1_W<'_>

Bit 9

pub fn slc1_rx_start_int_st1(&mut self) -> SLC1_RX_START_INT_ST1_W<'_>

Bit 8

pub fn frhost_bit15_int_st1(&mut self) -> FRHOST_BIT15_INT_ST1_W<'_>

Bit 7

pub fn frhost_bit14_int_st1(&mut self) -> FRHOST_BIT14_INT_ST1_W<'_>

Bit 6

pub fn frhost_bit13_int_st1(&mut self) -> FRHOST_BIT13_INT_ST1_W<'_>

Bit 5

pub fn frhost_bit12_int_st1(&mut self) -> FRHOST_BIT12_INT_ST1_W<'_>

Bit 4

pub fn frhost_bit11_int_st1(&mut self) -> FRHOST_BIT11_INT_ST1_W<'_>

Bit 3

pub fn frhost_bit10_int_st1(&mut self) -> FRHOST_BIT10_INT_ST1_W<'_>

Bit 2

pub fn frhost_bit9_int_st1(&mut self) -> FRHOST_BIT9_INT_ST1_W<'_>

Bit 1

pub fn frhost_bit8_int_st1(&mut self) -> FRHOST_BIT8_INT_ST1_W<'_>

Bit 0

impl W<u32, Reg<u32, __1INT_ENA1>>

pub fn slc1_tx_err_eof_int_ena1(&mut self) -> SLC1_TX_ERR_EOF_INT_ENA1_W<'_>

Bit 24

pub fn slc1_wr_retry_done_int_ena1(
    &mut self
) -> SLC1_WR_RETRY_DONE_INT_ENA1_W<'_>

Bit 23

pub fn slc1_host_rd_ack_int_ena1(&mut self) -> SLC1_HOST_RD_ACK_INT_ENA1_W<'_>

Bit 22

pub fn slc1_tx_dscr_empty_int_ena1(
    &mut self
) -> SLC1_TX_DSCR_EMPTY_INT_ENA1_W<'_>

Bit 21

pub fn slc1_rx_dscr_err_int_ena1(&mut self) -> SLC1_RX_DSCR_ERR_INT_ENA1_W<'_>

Bit 20

pub fn slc1_tx_dscr_err_int_ena1(&mut self) -> SLC1_TX_DSCR_ERR_INT_ENA1_W<'_>

Bit 19

pub fn slc1_tohost_int_ena1(&mut self) -> SLC1_TOHOST_INT_ENA1_W<'_>

Bit 18

pub fn slc1_rx_eof_int_ena1(&mut self) -> SLC1_RX_EOF_INT_ENA1_W<'_>

Bit 17

pub fn slc1_rx_done_int_ena1(&mut self) -> SLC1_RX_DONE_INT_ENA1_W<'_>

Bit 16

pub fn slc1_tx_suc_eof_int_ena1(&mut self) -> SLC1_TX_SUC_EOF_INT_ENA1_W<'_>

Bit 15

pub fn slc1_tx_done_int_ena1(&mut self) -> SLC1_TX_DONE_INT_ENA1_W<'_>

Bit 14

pub fn slc1_token1_1to0_int_ena1(&mut self) -> SLC1_TOKEN1_1TO0_INT_ENA1_W<'_>

Bit 13

pub fn slc1_token0_1to0_int_ena1(&mut self) -> SLC1_TOKEN0_1TO0_INT_ENA1_W<'_>

Bit 12

pub fn slc1_tx_ovf_int_ena1(&mut self) -> SLC1_TX_OVF_INT_ENA1_W<'_>

Bit 11

pub fn slc1_rx_udf_int_ena1(&mut self) -> SLC1_RX_UDF_INT_ENA1_W<'_>

Bit 10

pub fn slc1_tx_start_int_ena1(&mut self) -> SLC1_TX_START_INT_ENA1_W<'_>

Bit 9

pub fn slc1_rx_start_int_ena1(&mut self) -> SLC1_RX_START_INT_ENA1_W<'_>

Bit 8

pub fn frhost_bit15_int_ena1(&mut self) -> FRHOST_BIT15_INT_ENA1_W<'_>

Bit 7

pub fn frhost_bit14_int_ena1(&mut self) -> FRHOST_BIT14_INT_ENA1_W<'_>

Bit 6

pub fn frhost_bit13_int_ena1(&mut self) -> FRHOST_BIT13_INT_ENA1_W<'_>

Bit 5

pub fn frhost_bit12_int_ena1(&mut self) -> FRHOST_BIT12_INT_ENA1_W<'_>

Bit 4

pub fn frhost_bit11_int_ena1(&mut self) -> FRHOST_BIT11_INT_ENA1_W<'_>

Bit 3

pub fn frhost_bit10_int_ena1(&mut self) -> FRHOST_BIT10_INT_ENA1_W<'_>

Bit 2

pub fn frhost_bit9_int_ena1(&mut self) -> FRHOST_BIT9_INT_ENA1_W<'_>

Bit 1

pub fn frhost_bit8_int_ena1(&mut self) -> FRHOST_BIT8_INT_ENA1_W<'_>

Bit 0

impl W<u32, Reg<u32, _DATE>>

pub fn date(&mut self) -> DATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _ID>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _OPTIONS0>>

pub fn sw_sys_rst(&mut self) -> SW_SYS_RST_W<'_>

Bit 31

pub fn dg_wrap_force_norst(&mut self) -> DG_WRAP_FORCE_NORST_W<'_>

Bit 30

pub fn dg_wrap_force_rst(&mut self) -> DG_WRAP_FORCE_RST_W<'_>

Bit 29

pub fn analog_force_noiso(&mut self) -> ANALOG_FORCE_NOISO_W<'_>

Bit 28

pub fn pll_force_noiso(&mut self) -> PLL_FORCE_NOISO_W<'_>

Bit 27

pub fn xtl_force_noiso(&mut self) -> XTL_FORCE_NOISO_W<'_>

Bit 26

pub fn analog_force_iso(&mut self) -> ANALOG_FORCE_ISO_W<'_>

Bit 25

pub fn pll_force_iso(&mut self) -> PLL_FORCE_ISO_W<'_>

Bit 24

pub fn xtl_force_iso(&mut self) -> XTL_FORCE_ISO_W<'_>

Bit 23

pub fn bias_core_force_pu(&mut self) -> BIAS_CORE_FORCE_PU_W<'_>

Bit 22

pub fn bias_core_force_pd(&mut self) -> BIAS_CORE_FORCE_PD_W<'_>

Bit 21

pub fn bias_core_folw_8m(&mut self) -> BIAS_CORE_FOLW_8M_W<'_>

Bit 20

pub fn bias_i2c_force_pu(&mut self) -> BIAS_I2C_FORCE_PU_W<'_>

Bit 19

pub fn bias_i2c_force_pd(&mut self) -> BIAS_I2C_FORCE_PD_W<'_>

Bit 18

pub fn bias_i2c_folw_8m(&mut self) -> BIAS_I2C_FOLW_8M_W<'_>

Bit 17

pub fn bias_force_nosleep(&mut self) -> BIAS_FORCE_NOSLEEP_W<'_>

Bit 16

pub fn bias_force_sleep(&mut self) -> BIAS_FORCE_SLEEP_W<'_>

Bit 15

pub fn bias_sleep_folw_8m(&mut self) -> BIAS_SLEEP_FOLW_8M_W<'_>

Bit 14

pub fn xtl_force_pu(&mut self) -> XTL_FORCE_PU_W<'_>

Bit 13

pub fn xtl_force_pd(&mut self) -> XTL_FORCE_PD_W<'_>

Bit 12

pub fn bbpll_force_pu(&mut self) -> BBPLL_FORCE_PU_W<'_>

Bit 11

pub fn bbpll_force_pd(&mut self) -> BBPLL_FORCE_PD_W<'_>

Bit 10

pub fn bbpll_i2c_force_pu(&mut self) -> BBPLL_I2C_FORCE_PU_W<'_>

Bit 9

pub fn bbpll_i2c_force_pd(&mut self) -> BBPLL_I2C_FORCE_PD_W<'_>

Bit 8

pub fn bb_i2c_force_pu(&mut self) -> BB_I2C_FORCE_PU_W<'_>

Bit 7

pub fn bb_i2c_force_pd(&mut self) -> BB_I2C_FORCE_PD_W<'_>

Bit 6

pub fn sw_procpu_rst(&mut self) -> SW_PROCPU_RST_W<'_>

Bit 5

pub fn sw_appcpu_rst(&mut self) -> SW_APPCPU_RST_W<'_>

Bit 4

pub fn sw_stall_procpu_c0(&mut self) -> SW_STALL_PROCPU_C0_W<'_>

Bits 2:3

pub fn sw_stall_appcpu_c0(&mut self) -> SW_STALL_APPCPU_C0_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SLP_TIMER0>>

pub fn slp_val_lo(&mut self) -> SLP_VAL_LO_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SLP_TIMER1>>

pub fn main_timer_alarm_en(&mut self) -> MAIN_TIMER_ALARM_EN_W<'_>

Bit 16

pub fn slp_val_hi(&mut self) -> SLP_VAL_HI_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _TIME_UPDATE>>

pub fn time_update(&mut self) -> TIME_UPDATE_W<'_>

Bit 31

pub fn time_valid(&mut self) -> TIME_VALID_W<'_>

Bit 30

impl W<u32, Reg<u32, _TIME0>>

pub fn time_lo(&mut self) -> TIME_LO_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _TIME1>>

pub fn time_hi(&mut self) -> TIME_HI_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _STATE0>>

pub fn sleep_en(&mut self) -> SLEEP_EN_W<'_>

Bit 31

pub fn slp_reject(&mut self) -> SLP_REJECT_W<'_>

Bit 30

pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<'_>

Bit 29

pub fn sdio_active_ind(&mut self) -> SDIO_ACTIVE_IND_W<'_>

Bit 28

pub fn ulp_cp_slp_timer_en(&mut self) -> ULP_CP_SLP_TIMER_EN_W<'_>

Bit 24

pub fn touch_slp_timer_en(&mut self) -> TOUCH_SLP_TIMER_EN_W<'_>

Bit 23

pub fn apb2rtc_bridge_sel(&mut self) -> APB2RTC_BRIDGE_SEL_W<'_>

Bit 22

pub fn ulp_cp_wakeup_force_en(&mut self) -> ULP_CP_WAKEUP_FORCE_EN_W<'_>

Bit 21

pub fn touch_wakeup_force_en(&mut self) -> TOUCH_WAKEUP_FORCE_EN_W<'_>

Bit 20

impl W<u32, Reg<u32, _TIMER1>>

pub fn pll_buf_wait(&mut self) -> PLL_BUF_WAIT_W<'_>

Bits 24:31

pub fn xtl_buf_wait(&mut self) -> XTL_BUF_WAIT_W<'_>

Bits 14:23

pub fn ck8m_wait(&mut self) -> CK8M_WAIT_W<'_>

Bits 6:13

pub fn cpu_stall_wait(&mut self) -> CPU_STALL_WAIT_W<'_>

Bits 1:5

pub fn cpu_stall_en(&mut self) -> CPU_STALL_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _TIMER2>>

pub fn min_time_ck8m_off(&mut self) -> MIN_TIME_CK8M_OFF_W<'_>

Bits 24:31

pub fn ulpcp_touch_start_wait(&mut self) -> ULPCP_TOUCH_START_WAIT_W<'_>

Bits 15:23

impl W<u32, Reg<u32, _TIMER3>>

pub fn rom_ram_powerup_timer(&mut self) -> ROM_RAM_POWERUP_TIMER_W<'_>

Bits 25:31

pub fn rom_ram_wait_timer(&mut self) -> ROM_RAM_WAIT_TIMER_W<'_>

Bits 16:24

pub fn wifi_powerup_timer(&mut self) -> WIFI_POWERUP_TIMER_W<'_>

Bits 9:15

pub fn wifi_wait_timer(&mut self) -> WIFI_WAIT_TIMER_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _TIMER4>>

pub fn dg_wrap_powerup_timer(&mut self) -> DG_WRAP_POWERUP_TIMER_W<'_>

Bits 25:31

pub fn dg_wrap_wait_timer(&mut self) -> DG_WRAP_WAIT_TIMER_W<'_>

Bits 16:24

pub fn powerup_timer(&mut self) -> POWERUP_TIMER_W<'_>

Bits 9:15

pub fn wait_timer(&mut self) -> WAIT_TIMER_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _TIMER5>>

pub fn rtcmem_powerup_timer(&mut self) -> RTCMEM_POWERUP_TIMER_W<'_>

Bits 25:31

pub fn rtcmem_wait_timer(&mut self) -> RTCMEM_WAIT_TIMER_W<'_>

Bits 16:24

pub fn min_slp_val(&mut self) -> MIN_SLP_VAL_W<'_>

Bits 8:15

pub fn ulp_cp_subtimer_prediv(&mut self) -> ULP_CP_SUBTIMER_PREDIV_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _ANA_CONF>>

pub fn pll_i2c_pu(&mut self) -> PLL_I2C_PU_W<'_>

Bit 31

pub fn ckgen_i2c_pu(&mut self) -> CKGEN_I2C_PU_W<'_>

Bit 30

pub fn rfrx_pbus_pu(&mut self) -> RFRX_PBUS_PU_W<'_>

Bit 28

pub fn txrf_i2c_pu(&mut self) -> TXRF_I2C_PU_W<'_>

Bit 27

pub fn pvtmon_pu(&mut self) -> PVTMON_PU_W<'_>

Bit 26

pub fn bbpll_cal_slp_start(&mut self) -> BBPLL_CAL_SLP_START_W<'_>

Bit 25

pub fn plla_force_pu(&mut self) -> PLLA_FORCE_PU_W<'_>

Bit 24

pub fn plla_force_pd(&mut self) -> PLLA_FORCE_PD_W<'_>

Bit 23

impl W<u32, Reg<u32, _RESET_STATE>>

pub fn procpu_stat_vector_sel(&mut self) -> PROCPU_STAT_VECTOR_SEL_W<'_>

Bit 13

pub fn appcpu_stat_vector_sel(&mut self) -> APPCPU_STAT_VECTOR_SEL_W<'_>

Bit 12

pub fn reset_cause_appcpu(&mut self) -> RESET_CAUSE_APPCPU_W<'_>

Bits 6:11

pub fn reset_cause_procpu(&mut self) -> RESET_CAUSE_PROCPU_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _WAKEUP_STATE>>

pub fn gpio_wakeup_filter(&mut self) -> GPIO_WAKEUP_FILTER_W<'_>

Bit 22

pub fn wakeup_ena(&mut self) -> WAKEUP_ENA_W<'_>

Bits 11:21

pub fn wakeup_cause(&mut self) -> WAKEUP_CAUSE_W<'_>

Bits 0:10

impl W<u32, Reg<u32, _INT_ENA>>

pub fn main_timer_int_ena(&mut self) -> MAIN_TIMER_INT_ENA_W<'_>

Bit 8

pub fn brown_out_int_ena(&mut self) -> BROWN_OUT_INT_ENA_W<'_>

Bit 7

pub fn touch_int_ena(&mut self) -> TOUCH_INT_ENA_W<'_>

Bit 6

pub fn ulp_cp_int_ena(&mut self) -> ULP_CP_INT_ENA_W<'_>

Bit 5

pub fn time_valid_int_ena(&mut self) -> TIME_VALID_INT_ENA_W<'_>

Bit 4

pub fn wdt_int_ena(&mut self) -> WDT_INT_ENA_W<'_>

Bit 3

pub fn sdio_idle_int_ena(&mut self) -> SDIO_IDLE_INT_ENA_W<'_>

Bit 2

pub fn slp_reject_int_ena(&mut self) -> SLP_REJECT_INT_ENA_W<'_>

Bit 1

pub fn slp_wakeup_int_ena(&mut self) -> SLP_WAKEUP_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_RAW>>

pub fn main_timer_int_raw(&mut self) -> MAIN_TIMER_INT_RAW_W<'_>

Bit 8

pub fn brown_out_int_raw(&mut self) -> BROWN_OUT_INT_RAW_W<'_>

Bit 7

pub fn touch_int_raw(&mut self) -> TOUCH_INT_RAW_W<'_>

Bit 6

pub fn ulp_cp_int_raw(&mut self) -> ULP_CP_INT_RAW_W<'_>

Bit 5

pub fn time_valid_int_raw(&mut self) -> TIME_VALID_INT_RAW_W<'_>

Bit 4

pub fn wdt_int_raw(&mut self) -> WDT_INT_RAW_W<'_>

Bit 3

pub fn sdio_idle_int_raw(&mut self) -> SDIO_IDLE_INT_RAW_W<'_>

Bit 2

pub fn slp_reject_int_raw(&mut self) -> SLP_REJECT_INT_RAW_W<'_>

Bit 1

pub fn slp_wakeup_int_raw(&mut self) -> SLP_WAKEUP_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ST>>

pub fn main_timer_int_st(&mut self) -> MAIN_TIMER_INT_ST_W<'_>

Bit 8

pub fn brown_out_int_st(&mut self) -> BROWN_OUT_INT_ST_W<'_>

Bit 7

pub fn touch_int_st(&mut self) -> TOUCH_INT_ST_W<'_>

Bit 6

pub fn sar_int_st(&mut self) -> SAR_INT_ST_W<'_>

Bit 5

pub fn time_valid_int_st(&mut self) -> TIME_VALID_INT_ST_W<'_>

Bit 4

pub fn wdt_int_st(&mut self) -> WDT_INT_ST_W<'_>

Bit 3

pub fn sdio_idle_int_st(&mut self) -> SDIO_IDLE_INT_ST_W<'_>

Bit 2

pub fn slp_reject_int_st(&mut self) -> SLP_REJECT_INT_ST_W<'_>

Bit 1

pub fn slp_wakeup_int_st(&mut self) -> SLP_WAKEUP_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_CLR>>

pub fn main_timer_int_clr(&mut self) -> MAIN_TIMER_INT_CLR_W<'_>

Bit 8

pub fn brown_out_int_clr(&mut self) -> BROWN_OUT_INT_CLR_W<'_>

Bit 7

pub fn touch_int_clr(&mut self) -> TOUCH_INT_CLR_W<'_>

Bit 6

pub fn sar_int_clr(&mut self) -> SAR_INT_CLR_W<'_>

Bit 5

pub fn time_valid_int_clr(&mut self) -> TIME_VALID_INT_CLR_W<'_>

Bit 4

pub fn wdt_int_clr(&mut self) -> WDT_INT_CLR_W<'_>

Bit 3

pub fn sdio_idle_int_clr(&mut self) -> SDIO_IDLE_INT_CLR_W<'_>

Bit 2

pub fn slp_reject_int_clr(&mut self) -> SLP_REJECT_INT_CLR_W<'_>

Bit 1

pub fn slp_wakeup_int_clr(&mut self) -> SLP_WAKEUP_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, _STORE0>>

pub fn scratch0(&mut self) -> SCRATCH0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _STORE1>>

pub fn scratch1(&mut self) -> SCRATCH1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _STORE2>>

pub fn scratch2(&mut self) -> SCRATCH2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _STORE3>>

pub fn scratch3(&mut self) -> SCRATCH3_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _EXT_XTL_CONF>>

pub fn xtl_ext_ctr_en(&mut self) -> XTL_EXT_CTR_EN_W<'_>

Bit 31

pub fn xtl_ext_ctr_lv(&mut self) -> XTL_EXT_CTR_LV_W<'_>

Bit 30

impl W<u32, Reg<u32, _EXT_WAKEUP_CONF>>

pub fn ext_wakeup1_lv(&mut self) -> EXT_WAKEUP1_LV_W<'_>

Bit 31

pub fn ext_wakeup0_lv(&mut self) -> EXT_WAKEUP0_LV_W<'_>

Bit 30

impl W<u32, Reg<u32, _SLP_REJECT_CONF>>

pub fn reject_cause(&mut self) -> REJECT_CAUSE_W<'_>

Bits 28:31

pub fn deep_slp_reject_en(&mut self) -> DEEP_SLP_REJECT_EN_W<'_>

Bit 27

pub fn light_slp_reject_en(&mut self) -> LIGHT_SLP_REJECT_EN_W<'_>

Bit 26

pub fn sdio_reject_en(&mut self) -> SDIO_REJECT_EN_W<'_>

Bit 25

pub fn gpio_reject_en(&mut self) -> GPIO_REJECT_EN_W<'_>

Bit 24

impl W<u32, Reg<u32, _CPU_PERIOD_CONF>>

pub fn cpuperiod_sel(&mut self) -> CPUPERIOD_SEL_W<'_>

Bits 30:31

pub fn cpusel_conf(&mut self) -> CPUSEL_CONF_W<'_>

Bit 29

impl W<u32, Reg<u32, _SDIO_ACT_CONF>>

pub fn sdio_act_dnum(&mut self) -> SDIO_ACT_DNUM_W<'_>

Bits 22:31

impl W<u32, Reg<u32, _CLK_CONF>>

pub fn ana_clk_rtc_sel(&mut self) -> ANA_CLK_RTC_SEL_W<'_>

Bits 30:31

pub fn fast_clk_rtc_sel(&mut self) -> FAST_CLK_RTC_SEL_W<'_>

Bit 29

pub fn soc_clk_sel(&mut self) -> SOC_CLK_SEL_W<'_>

Bits 27:28

pub fn ck8m_force_pu(&mut self) -> CK8M_FORCE_PU_W<'_>

Bit 26

pub fn ck8m_force_pd(&mut self) -> CK8M_FORCE_PD_W<'_>

Bit 25

pub fn ck8m_dfreq(&mut self) -> CK8M_DFREQ_W<'_>

Bits 17:24

pub fn ck8m_force_nogating(&mut self) -> CK8M_FORCE_NOGATING_W<'_>

Bit 16

pub fn xtal_force_nogating(&mut self) -> XTAL_FORCE_NOGATING_W<'_>

Bit 15

pub fn ck8m_div_sel(&mut self) -> CK8M_DIV_SEL_W<'_>

Bits 12:14

pub fn ck8m_dfreq_force(&mut self) -> CK8M_DFREQ_FORCE_W<'_>

Bit 11

pub fn dig_clk8m_en(&mut self) -> DIG_CLK8M_EN_W<'_>

Bit 10

pub fn dig_clk8m_d256_en(&mut self) -> DIG_CLK8M_D256_EN_W<'_>

Bit 9

pub fn dig_xtal32k_en(&mut self) -> DIG_XTAL32K_EN_W<'_>

Bit 8

pub fn enb_ck8m_div(&mut self) -> ENB_CK8M_DIV_W<'_>

Bit 7

pub fn enb_ck8m(&mut self) -> ENB_CK8M_W<'_>

Bit 6

pub fn ck8m_div(&mut self) -> CK8M_DIV_W<'_>

Bits 4:5

impl W<u32, Reg<u32, _SDIO_CONF>>

pub fn xpd_sdio_reg(&mut self) -> XPD_SDIO_REG_W<'_>

Bit 31

pub fn drefh_sdio(&mut self) -> DREFH_SDIO_W<'_>

Bits 29:30

pub fn drefm_sdio(&mut self) -> DREFM_SDIO_W<'_>

Bits 27:28

pub fn drefl_sdio(&mut self) -> DREFL_SDIO_W<'_>

Bits 25:26

pub fn reg1p8_ready(&mut self) -> REG1P8_READY_W<'_>

Bit 24

pub fn sdio_tieh(&mut self) -> SDIO_TIEH_W<'_>

Bit 23

pub fn sdio_force(&mut self) -> SDIO_FORCE_W<'_>

Bit 22

pub fn sdio_pd_en(&mut self) -> SDIO_PD_EN_W<'_>

Bit 21

impl W<u32, Reg<u32, _BIAS_CONF>>

pub fn rst_bias_i2c(&mut self) -> RST_BIAS_I2C_W<'_>

Bit 31

pub fn dec_heartbeat_width(&mut self) -> DEC_HEARTBEAT_WIDTH_W<'_>

Bit 30

pub fn inc_heartbeat_period(&mut self) -> INC_HEARTBEAT_PERIOD_W<'_>

Bit 29

pub fn dec_heartbeat_period(&mut self) -> DEC_HEARTBEAT_PERIOD_W<'_>

Bit 28

pub fn inc_heartbeat_refresh(&mut self) -> INC_HEARTBEAT_REFRESH_W<'_>

Bit 27

pub fn enb_sck_xtal(&mut self) -> ENB_SCK_XTAL_W<'_>

Bit 26

pub fn dbg_atten(&mut self) -> DBG_ATTEN_W<'_>

Bits 24:25

pub fn force_pu(&mut self) -> FORCE_PU_W<'_>

Bit 31

pub fn force_pd(&mut self) -> FORCE_PD_W<'_>

Bit 30

pub fn dboost_force_pu(&mut self) -> DBOOST_FORCE_PU_W<'_>

Bit 29

pub fn dboost_force_pd(&mut self) -> DBOOST_FORCE_PD_W<'_>

Bit 28

pub fn dbias_wak(&mut self) -> DBIAS_WAK_W<'_>

Bits 25:27

pub fn dbias_slp(&mut self) -> DBIAS_SLP_W<'_>

Bits 22:24

pub fn sck_dcap(&mut self) -> SCK_DCAP_W<'_>

Bits 14:21

pub fn dig_dbias_wak(&mut self) -> DIG_DBIAS_WAK_W<'_>

Bits 11:13

pub fn dig_dbias_slp(&mut self) -> DIG_DBIAS_SLP_W<'_>

Bits 8:10

pub fn sck_dcap_force(&mut self) -> SCK_DCAP_FORCE_W<'_>

Bit 7

impl W<u32, Reg<u32, _PWC>>

pub fn pd_en(&mut self) -> PD_EN_W<'_>

Bit 20

pub fn force_pu(&mut self) -> FORCE_PU_W<'_>

Bit 19

pub fn force_pd(&mut self) -> FORCE_PD_W<'_>

Bit 18

pub fn slowmem_pd_en(&mut self) -> SLOWMEM_PD_EN_W<'_>

Bit 17

pub fn slowmem_force_pu(&mut self) -> SLOWMEM_FORCE_PU_W<'_>

Bit 16

pub fn slowmem_force_pd(&mut self) -> SLOWMEM_FORCE_PD_W<'_>

Bit 15

pub fn fastmem_pd_en(&mut self) -> FASTMEM_PD_EN_W<'_>

Bit 14

pub fn fastmem_force_pu(&mut self) -> FASTMEM_FORCE_PU_W<'_>

Bit 13

pub fn fastmem_force_pd(&mut self) -> FASTMEM_FORCE_PD_W<'_>

Bit 12

pub fn slowmem_force_lpu(&mut self) -> SLOWMEM_FORCE_LPU_W<'_>

Bit 11

pub fn slowmem_force_lpd(&mut self) -> SLOWMEM_FORCE_LPD_W<'_>

Bit 10

pub fn slowmem_folw_cpu(&mut self) -> SLOWMEM_FOLW_CPU_W<'_>

Bit 9

pub fn fastmem_force_lpu(&mut self) -> FASTMEM_FORCE_LPU_W<'_>

Bit 8

pub fn fastmem_force_lpd(&mut self) -> FASTMEM_FORCE_LPD_W<'_>

Bit 7

pub fn fastmem_folw_cpu(&mut self) -> FASTMEM_FOLW_CPU_W<'_>

Bit 6

pub fn force_noiso(&mut self) -> FORCE_NOISO_W<'_>

Bit 5

pub fn force_iso(&mut self) -> FORCE_ISO_W<'_>

Bit 4

pub fn slowmem_force_iso(&mut self) -> SLOWMEM_FORCE_ISO_W<'_>

Bit 3

pub fn slowmem_force_noiso(&mut self) -> SLOWMEM_FORCE_NOISO_W<'_>

Bit 2

pub fn fastmem_force_iso(&mut self) -> FASTMEM_FORCE_ISO_W<'_>

Bit 1

pub fn fastmem_force_noiso(&mut self) -> FASTMEM_FORCE_NOISO_W<'_>

Bit 0

impl W<u32, Reg<u32, _DIG_PWC>>

pub fn dg_wrap_pd_en(&mut self) -> DG_WRAP_PD_EN_W<'_>

Bit 31

pub fn wifi_pd_en(&mut self) -> WIFI_PD_EN_W<'_>

Bit 30

pub fn inter_ram4_pd_en(&mut self) -> INTER_RAM4_PD_EN_W<'_>

Bit 29

pub fn inter_ram3_pd_en(&mut self) -> INTER_RAM3_PD_EN_W<'_>

Bit 28

pub fn inter_ram2_pd_en(&mut self) -> INTER_RAM2_PD_EN_W<'_>

Bit 27

pub fn inter_ram1_pd_en(&mut self) -> INTER_RAM1_PD_EN_W<'_>

Bit 26

pub fn inter_ram0_pd_en(&mut self) -> INTER_RAM0_PD_EN_W<'_>

Bit 25

pub fn rom0_pd_en(&mut self) -> ROM0_PD_EN_W<'_>

Bit 24

pub fn dg_wrap_force_pu(&mut self) -> DG_WRAP_FORCE_PU_W<'_>

Bit 20

pub fn dg_wrap_force_pd(&mut self) -> DG_WRAP_FORCE_PD_W<'_>

Bit 19

pub fn wifi_force_pu(&mut self) -> WIFI_FORCE_PU_W<'_>

Bit 18

pub fn wifi_force_pd(&mut self) -> WIFI_FORCE_PD_W<'_>

Bit 17

pub fn inter_ram4_force_pu(&mut self) -> INTER_RAM4_FORCE_PU_W<'_>

Bit 16

pub fn inter_ram4_force_pd(&mut self) -> INTER_RAM4_FORCE_PD_W<'_>

Bit 15

pub fn inter_ram3_force_pu(&mut self) -> INTER_RAM3_FORCE_PU_W<'_>

Bit 14

pub fn inter_ram3_force_pd(&mut self) -> INTER_RAM3_FORCE_PD_W<'_>

Bit 13

pub fn inter_ram2_force_pu(&mut self) -> INTER_RAM2_FORCE_PU_W<'_>

Bit 12

pub fn inter_ram2_force_pd(&mut self) -> INTER_RAM2_FORCE_PD_W<'_>

Bit 11

pub fn inter_ram1_force_pu(&mut self) -> INTER_RAM1_FORCE_PU_W<'_>

Bit 10

pub fn inter_ram1_force_pd(&mut self) -> INTER_RAM1_FORCE_PD_W<'_>

Bit 9

pub fn inter_ram0_force_pu(&mut self) -> INTER_RAM0_FORCE_PU_W<'_>

Bit 8

pub fn inter_ram0_force_pd(&mut self) -> INTER_RAM0_FORCE_PD_W<'_>

Bit 7

pub fn rom0_force_pu(&mut self) -> ROM0_FORCE_PU_W<'_>

Bit 6

pub fn rom0_force_pd(&mut self) -> ROM0_FORCE_PD_W<'_>

Bit 5

pub fn lslp_mem_force_pu(&mut self) -> LSLP_MEM_FORCE_PU_W<'_>

Bit 4

pub fn lslp_mem_force_pd(&mut self) -> LSLP_MEM_FORCE_PD_W<'_>

Bit 3

impl W<u32, Reg<u32, _DIG_ISO>>

pub fn dg_wrap_force_noiso(&mut self) -> DG_WRAP_FORCE_NOISO_W<'_>

Bit 31

pub fn dg_wrap_force_iso(&mut self) -> DG_WRAP_FORCE_ISO_W<'_>

Bit 30

pub fn wifi_force_noiso(&mut self) -> WIFI_FORCE_NOISO_W<'_>

Bit 29

pub fn wifi_force_iso(&mut self) -> WIFI_FORCE_ISO_W<'_>

Bit 28

pub fn inter_ram4_force_noiso(&mut self) -> INTER_RAM4_FORCE_NOISO_W<'_>

Bit 27

pub fn inter_ram4_force_iso(&mut self) -> INTER_RAM4_FORCE_ISO_W<'_>

Bit 26

pub fn inter_ram3_force_noiso(&mut self) -> INTER_RAM3_FORCE_NOISO_W<'_>

Bit 25

pub fn inter_ram3_force_iso(&mut self) -> INTER_RAM3_FORCE_ISO_W<'_>

Bit 24

pub fn inter_ram2_force_noiso(&mut self) -> INTER_RAM2_FORCE_NOISO_W<'_>

Bit 23

pub fn inter_ram2_force_iso(&mut self) -> INTER_RAM2_FORCE_ISO_W<'_>

Bit 22

pub fn inter_ram1_force_noiso(&mut self) -> INTER_RAM1_FORCE_NOISO_W<'_>

Bit 21

pub fn inter_ram1_force_iso(&mut self) -> INTER_RAM1_FORCE_ISO_W<'_>

Bit 20

pub fn inter_ram0_force_noiso(&mut self) -> INTER_RAM0_FORCE_NOISO_W<'_>

Bit 19

pub fn inter_ram0_force_iso(&mut self) -> INTER_RAM0_FORCE_ISO_W<'_>

Bit 18

pub fn rom0_force_noiso(&mut self) -> ROM0_FORCE_NOISO_W<'_>

Bit 17

pub fn rom0_force_iso(&mut self) -> ROM0_FORCE_ISO_W<'_>

Bit 16

pub fn dg_pad_force_hold(&mut self) -> DG_PAD_FORCE_HOLD_W<'_>

Bit 15

pub fn dg_pad_force_unhold(&mut self) -> DG_PAD_FORCE_UNHOLD_W<'_>

Bit 14

pub fn dg_pad_force_iso(&mut self) -> DG_PAD_FORCE_ISO_W<'_>

Bit 13

pub fn dg_pad_force_noiso(&mut self) -> DG_PAD_FORCE_NOISO_W<'_>

Bit 12

pub fn dg_pad_autohold_en(&mut self) -> DG_PAD_AUTOHOLD_EN_W<'_>

Bit 11

pub fn clr_dg_pad_autohold(&mut self) -> CLR_DG_PAD_AUTOHOLD_W<'_>

Bit 10

pub fn dg_pad_autohold(&mut self) -> DG_PAD_AUTOHOLD_W<'_>

Bit 9

pub fn dig_iso_force_on(&mut self) -> DIG_ISO_FORCE_ON_W<'_>

Bit 8

pub fn dig_iso_force_off(&mut self) -> DIG_ISO_FORCE_OFF_W<'_>

Bit 7

impl W<u32, Reg<u32, _WDTCONFIG0>>

pub fn wdt_en(&mut self) -> WDT_EN_W<'_>

Bit 31

pub fn wdt_stg0(&mut self) -> WDT_STG0_W<'_>

Bits 28:30

pub fn wdt_stg1(&mut self) -> WDT_STG1_W<'_>

Bits 25:27

pub fn wdt_stg2(&mut self) -> WDT_STG2_W<'_>

Bits 22:24

pub fn wdt_stg3(&mut self) -> WDT_STG3_W<'_>

Bits 19:21

pub fn wdt_edge_int_en(&mut self) -> WDT_EDGE_INT_EN_W<'_>

Bit 18

pub fn wdt_level_int_en(&mut self) -> WDT_LEVEL_INT_EN_W<'_>

Bit 17

pub fn wdt_cpu_reset_length(&mut self) -> WDT_CPU_RESET_LENGTH_W<'_>

Bits 14:16

pub fn wdt_sys_reset_length(&mut self) -> WDT_SYS_RESET_LENGTH_W<'_>

Bits 11:13

pub fn wdt_flashboot_mod_en(&mut self) -> WDT_FLASHBOOT_MOD_EN_W<'_>

Bit 10

pub fn wdt_procpu_reset_en(&mut self) -> WDT_PROCPU_RESET_EN_W<'_>

Bit 9

pub fn wdt_appcpu_reset_en(&mut self) -> WDT_APPCPU_RESET_EN_W<'_>

Bit 8

pub fn wdt_pause_in_slp(&mut self) -> WDT_PAUSE_IN_SLP_W<'_>

Bit 7

impl W<u32, Reg<u32, _WDTCONFIG1>>

pub fn wdt_stg0_hold(&mut self) -> WDT_STG0_HOLD_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _WDTCONFIG2>>

pub fn wdt_stg1_hold(&mut self) -> WDT_STG1_HOLD_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _WDTCONFIG3>>

pub fn wdt_stg2_hold(&mut self) -> WDT_STG2_HOLD_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _WDTCONFIG4>>

pub fn wdt_stg3_hold(&mut self) -> WDT_STG3_HOLD_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _WDTFEED>>

pub fn wdt_feed(&mut self) -> WDT_FEED_W<'_>

Bit 31

impl W<u32, Reg<u32, _WDTWPROTECT>>

pub fn wdt_wkey(&mut self) -> WDT_WKEY_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _TEST_MUX>>

pub fn dtest_rtc(&mut self) -> DTEST_RTC_W<'_>

Bits 30:31

pub fn ent_rtc(&mut self) -> ENT_RTC_W<'_>

Bit 29

impl W<u32, Reg<u32, _SW_CPU_STALL>>

pub fn sw_stall_procpu_c1(&mut self) -> SW_STALL_PROCPU_C1_W<'_>

Bits 26:31

pub fn sw_stall_appcpu_c1(&mut self) -> SW_STALL_APPCPU_C1_W<'_>

Bits 20:25

impl W<u32, Reg<u32, _STORE4>>

pub fn scratch4(&mut self) -> SCRATCH4_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _STORE5>>

pub fn scratch5(&mut self) -> SCRATCH5_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _STORE6>>

pub fn scratch6(&mut self) -> SCRATCH6_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _STORE7>>

pub fn scratch7(&mut self) -> SCRATCH7_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _DIAG1>>

pub fn low_power_diag1(&mut self) -> LOW_POWER_DIAG1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _HOLD_FORCE>>

pub fn x32n_hold_force(&mut self) -> X32N_HOLD_FORCE_W<'_>

Bit 17

pub fn x32p_hold_force(&mut self) -> X32P_HOLD_FORCE_W<'_>

Bit 16

pub fn touch_pad7_hold_force(&mut self) -> TOUCH_PAD7_HOLD_FORCE_W<'_>

Bit 15

pub fn touch_pad6_hold_force(&mut self) -> TOUCH_PAD6_HOLD_FORCE_W<'_>

Bit 14

pub fn touch_pad5_hold_force(&mut self) -> TOUCH_PAD5_HOLD_FORCE_W<'_>

Bit 13

pub fn touch_pad4_hold_force(&mut self) -> TOUCH_PAD4_HOLD_FORCE_W<'_>

Bit 12

pub fn touch_pad3_hold_force(&mut self) -> TOUCH_PAD3_HOLD_FORCE_W<'_>

Bit 11

pub fn touch_pad2_hold_force(&mut self) -> TOUCH_PAD2_HOLD_FORCE_W<'_>

Bit 10

pub fn touch_pad1_hold_force(&mut self) -> TOUCH_PAD1_HOLD_FORCE_W<'_>

Bit 9

pub fn touch_pad0_hold_force(&mut self) -> TOUCH_PAD0_HOLD_FORCE_W<'_>

Bit 8

pub fn sense4_hold_force(&mut self) -> SENSE4_HOLD_FORCE_W<'_>

Bit 7

pub fn sense3_hold_force(&mut self) -> SENSE3_HOLD_FORCE_W<'_>

Bit 6

pub fn sense2_hold_force(&mut self) -> SENSE2_HOLD_FORCE_W<'_>

Bit 5

pub fn sense1_hold_force(&mut self) -> SENSE1_HOLD_FORCE_W<'_>

Bit 4

pub fn pdac2_hold_force(&mut self) -> PDAC2_HOLD_FORCE_W<'_>

Bit 3

pub fn pdac1_hold_force(&mut self) -> PDAC1_HOLD_FORCE_W<'_>

Bit 2

pub fn adc2_hold_force(&mut self) -> ADC2_HOLD_FORCE_W<'_>

Bit 1

pub fn adc1_hold_force(&mut self) -> ADC1_HOLD_FORCE_W<'_>

Bit 0

impl W<u32, Reg<u32, _EXT_WAKEUP1>>

pub fn ext_wakeup1_status_clr(&mut self) -> EXT_WAKEUP1_STATUS_CLR_W<'_>

Bit 18

pub fn ext_wakeup1_sel(&mut self) -> EXT_WAKEUP1_SEL_W<'_>

Bits 0:17

impl W<u32, Reg<u32, _EXT_WAKEUP1_STATUS>>

pub fn ext_wakeup1_status(&mut self) -> EXT_WAKEUP1_STATUS_W<'_>

Bits 0:17

impl W<u32, Reg<u32, _BROWN_OUT>>

pub fn brown_out_det(&mut self) -> BROWN_OUT_DET_W<'_>

Bit 31

pub fn brown_out_ena(&mut self) -> BROWN_OUT_ENA_W<'_>

Bit 30

pub fn dbrown_out_thres(&mut self) -> DBROWN_OUT_THRES_W<'_>

Bits 27:29

pub fn brown_out_rst_ena(&mut self) -> BROWN_OUT_RST_ENA_W<'_>

Bit 26

pub fn brown_out_rst_wait(&mut self) -> BROWN_OUT_RST_WAIT_W<'_>

Bits 16:25

pub fn brown_out_pd_rf_ena(&mut self) -> BROWN_OUT_PD_RF_ENA_W<'_>

Bit 15

pub fn brown_out_close_flash_ena(&mut self) -> BROWN_OUT_CLOSE_FLASH_ENA_W<'_>

Bit 14

impl W<u32, Reg<u32, _DATE>>

pub fn cntl_date(&mut self) -> CNTL_DATE_W<'_>

Bits 0:27

impl W<u32, Reg<u32, _CNTL>>

pub fn force_pu(&mut self) -> FORCE_PU_W<'_>

Bit 31 - Force RTC power up

pub fn force_pd(&mut self) -> FORCE_PD_W<'_>

Bit 30 - Force RTC power down (decrease voltage to 0.8V or lower)

pub fn force_dboost_pu(&mut self) -> FORCE_DBOOST_PU_W<'_>

Bit 29 - Force DBOOST power up

pub fn force_dboost_pd(&mut self) -> FORCE_DBOOST_PD_W<'_>

Bit 28 - Force DBOOST power down

pub fn dbias_wak(&mut self) -> DBIAS_WAK_W<'_>

Bits 25:27 - RTC DBIAS during wakeup

pub fn dbias_slp(&mut self) -> DBIAS_SLP_W<'_>

Bits 22:24 - RTC DBIAS during sleep

pub fn sck_dcap(&mut self) -> SCK_DCAP_W<'_>

Bits 14:21 - 150kHz oscillator tuning

pub fn dig_dbias_wak(&mut self) -> DIG_DBIAS_WAK_W<'_>

Bits 11:13 - DBIAS during wakeup

pub fn dig_dbias_slp(&mut self) -> DIG_DBIAS_SLP_W<'_>

Bits 8:10 - DBIAS during wakeup

pub fn sck_dcap_force(&mut self) -> SCK_DCAP_FORCE_W<'_>

Bit 7 - 150kHz tuning force

impl W<u32, Reg<u32, _APLL>>

pub fn block(&mut self) -> BLOCK_W<'_>

Bits 0:7 - Block

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 8:15 - Address

pub fn data(&mut self) -> DATA_W<'_>

Bits 16:23 - Data

pub fn write(&mut self) -> WRITE_W<'_>

Bit 24 - Write

pub fn busy(&mut self) -> BUSY_W<'_>

Bit 25 - Ready

impl W<u32, Reg<u32, _PLL>>

pub fn block(&mut self) -> BLOCK_W<'_>

Bits 0:7 - Block

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 8:15 - Address

pub fn data(&mut self) -> DATA_W<'_>

Bits 16:23 - Data

pub fn write(&mut self) -> WRITE_W<'_>

Bit 24 - Write

pub fn busy(&mut self) -> BUSY_W<'_>

Bit 25 - Ready

impl W<u32, Reg<u32, _SAR_READ_CTRL>>

pub fn sar1_data_inv(&mut self) -> SAR1_DATA_INV_W<'_>

Bit 28

pub fn sar1_dig_force(&mut self) -> SAR1_DIG_FORCE_W<'_>

Bit 27

pub fn sar1_sample_num(&mut self) -> SAR1_SAMPLE_NUM_W<'_>

Bits 19:26

pub fn sar1_clk_gated(&mut self) -> SAR1_CLK_GATED_W<'_>

Bit 18

pub fn sar1_sample_bit(&mut self) -> SAR1_SAMPLE_BIT_W<'_>

Bits 16:17

pub fn sar1_sample_cycle(&mut self) -> SAR1_SAMPLE_CYCLE_W<'_>

Bits 8:15

pub fn sar1_clk_div(&mut self) -> SAR1_CLK_DIV_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SAR_READ_STATUS1>>

pub fn sar1_reader_status(&mut self) -> SAR1_READER_STATUS_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SAR_MEAS_WAIT1>>

pub fn sar_amp_wait2(&mut self) -> SAR_AMP_WAIT2_W<'_>

Bits 16:31

pub fn sar_amp_wait1(&mut self) -> SAR_AMP_WAIT1_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_MEAS_WAIT2>>

pub fn sar2_rstb_wait(&mut self) -> SAR2_RSTB_WAIT_W<'_>

Bits 20:27

pub fn force_xpd_sar(&mut self) -> FORCE_XPD_SAR_W<'_>

Bits 18:19

pub fn force_xpd_amp(&mut self) -> FORCE_XPD_AMP_W<'_>

Bits 16:17

pub fn sar_amp_wait3(&mut self) -> SAR_AMP_WAIT3_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_MEAS_CTRL>>

pub fn sar2_xpd_wait(&mut self) -> SAR2_XPD_WAIT_W<'_>

Bits 24:31

pub fn sar_rstb_fsm(&mut self) -> SAR_RSTB_FSM_W<'_>

Bits 20:23

pub fn xpd_sar_fsm(&mut self) -> XPD_SAR_FSM_W<'_>

Bits 16:19

pub fn amp_short_ref_gnd_fsm(&mut self) -> AMP_SHORT_REF_GND_FSM_W<'_>

Bits 12:15

pub fn amp_short_ref_fsm(&mut self) -> AMP_SHORT_REF_FSM_W<'_>

Bits 8:11

pub fn amp_rst_fb_fsm(&mut self) -> AMP_RST_FB_FSM_W<'_>

Bits 4:7

pub fn xpd_sar_amp_fsm(&mut self) -> XPD_SAR_AMP_FSM_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _SAR_READ_STATUS2>>

pub fn sar2_reader_status(&mut self) -> SAR2_READER_STATUS_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _ULP_CP_SLEEP_CYC0>>

pub fn sleep_cycles_s0(&mut self) -> SLEEP_CYCLES_S0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _ULP_CP_SLEEP_CYC1>>

pub fn sleep_cycles_s1(&mut self) -> SLEEP_CYCLES_S1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _ULP_CP_SLEEP_CYC2>>

pub fn sleep_cycles_s2(&mut self) -> SLEEP_CYCLES_S2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _ULP_CP_SLEEP_CYC3>>

pub fn sleep_cycles_s3(&mut self) -> SLEEP_CYCLES_S3_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _ULP_CP_SLEEP_CYC4>>

pub fn sleep_cycles_s4(&mut self) -> SLEEP_CYCLES_S4_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SAR_START_FORCE>>

pub fn sar2_pwdet_en(&mut self) -> SAR2_PWDET_EN_W<'_>

Bit 24

pub fn sar1_stop(&mut self) -> SAR1_STOP_W<'_>

Bit 23

pub fn sar2_stop(&mut self) -> SAR2_STOP_W<'_>

Bit 22

pub fn pc_init(&mut self) -> PC_INIT_W<'_>

Bits 11:21

pub fn sarclk_en(&mut self) -> SARCLK_EN_W<'_>

Bit 10

pub fn ulp_cp_start_top(&mut self) -> ULP_CP_START_TOP_W<'_>

Bit 9

pub fn ulp_cp_force_start_top(&mut self) -> ULP_CP_FORCE_START_TOP_W<'_>

Bit 8

pub fn sar2_pwdet_cct(&mut self) -> SAR2_PWDET_CCT_W<'_>

Bits 5:7

pub fn sar2_en_test(&mut self) -> SAR2_EN_TEST_W<'_>

Bit 4

pub fn sar2_bit_width(&mut self) -> SAR2_BIT_WIDTH_W<'_>

Bits 2:3

pub fn sar1_bit_width(&mut self) -> SAR1_BIT_WIDTH_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SAR_MEM_WR_CTRL>>

pub fn rtc_mem_wr_offst_clr(&mut self) -> RTC_MEM_WR_OFFST_CLR_W<'_>

Bit 22

pub fn mem_wr_addr_size(&mut self) -> MEM_WR_ADDR_SIZE_W<'_>

Bits 11:21

pub fn mem_wr_addr_init(&mut self) -> MEM_WR_ADDR_INIT_W<'_>

Bits 0:10

impl W<u32, Reg<u32, _SAR_ATTEN1>>

pub fn sar1_atten(&mut self) -> SAR1_ATTEN_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SAR_ATTEN2>>

pub fn sar2_atten(&mut self) -> SAR2_ATTEN_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SAR_SLAVE_ADDR1>>

pub fn meas_status(&mut self) -> MEAS_STATUS_W<'_>

Bits 22:29

pub fn i2c_slave_addr0(&mut self) -> I2C_SLAVE_ADDR0_W<'_>

Bits 11:21

pub fn i2c_slave_addr1(&mut self) -> I2C_SLAVE_ADDR1_W<'_>

Bits 0:10

impl W<u32, Reg<u32, _SAR_SLAVE_ADDR2>>

pub fn i2c_slave_addr2(&mut self) -> I2C_SLAVE_ADDR2_W<'_>

Bits 11:21

pub fn i2c_slave_addr3(&mut self) -> I2C_SLAVE_ADDR3_W<'_>

Bits 0:10

impl W<u32, Reg<u32, _SAR_SLAVE_ADDR3>>

pub fn tsens_rdy_out(&mut self) -> TSENS_RDY_OUT_W<'_>

Bit 30

pub fn tsens_out(&mut self) -> TSENS_OUT_W<'_>

Bits 22:29

pub fn i2c_slave_addr4(&mut self) -> I2C_SLAVE_ADDR4_W<'_>

Bits 11:21

pub fn i2c_slave_addr5(&mut self) -> I2C_SLAVE_ADDR5_W<'_>

Bits 0:10

impl W<u32, Reg<u32, _SAR_SLAVE_ADDR4>>

pub fn i2c_done(&mut self) -> I2C_DONE_W<'_>

Bit 30

pub fn i2c_rdata(&mut self) -> I2C_RDATA_W<'_>

Bits 22:29

pub fn i2c_slave_addr6(&mut self) -> I2C_SLAVE_ADDR6_W<'_>

Bits 11:21

pub fn i2c_slave_addr7(&mut self) -> I2C_SLAVE_ADDR7_W<'_>

Bits 0:10

impl W<u32, Reg<u32, _SAR_TSENS_CTRL>>

pub fn tsens_dump_out(&mut self) -> TSENS_DUMP_OUT_W<'_>

Bit 26

pub fn tsens_power_up_force(&mut self) -> TSENS_POWER_UP_FORCE_W<'_>

Bit 25

pub fn tsens_power_up(&mut self) -> TSENS_POWER_UP_W<'_>

Bit 24

pub fn tsens_clk_div(&mut self) -> TSENS_CLK_DIV_W<'_>

Bits 16:23

pub fn tsens_in_inv(&mut self) -> TSENS_IN_INV_W<'_>

Bit 15

pub fn tsens_clk_gated(&mut self) -> TSENS_CLK_GATED_W<'_>

Bit 14

pub fn tsens_clk_inv(&mut self) -> TSENS_CLK_INV_W<'_>

Bit 13

pub fn tsens_xpd_force(&mut self) -> TSENS_XPD_FORCE_W<'_>

Bit 12

pub fn tsens_xpd_wait(&mut self) -> TSENS_XPD_WAIT_W<'_>

Bits 0:11

impl W<u32, Reg<u32, _SAR_I2C_CTRL>>

pub fn sar_i2c_start_force(&mut self) -> SAR_I2C_START_FORCE_W<'_>

Bit 29

pub fn sar_i2c_start(&mut self) -> SAR_I2C_START_W<'_>

Bit 28

pub fn sar_i2c_ctrl(&mut self) -> SAR_I2C_CTRL_W<'_>

Bits 0:27

impl W<u32, Reg<u32, _SAR_MEAS_START1>>

pub fn sar1_en_pad_force(&mut self) -> SAR1_EN_PAD_FORCE_W<'_>

Bit 31

pub fn sar1_en_pad(&mut self) -> SAR1_EN_PAD_W<'_>

Bits 19:30

pub fn meas1_start_force(&mut self) -> MEAS1_START_FORCE_W<'_>

Bit 18

pub fn meas1_start_sar(&mut self) -> MEAS1_START_SAR_W<'_>

Bit 17

pub fn meas1_done_sar(&mut self) -> MEAS1_DONE_SAR_W<'_>

Bit 16

pub fn meas1_data_sar(&mut self) -> MEAS1_DATA_SAR_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_TOUCH_CTRL1>>

pub fn hall_phase_force(&mut self) -> HALL_PHASE_FORCE_W<'_>

Bit 27

pub fn xpd_hall_force(&mut self) -> XPD_HALL_FORCE_W<'_>

Bit 26

pub fn touch_out_1en(&mut self) -> TOUCH_OUT_1EN_W<'_>

Bit 25

pub fn touch_out_sel(&mut self) -> TOUCH_OUT_SEL_W<'_>

Bit 24

pub fn touch_xpd_wait(&mut self) -> TOUCH_XPD_WAIT_W<'_>

Bits 16:23

pub fn touch_meas_delay(&mut self) -> TOUCH_MEAS_DELAY_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_TOUCH_THRES1>>

pub fn touch_out_th0(&mut self) -> TOUCH_OUT_TH0_W<'_>

Bits 16:31

pub fn touch_out_th1(&mut self) -> TOUCH_OUT_TH1_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_TOUCH_THRES2>>

pub fn touch_out_th2(&mut self) -> TOUCH_OUT_TH2_W<'_>

Bits 16:31

pub fn touch_out_th3(&mut self) -> TOUCH_OUT_TH3_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_TOUCH_THRES3>>

pub fn touch_out_th4(&mut self) -> TOUCH_OUT_TH4_W<'_>

Bits 16:31

pub fn touch_out_th5(&mut self) -> TOUCH_OUT_TH5_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_TOUCH_THRES4>>

pub fn touch_out_th6(&mut self) -> TOUCH_OUT_TH6_W<'_>

Bits 16:31

pub fn touch_out_th7(&mut self) -> TOUCH_OUT_TH7_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_TOUCH_THRES5>>

pub fn touch_out_th8(&mut self) -> TOUCH_OUT_TH8_W<'_>

Bits 16:31

pub fn touch_out_th9(&mut self) -> TOUCH_OUT_TH9_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_TOUCH_OUT1>>

pub fn touch_meas_out0(&mut self) -> TOUCH_MEAS_OUT0_W<'_>

Bits 16:31

pub fn touch_meas_out1(&mut self) -> TOUCH_MEAS_OUT1_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_TOUCH_OUT2>>

pub fn touch_meas_out2(&mut self) -> TOUCH_MEAS_OUT2_W<'_>

Bits 16:31

pub fn touch_meas_out3(&mut self) -> TOUCH_MEAS_OUT3_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_TOUCH_OUT3>>

pub fn touch_meas_out4(&mut self) -> TOUCH_MEAS_OUT4_W<'_>

Bits 16:31

pub fn touch_meas_out5(&mut self) -> TOUCH_MEAS_OUT5_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_TOUCH_OUT4>>

pub fn touch_meas_out6(&mut self) -> TOUCH_MEAS_OUT6_W<'_>

Bits 16:31

pub fn touch_meas_out7(&mut self) -> TOUCH_MEAS_OUT7_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_TOUCH_OUT5>>

pub fn touch_meas_out8(&mut self) -> TOUCH_MEAS_OUT8_W<'_>

Bits 16:31

pub fn touch_meas_out9(&mut self) -> TOUCH_MEAS_OUT9_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_TOUCH_CTRL2>>

pub fn touch_meas_en_clr(&mut self) -> TOUCH_MEAS_EN_CLR_W<'_>

Bit 30

pub fn touch_sleep_cycles(&mut self) -> TOUCH_SLEEP_CYCLES_W<'_>

Bits 14:29

pub fn touch_start_force(&mut self) -> TOUCH_START_FORCE_W<'_>

Bit 13

pub fn touch_start_en(&mut self) -> TOUCH_START_EN_W<'_>

Bit 12

pub fn touch_start_fsm_en(&mut self) -> TOUCH_START_FSM_EN_W<'_>

Bit 11

pub fn touch_meas_done(&mut self) -> TOUCH_MEAS_DONE_W<'_>

Bit 10

pub fn touch_meas_en(&mut self) -> TOUCH_MEAS_EN_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _SAR_TOUCH_ENABLE>>

pub fn touch_pad_outen1(&mut self) -> TOUCH_PAD_OUTEN1_W<'_>

Bits 20:29

pub fn touch_pad_outen2(&mut self) -> TOUCH_PAD_OUTEN2_W<'_>

Bits 10:19

pub fn touch_pad_worken(&mut self) -> TOUCH_PAD_WORKEN_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _SAR_READ_CTRL2>>

pub fn sar2_data_inv(&mut self) -> SAR2_DATA_INV_W<'_>

Bit 29

pub fn sar2_dig_force(&mut self) -> SAR2_DIG_FORCE_W<'_>

Bit 28

pub fn sar2_pwdet_force(&mut self) -> SAR2_PWDET_FORCE_W<'_>

Bit 27

pub fn sar2_sample_num(&mut self) -> SAR2_SAMPLE_NUM_W<'_>

Bits 19:26

pub fn sar2_clk_gated(&mut self) -> SAR2_CLK_GATED_W<'_>

Bit 18

pub fn sar2_sample_bit(&mut self) -> SAR2_SAMPLE_BIT_W<'_>

Bits 16:17

pub fn sar2_sample_cycle(&mut self) -> SAR2_SAMPLE_CYCLE_W<'_>

Bits 8:15

pub fn sar2_clk_div(&mut self) -> SAR2_CLK_DIV_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SAR_MEAS_START2>>

pub fn sar2_en_pad_force(&mut self) -> SAR2_EN_PAD_FORCE_W<'_>

Bit 31

pub fn sar2_en_pad(&mut self) -> SAR2_EN_PAD_W<'_>

Bits 19:30

pub fn meas2_start_force(&mut self) -> MEAS2_START_FORCE_W<'_>

Bit 18

pub fn meas2_start_sar(&mut self) -> MEAS2_START_SAR_W<'_>

Bit 17

pub fn meas2_done_sar(&mut self) -> MEAS2_DONE_SAR_W<'_>

Bit 16

pub fn meas2_data_sar(&mut self) -> MEAS2_DATA_SAR_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_DAC_CTRL1>>

pub fn dac_clk_inv(&mut self) -> DAC_CLK_INV_W<'_>

Bit 25

pub fn dac_clk_force_high(&mut self) -> DAC_CLK_FORCE_HIGH_W<'_>

Bit 24

pub fn dac_clk_force_low(&mut self) -> DAC_CLK_FORCE_LOW_W<'_>

Bit 23

pub fn dac_dig_force(&mut self) -> DAC_DIG_FORCE_W<'_>

Bit 22

pub fn debug_bit_sel(&mut self) -> DEBUG_BIT_SEL_W<'_>

Bits 17:21

pub fn sw_tone_en(&mut self) -> SW_TONE_EN_W<'_>

Bit 16

pub fn sw_fstep(&mut self) -> SW_FSTEP_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _SAR_DAC_CTRL2>>

pub fn dac_cw_en2(&mut self) -> DAC_CW_EN2_W<'_>

Bit 25

pub fn dac_cw_en1(&mut self) -> DAC_CW_EN1_W<'_>

Bit 24

pub fn dac_inv2(&mut self) -> DAC_INV2_W<'_>

Bits 22:23

pub fn dac_inv1(&mut self) -> DAC_INV1_W<'_>

Bits 20:21

pub fn dac_scale2(&mut self) -> DAC_SCALE2_W<'_>

Bits 18:19

pub fn dac_scale1(&mut self) -> DAC_SCALE1_W<'_>

Bits 16:17

pub fn dac_dc2(&mut self) -> DAC_DC2_W<'_>

Bits 8:15

pub fn dac_dc1(&mut self) -> DAC_DC1_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SAR_MEAS_CTRL2>>

pub fn amp_short_ref_gnd_force(&mut self) -> AMP_SHORT_REF_GND_FORCE_W<'_>

Bits 17:18

pub fn amp_short_ref_force(&mut self) -> AMP_SHORT_REF_FORCE_W<'_>

Bits 15:16

pub fn amp_rst_fb_force(&mut self) -> AMP_RST_FB_FORCE_W<'_>

Bits 13:14

pub fn sar2_rstb_force(&mut self) -> SAR2_RSTB_FORCE_W<'_>

Bits 11:12

pub fn sar_rstb_fsm_idle(&mut self) -> SAR_RSTB_FSM_IDLE_W<'_>

Bit 10

pub fn xpd_sar_fsm_idle(&mut self) -> XPD_SAR_FSM_IDLE_W<'_>

Bit 9

pub fn amp_short_ref_gnd_fsm_idle(&mut self) -> AMP_SHORT_REF_GND_FSM_IDLE_W<'_>

Bit 8

pub fn amp_short_ref_fsm_idle(&mut self) -> AMP_SHORT_REF_FSM_IDLE_W<'_>

Bit 7

pub fn amp_rst_fb_fsm_idle(&mut self) -> AMP_RST_FB_FSM_IDLE_W<'_>

Bit 6

pub fn xpd_sar_amp_fsm_idle(&mut self) -> XPD_SAR_AMP_FSM_IDLE_W<'_>

Bit 5

pub fn sar1_dac_xpd_fsm_idle(&mut self) -> SAR1_DAC_XPD_FSM_IDLE_W<'_>

Bit 4

pub fn sar1_dac_xpd_fsm(&mut self) -> SAR1_DAC_XPD_FSM_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _SAR_NOUSE>>

pub fn sar_nouse(&mut self) -> SAR_NOUSE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SARDATE>>

pub fn sar_date(&mut self) -> SAR_DATE_W<'_>

Bits 0:27

impl W<u32, Reg<u32, _OUT>>

pub fn out_data(&mut self) -> OUT_DATA_W<'_>

Bits 14:31

impl W<u32, Reg<u32, _OUT_W1TS>>

pub fn out_data_w1ts(&mut self) -> OUT_DATA_W1TS_W<'_>

Bits 14:31

impl W<u32, Reg<u32, _OUT_W1TC>>

pub fn out_data_w1tc(&mut self) -> OUT_DATA_W1TC_W<'_>

Bits 14:31

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bits 14:31

impl W<u32, Reg<u32, _ENABLE_W1TS>>

pub fn enable_w1ts(&mut self) -> ENABLE_W1TS_W<'_>

Bits 14:31

impl W<u32, Reg<u32, _ENABLE_W1TC>>

pub fn enable_w1tc(&mut self) -> ENABLE_W1TC_W<'_>

Bits 14:31

impl W<u32, Reg<u32, _STATUS>>

pub fn status_int(&mut self) -> STATUS_INT_W<'_>

Bits 14:31

impl W<u32, Reg<u32, _STATUS_W1TS>>

pub fn status_int_w1ts(&mut self) -> STATUS_INT_W1TS_W<'_>

Bits 14:31

impl W<u32, Reg<u32, _STATUS_W1TC>>

pub fn status_int_w1tc(&mut self) -> STATUS_INT_W1TC_W<'_>

Bits 14:31

impl W<u32, Reg<u32, _IN>>

pub fn in_next(&mut self) -> IN_NEXT_W<'_>

Bits 14:31

impl W<u32, Reg<u32, _PIN>>

pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_>

Bit 10

pub fn int_type(&mut self) -> INT_TYPE_W<'_>

Bits 7:9

pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_>

Bit 2

impl W<u32, Reg<u32, _RTC_DEBUG_SEL>>

pub fn debug_12m_no_gating(&mut self) -> DEBUG_12M_NO_GATING_W<'_>

Bit 25

pub fn debug_sel4(&mut self) -> DEBUG_SEL4_W<'_>

Bits 20:24

pub fn debug_sel3(&mut self) -> DEBUG_SEL3_W<'_>

Bits 15:19

pub fn debug_sel2(&mut self) -> DEBUG_SEL2_W<'_>

Bits 10:14

pub fn debug_sel1(&mut self) -> DEBUG_SEL1_W<'_>

Bits 5:9

pub fn debug_sel0(&mut self) -> DEBUG_SEL0_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _DIG_PAD_HOLD>>

pub fn dig_pad_hold(&mut self) -> DIG_PAD_HOLD_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _HALL_SENS>>

pub fn xpd_hall(&mut self) -> XPD_HALL_W<'_>

Bit 31

pub fn hall_phase(&mut self) -> HALL_PHASE_W<'_>

Bit 30

impl W<u32, Reg<u32, _SENSOR_PADS>>

pub fn sense1_hold(&mut self) -> SENSE1_HOLD_W<'_>

Bit 31

pub fn sense2_hold(&mut self) -> SENSE2_HOLD_W<'_>

Bit 30

pub fn sense3_hold(&mut self) -> SENSE3_HOLD_W<'_>

Bit 29

pub fn sense4_hold(&mut self) -> SENSE4_HOLD_W<'_>

Bit 28

pub fn sense1_mux_sel(&mut self) -> SENSE1_MUX_SEL_W<'_>

Bit 27

pub fn sense2_mux_sel(&mut self) -> SENSE2_MUX_SEL_W<'_>

Bit 26

pub fn sense3_mux_sel(&mut self) -> SENSE3_MUX_SEL_W<'_>

Bit 25

pub fn sense4_mux_sel(&mut self) -> SENSE4_MUX_SEL_W<'_>

Bit 24

pub fn sense1_fun_sel(&mut self) -> SENSE1_FUN_SEL_W<'_>

Bits 22:23

pub fn sense1_slp_sel(&mut self) -> SENSE1_SLP_SEL_W<'_>

Bit 21

pub fn sense1_slp_ie(&mut self) -> SENSE1_SLP_IE_W<'_>

Bit 20

pub fn sense1_fun_ie(&mut self) -> SENSE1_FUN_IE_W<'_>

Bit 19

pub fn sense2_fun_sel(&mut self) -> SENSE2_FUN_SEL_W<'_>

Bits 17:18

pub fn sense2_slp_sel(&mut self) -> SENSE2_SLP_SEL_W<'_>

Bit 16

pub fn sense2_slp_ie(&mut self) -> SENSE2_SLP_IE_W<'_>

Bit 15

pub fn sense2_fun_ie(&mut self) -> SENSE2_FUN_IE_W<'_>

Bit 14

pub fn sense3_fun_sel(&mut self) -> SENSE3_FUN_SEL_W<'_>

Bits 12:13

pub fn sense3_slp_sel(&mut self) -> SENSE3_SLP_SEL_W<'_>

Bit 11

pub fn sense3_slp_ie(&mut self) -> SENSE3_SLP_IE_W<'_>

Bit 10

pub fn sense3_fun_ie(&mut self) -> SENSE3_FUN_IE_W<'_>

Bit 9

pub fn sense4_fun_sel(&mut self) -> SENSE4_FUN_SEL_W<'_>

Bits 7:8

pub fn sense4_slp_sel(&mut self) -> SENSE4_SLP_SEL_W<'_>

Bit 6

pub fn sense4_slp_ie(&mut self) -> SENSE4_SLP_IE_W<'_>

Bit 5

pub fn sense4_fun_ie(&mut self) -> SENSE4_FUN_IE_W<'_>

Bit 4

impl W<u32, Reg<u32, _ADC_PAD>>

pub fn adc1_hold(&mut self) -> ADC1_HOLD_W<'_>

Bit 31

pub fn adc2_hold(&mut self) -> ADC2_HOLD_W<'_>

Bit 30

pub fn adc1_mux_sel(&mut self) -> ADC1_MUX_SEL_W<'_>

Bit 29

pub fn adc2_mux_sel(&mut self) -> ADC2_MUX_SEL_W<'_>

Bit 28

pub fn adc1_fun_sel(&mut self) -> ADC1_FUN_SEL_W<'_>

Bits 26:27

pub fn adc1_slp_sel(&mut self) -> ADC1_SLP_SEL_W<'_>

Bit 25

pub fn adc1_slp_ie(&mut self) -> ADC1_SLP_IE_W<'_>

Bit 24

pub fn adc1_fun_ie(&mut self) -> ADC1_FUN_IE_W<'_>

Bit 23

pub fn adc2_fun_sel(&mut self) -> ADC2_FUN_SEL_W<'_>

Bits 21:22

pub fn adc2_slp_sel(&mut self) -> ADC2_SLP_SEL_W<'_>

Bit 20

pub fn adc2_slp_ie(&mut self) -> ADC2_SLP_IE_W<'_>

Bit 19

pub fn adc2_fun_ie(&mut self) -> ADC2_FUN_IE_W<'_>

Bit 18

impl W<u32, Reg<u32, _PAD_DAC1>>

pub fn pdac1_drv(&mut self) -> PDAC1_DRV_W<'_>

Bits 30:31

pub fn pdac1_hold(&mut self) -> PDAC1_HOLD_W<'_>

Bit 29

pub fn pdac1_rde(&mut self) -> PDAC1_RDE_W<'_>

Bit 28

pub fn pdac1_rue(&mut self) -> PDAC1_RUE_W<'_>

Bit 27

pub fn pdac1_dac(&mut self) -> PDAC1_DAC_W<'_>

Bits 19:26

pub fn pdac1_xpd_dac(&mut self) -> PDAC1_XPD_DAC_W<'_>

Bit 18

pub fn pdac1_mux_sel(&mut self) -> PDAC1_MUX_SEL_W<'_>

Bit 17

pub fn pdac1_fun_sel(&mut self) -> PDAC1_FUN_SEL_W<'_>

Bits 15:16

pub fn pdac1_slp_sel(&mut self) -> PDAC1_SLP_SEL_W<'_>

Bit 14

pub fn pdac1_slp_ie(&mut self) -> PDAC1_SLP_IE_W<'_>

Bit 13

pub fn pdac1_slp_oe(&mut self) -> PDAC1_SLP_OE_W<'_>

Bit 12

pub fn pdac1_fun_ie(&mut self) -> PDAC1_FUN_IE_W<'_>

Bit 11

pub fn pdac1_dac_xpd_force(&mut self) -> PDAC1_DAC_XPD_FORCE_W<'_>

Bit 10

impl W<u32, Reg<u32, _PAD_DAC2>>

pub fn pdac2_drv(&mut self) -> PDAC2_DRV_W<'_>

Bits 30:31

pub fn pdac2_hold(&mut self) -> PDAC2_HOLD_W<'_>

Bit 29

pub fn pdac2_rde(&mut self) -> PDAC2_RDE_W<'_>

Bit 28

pub fn pdac2_rue(&mut self) -> PDAC2_RUE_W<'_>

Bit 27

pub fn pdac2_dac(&mut self) -> PDAC2_DAC_W<'_>

Bits 19:26

pub fn pdac2_xpd_dac(&mut self) -> PDAC2_XPD_DAC_W<'_>

Bit 18

pub fn pdac2_mux_sel(&mut self) -> PDAC2_MUX_SEL_W<'_>

Bit 17

pub fn pdac2_fun_sel(&mut self) -> PDAC2_FUN_SEL_W<'_>

Bits 15:16

pub fn pdac2_slp_sel(&mut self) -> PDAC2_SLP_SEL_W<'_>

Bit 14

pub fn pdac2_slp_ie(&mut self) -> PDAC2_SLP_IE_W<'_>

Bit 13

pub fn pdac2_slp_oe(&mut self) -> PDAC2_SLP_OE_W<'_>

Bit 12

pub fn pdac2_fun_ie(&mut self) -> PDAC2_FUN_IE_W<'_>

Bit 11

pub fn pdac2_dac_xpd_force(&mut self) -> PDAC2_DAC_XPD_FORCE_W<'_>

Bit 10

impl W<u32, Reg<u32, _XTAL_32K_PAD>>

pub fn x32n_drv(&mut self) -> X32N_DRV_W<'_>

Bits 30:31

pub fn x32n_hold(&mut self) -> X32N_HOLD_W<'_>

Bit 29

pub fn x32n_rde(&mut self) -> X32N_RDE_W<'_>

Bit 28

pub fn x32n_rue(&mut self) -> X32N_RUE_W<'_>

Bit 27

pub fn x32p_drv(&mut self) -> X32P_DRV_W<'_>

Bits 25:26

pub fn x32p_hold(&mut self) -> X32P_HOLD_W<'_>

Bit 24

pub fn x32p_rde(&mut self) -> X32P_RDE_W<'_>

Bit 23

pub fn x32p_rue(&mut self) -> X32P_RUE_W<'_>

Bit 22

pub fn dac_xtal_32k(&mut self) -> DAC_XTAL_32K_W<'_>

Bits 20:21

pub fn xpd_xtal_32k(&mut self) -> XPD_XTAL_32K_W<'_>

Bit 19

pub fn x32n_mux_sel(&mut self) -> X32N_MUX_SEL_W<'_>

Bit 18

pub fn x32p_mux_sel(&mut self) -> X32P_MUX_SEL_W<'_>

Bit 17

pub fn x32n_fun_sel(&mut self) -> X32N_FUN_SEL_W<'_>

Bits 15:16

pub fn x32n_slp_sel(&mut self) -> X32N_SLP_SEL_W<'_>

Bit 14

pub fn x32n_slp_ie(&mut self) -> X32N_SLP_IE_W<'_>

Bit 13

pub fn x32n_slp_oe(&mut self) -> X32N_SLP_OE_W<'_>

Bit 12

pub fn x32n_fun_ie(&mut self) -> X32N_FUN_IE_W<'_>

Bit 11

pub fn x32p_fun_sel(&mut self) -> X32P_FUN_SEL_W<'_>

Bits 9:10

pub fn x32p_slp_sel(&mut self) -> X32P_SLP_SEL_W<'_>

Bit 8

pub fn x32p_slp_ie(&mut self) -> X32P_SLP_IE_W<'_>

Bit 7

pub fn x32p_slp_oe(&mut self) -> X32P_SLP_OE_W<'_>

Bit 6

pub fn x32p_fun_ie(&mut self) -> X32P_FUN_IE_W<'_>

Bit 5

pub fn dres_xtal_32k(&mut self) -> DRES_XTAL_32K_W<'_>

Bits 3:4

pub fn dbias_xtal_32k(&mut self) -> DBIAS_XTAL_32K_W<'_>

Bits 1:2

impl W<u32, Reg<u32, _TOUCH_CFG>>

pub fn touch_xpd_bias(&mut self) -> TOUCH_XPD_BIAS_W<'_>

Bit 31

pub fn touch_drefh(&mut self) -> TOUCH_DREFH_W<'_>

Bits 29:30

pub fn touch_drefl(&mut self) -> TOUCH_DREFL_W<'_>

Bits 27:28

pub fn touch_drange(&mut self) -> TOUCH_DRANGE_W<'_>

Bits 25:26

pub fn touch_dcur(&mut self) -> TOUCH_DCUR_W<'_>

Bits 23:24

impl W<u32, Reg<u32, _TOUCH_PAD0>>

pub fn hold(&mut self) -> HOLD_W<'_>

Bit 31

pub fn drv(&mut self) -> DRV_W<'_>

Bits 29:30

pub fn rde(&mut self) -> RDE_W<'_>

Bit 28

pub fn rue(&mut self) -> RUE_W<'_>

Bit 27

pub fn dac(&mut self) -> DAC_W<'_>

Bits 23:25

pub fn start(&mut self) -> START_W<'_>

Bit 22

pub fn tie_opt(&mut self) -> TIE_OPT_W<'_>

Bit 21

pub fn xpd(&mut self) -> XPD_W<'_>

Bit 20

pub fn mux_sel(&mut self) -> MUX_SEL_W<'_>

Bit 19

pub fn fun_sel(&mut self) -> FUN_SEL_W<'_>

Bits 17:18

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 16

pub fn slp_ie(&mut self) -> SLP_IE_W<'_>

Bit 15

pub fn slp_oe(&mut self) -> SLP_OE_W<'_>

Bit 14

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 13

pub fn to_gpio(&mut self) -> TO_GPIO_W<'_>

Bit 12

impl W<u32, Reg<u32, _TOUCH_PAD1>>

pub fn hold(&mut self) -> HOLD_W<'_>

Bit 31

pub fn drv(&mut self) -> DRV_W<'_>

Bits 29:30

pub fn rde(&mut self) -> RDE_W<'_>

Bit 28

pub fn rue(&mut self) -> RUE_W<'_>

Bit 27

pub fn dac(&mut self) -> DAC_W<'_>

Bits 23:25

pub fn start(&mut self) -> START_W<'_>

Bit 22

pub fn tie_opt(&mut self) -> TIE_OPT_W<'_>

Bit 21

pub fn xpd(&mut self) -> XPD_W<'_>

Bit 20

pub fn mux_sel(&mut self) -> MUX_SEL_W<'_>

Bit 19

pub fn fun_sel(&mut self) -> FUN_SEL_W<'_>

Bits 17:18

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 16

pub fn slp_ie(&mut self) -> SLP_IE_W<'_>

Bit 15

pub fn slp_oe(&mut self) -> SLP_OE_W<'_>

Bit 14

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 13

pub fn to_gpio(&mut self) -> TO_GPIO_W<'_>

Bit 12

impl W<u32, Reg<u32, _TOUCH_PAD2>>

pub fn hold(&mut self) -> HOLD_W<'_>

Bit 31

pub fn drv(&mut self) -> DRV_W<'_>

Bits 29:30

pub fn rde(&mut self) -> RDE_W<'_>

Bit 28

pub fn rue(&mut self) -> RUE_W<'_>

Bit 27

pub fn dac(&mut self) -> DAC_W<'_>

Bits 23:25

pub fn start(&mut self) -> START_W<'_>

Bit 22

pub fn tie_opt(&mut self) -> TIE_OPT_W<'_>

Bit 21

pub fn xpd(&mut self) -> XPD_W<'_>

Bit 20

pub fn mux_sel(&mut self) -> MUX_SEL_W<'_>

Bit 19

pub fn fun_sel(&mut self) -> FUN_SEL_W<'_>

Bits 17:18

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 16

pub fn slp_ie(&mut self) -> SLP_IE_W<'_>

Bit 15

pub fn slp_oe(&mut self) -> SLP_OE_W<'_>

Bit 14

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 13

pub fn to_gpio(&mut self) -> TO_GPIO_W<'_>

Bit 12

impl W<u32, Reg<u32, _TOUCH_PAD3>>

pub fn hold(&mut self) -> HOLD_W<'_>

Bit 31

pub fn drv(&mut self) -> DRV_W<'_>

Bits 29:30

pub fn rde(&mut self) -> RDE_W<'_>

Bit 28

pub fn rue(&mut self) -> RUE_W<'_>

Bit 27

pub fn dac(&mut self) -> DAC_W<'_>

Bits 23:25

pub fn start(&mut self) -> START_W<'_>

Bit 22

pub fn tie_opt(&mut self) -> TIE_OPT_W<'_>

Bit 21

pub fn xpd(&mut self) -> XPD_W<'_>

Bit 20

pub fn mux_sel(&mut self) -> MUX_SEL_W<'_>

Bit 19

pub fn fun_sel(&mut self) -> FUN_SEL_W<'_>

Bits 17:18

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 16

pub fn slp_ie(&mut self) -> SLP_IE_W<'_>

Bit 15

pub fn slp_oe(&mut self) -> SLP_OE_W<'_>

Bit 14

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 13

pub fn to_gpio(&mut self) -> TO_GPIO_W<'_>

Bit 12

impl W<u32, Reg<u32, _TOUCH_PAD4>>

pub fn hold(&mut self) -> HOLD_W<'_>

Bit 31

pub fn drv(&mut self) -> DRV_W<'_>

Bits 29:30

pub fn rde(&mut self) -> RDE_W<'_>

Bit 28

pub fn rue(&mut self) -> RUE_W<'_>

Bit 27

pub fn dac(&mut self) -> DAC_W<'_>

Bits 23:25

pub fn start(&mut self) -> START_W<'_>

Bit 22

pub fn tie_opt(&mut self) -> TIE_OPT_W<'_>

Bit 21

pub fn xpd(&mut self) -> XPD_W<'_>

Bit 20

pub fn mux_sel(&mut self) -> MUX_SEL_W<'_>

Bit 19

pub fn fun_sel(&mut self) -> FUN_SEL_W<'_>

Bits 17:18

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 16

pub fn slp_ie(&mut self) -> SLP_IE_W<'_>

Bit 15

pub fn slp_oe(&mut self) -> SLP_OE_W<'_>

Bit 14

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 13

pub fn to_gpio(&mut self) -> TO_GPIO_W<'_>

Bit 12

impl W<u32, Reg<u32, _TOUCH_PAD5>>

pub fn hold(&mut self) -> HOLD_W<'_>

Bit 31

pub fn drv(&mut self) -> DRV_W<'_>

Bits 29:30

pub fn rde(&mut self) -> RDE_W<'_>

Bit 28

pub fn rue(&mut self) -> RUE_W<'_>

Bit 27

pub fn dac(&mut self) -> DAC_W<'_>

Bits 23:25

pub fn start(&mut self) -> START_W<'_>

Bit 22

pub fn tie_opt(&mut self) -> TIE_OPT_W<'_>

Bit 21

pub fn xpd(&mut self) -> XPD_W<'_>

Bit 20

pub fn mux_sel(&mut self) -> MUX_SEL_W<'_>

Bit 19

pub fn fun_sel(&mut self) -> FUN_SEL_W<'_>

Bits 17:18

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 16

pub fn slp_ie(&mut self) -> SLP_IE_W<'_>

Bit 15

pub fn slp_oe(&mut self) -> SLP_OE_W<'_>

Bit 14

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 13

pub fn to_gpio(&mut self) -> TO_GPIO_W<'_>

Bit 12

impl W<u32, Reg<u32, _TOUCH_PAD6>>

pub fn hold(&mut self) -> HOLD_W<'_>

Bit 31

pub fn drv(&mut self) -> DRV_W<'_>

Bits 29:30

pub fn rde(&mut self) -> RDE_W<'_>

Bit 28

pub fn rue(&mut self) -> RUE_W<'_>

Bit 27

pub fn dac(&mut self) -> DAC_W<'_>

Bits 23:25

pub fn start(&mut self) -> START_W<'_>

Bit 22

pub fn tie_opt(&mut self) -> TIE_OPT_W<'_>

Bit 21

pub fn xpd(&mut self) -> XPD_W<'_>

Bit 20

pub fn mux_sel(&mut self) -> MUX_SEL_W<'_>

Bit 19

pub fn fun_sel(&mut self) -> FUN_SEL_W<'_>

Bits 17:18

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 16

pub fn slp_ie(&mut self) -> SLP_IE_W<'_>

Bit 15

pub fn slp_oe(&mut self) -> SLP_OE_W<'_>

Bit 14

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 13

pub fn to_gpio(&mut self) -> TO_GPIO_W<'_>

Bit 12

impl W<u32, Reg<u32, _TOUCH_PAD7>>

pub fn hold(&mut self) -> HOLD_W<'_>

Bit 31

pub fn drv(&mut self) -> DRV_W<'_>

Bits 29:30

pub fn rde(&mut self) -> RDE_W<'_>

Bit 28

pub fn rue(&mut self) -> RUE_W<'_>

Bit 27

pub fn dac(&mut self) -> DAC_W<'_>

Bits 23:25

pub fn start(&mut self) -> START_W<'_>

Bit 22

pub fn tie_opt(&mut self) -> TIE_OPT_W<'_>

Bit 21

pub fn xpd(&mut self) -> XPD_W<'_>

Bit 20

pub fn mux_sel(&mut self) -> MUX_SEL_W<'_>

Bit 19

pub fn fun_sel(&mut self) -> FUN_SEL_W<'_>

Bits 17:18

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 16

pub fn slp_ie(&mut self) -> SLP_IE_W<'_>

Bit 15

pub fn slp_oe(&mut self) -> SLP_OE_W<'_>

Bit 14

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 13

pub fn to_gpio(&mut self) -> TO_GPIO_W<'_>

Bit 12

impl W<u32, Reg<u32, _TOUCH_PAD8>>

pub fn dac(&mut self) -> DAC_W<'_>

Bits 23:25

pub fn start(&mut self) -> START_W<'_>

Bit 22

pub fn tie_opt(&mut self) -> TIE_OPT_W<'_>

Bit 21

pub fn xpd(&mut self) -> XPD_W<'_>

Bit 20

pub fn to_gpio(&mut self) -> TO_GPIO_W<'_>

Bit 19

impl W<u32, Reg<u32, _TOUCH_PAD9>>

pub fn dac(&mut self) -> DAC_W<'_>

Bits 23:25

pub fn start(&mut self) -> START_W<'_>

Bit 22

pub fn tie_opt(&mut self) -> TIE_OPT_W<'_>

Bit 21

pub fn xpd(&mut self) -> XPD_W<'_>

Bit 20

pub fn to_gpio(&mut self) -> TO_GPIO_W<'_>

Bit 19

impl W<u32, Reg<u32, _EXT_WAKEUP0>>

pub fn ext_wakeup0_sel(&mut self) -> EXT_WAKEUP0_SEL_W<'_>

Bits 27:31

impl W<u32, Reg<u32, _XTL_EXT_CTR>>

pub fn xtl_ext_ctr_sel(&mut self) -> XTL_EXT_CTR_SEL_W<'_>

Bits 27:31

impl W<u32, Reg<u32, _SAR_I2C_IO>>

pub fn sar_i2c_sda_sel(&mut self) -> SAR_I2C_SDA_SEL_W<'_>

Bits 30:31

pub fn sar_i2c_scl_sel(&mut self) -> SAR_I2C_SCL_SEL_W<'_>

Bits 28:29

pub fn sar_debug_bit_sel(&mut self) -> SAR_DEBUG_BIT_SEL_W<'_>

Bits 23:27

impl W<u32, Reg<u32, _DATE>>

pub fn io_date(&mut self) -> IO_DATE_W<'_>

Bits 0:27

impl W<u32, Reg<u32, _PRO_BOOT_REMAP_CTRL>>

pub fn pro_boot_remap(&mut self) -> PRO_BOOT_REMAP_W<'_>

Bit 0

impl W<u32, Reg<u32, _APP_BOOT_REMAP_CTRL>>

pub fn app_boot_remap(&mut self) -> APP_BOOT_REMAP_W<'_>

Bit 0

impl W<u32, Reg<u32, _ACCESS_CHECK>>

pub fn access_check_app(&mut self) -> ACCESS_CHECK_APP_W<'_>

Bit 8

pub fn access_check_pro(&mut self) -> ACCESS_CHECK_PRO_W<'_>

Bit 0

impl W<u32, Reg<u32, _PRO_DPORT_APB_MASK0>>

pub fn prodport_apb_mask0(&mut self) -> PRODPORT_APB_MASK0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _PRO_DPORT_APB_MASK1>>

pub fn prodport_apb_mask1(&mut self) -> PRODPORT_APB_MASK1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APP_DPORT_APB_MASK0>>

pub fn appdport_apb_mask0(&mut self) -> APPDPORT_APB_MASK0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APP_DPORT_APB_MASK1>>

pub fn appdport_apb_mask1(&mut self) -> APPDPORT_APB_MASK1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _PERI_CLK_EN>>

pub fn peri_clk_en(&mut self) -> PERI_CLK_EN_W<'_>

Bits 0:31

pub fn digital_signature(&mut self) -> DIGITAL_SIGNATURE_W<'_>

Bit 4

pub fn secure_boot(&mut self) -> SECURE_BOOT_W<'_>

Bit 3

pub fn rsa_accelerator(&mut self) -> RSA_ACCELERATOR_W<'_>

Bit 2

pub fn sha_accelerator(&mut self) -> SHA_ACCELERATOR_W<'_>

Bit 1

pub fn aes_accelerator(&mut self) -> AES_ACCELERATOR_W<'_>

Bit 0

impl W<u32, Reg<u32, _PERI_RST_EN>>

pub fn peri_rst_en(&mut self) -> PERI_RST_EN_W<'_>

Bits 0:31

pub fn digital_signature(&mut self) -> DIGITAL_SIGNATURE_W<'_>

Bit 4

pub fn secure_boot(&mut self) -> SECURE_BOOT_W<'_>

Bit 3

pub fn rsa_accelerator(&mut self) -> RSA_ACCELERATOR_W<'_>

Bit 2

pub fn sha_accelerator(&mut self) -> SHA_ACCELERATOR_W<'_>

Bit 1

pub fn aes_accelerator(&mut self) -> AES_ACCELERATOR_W<'_>

Bit 0

impl W<u32, Reg<u32, _WIFI_BB_CFG>>

pub fn wifi_bb_cfg(&mut self) -> WIFI_BB_CFG_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _WIFI_BB_CFG_2>>

pub fn wifi_bb_cfg_2(&mut self) -> WIFI_BB_CFG_2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APPCPU_CTRL_A>>

pub fn appcpu_resetting(&mut self) -> APPCPU_RESETTING_W<'_>

Bit 0

impl W<u32, Reg<u32, _APPCPU_CTRL_B>>

pub fn appcpu_clkgate_en(&mut self) -> APPCPU_CLKGATE_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _APPCPU_CTRL_C>>

pub fn appcpu_runstall(&mut self) -> APPCPU_RUNSTALL_W<'_>

Bit 0

impl W<u32, Reg<u32, _APPCPU_CTRL_D>>

pub fn appcpu_boot_addr(&mut self) -> APPCPU_BOOT_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CPU_PER_CONF>>

pub fn fast_clk_rtc_sel(&mut self) -> FAST_CLK_RTC_SEL_W<'_>

Bit 3

pub fn lowspeed_clk_sel(&mut self) -> LOWSPEED_CLK_SEL_W<'_>

Bit 2

pub fn cpuperiod_sel(&mut self) -> CPUPERIOD_SEL_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _PRO_CACHE_CTRL>>

pub fn pro_dram_hl(&mut self) -> PRO_DRAM_HL_W<'_>

Bit 16

pub fn slave_req(&mut self) -> SLAVE_REQ_W<'_>

Bit 15

pub fn ahb_spi_req(&mut self) -> AHB_SPI_REQ_W<'_>

Bit 14

pub fn pro_slave_req(&mut self) -> PRO_SLAVE_REQ_W<'_>

Bit 13

pub fn pro_ahb_spi_req(&mut self) -> PRO_AHB_SPI_REQ_W<'_>

Bit 12

pub fn pro_dram_split(&mut self) -> PRO_DRAM_SPLIT_W<'_>

Bit 11

pub fn pro_single_iram_ena(&mut self) -> PRO_SINGLE_IRAM_ENA_W<'_>

Bit 10

pub fn pro_cache_lock_3_en(&mut self) -> PRO_CACHE_LOCK_3_EN_W<'_>

Bit 9

pub fn pro_cache_lock_2_en(&mut self) -> PRO_CACHE_LOCK_2_EN_W<'_>

Bit 8

pub fn pro_cache_lock_1_en(&mut self) -> PRO_CACHE_LOCK_1_EN_W<'_>

Bit 7

pub fn pro_cache_lock_0_en(&mut self) -> PRO_CACHE_LOCK_0_EN_W<'_>

Bit 6

pub fn pro_cache_flush_done(&mut self) -> PRO_CACHE_FLUSH_DONE_W<'_>

Bit 5

pub fn pro_cache_flush_ena(&mut self) -> PRO_CACHE_FLUSH_ENA_W<'_>

Bit 4

pub fn pro_cache_enable(&mut self) -> PRO_CACHE_ENABLE_W<'_>

Bit 3

pub fn pro_cache_mode(&mut self) -> PRO_CACHE_MODE_W<'_>

Bit 2

impl W<u32, Reg<u32, _PRO_CACHE_CTRL1>>

pub fn pro_cache_mmu_ia_clr(&mut self) -> PRO_CACHE_MMU_IA_CLR_W<'_>

Bit 13

pub fn pro_cmmu_pd(&mut self) -> PRO_CMMU_PD_W<'_>

Bit 12

pub fn pro_cmmu_force_on(&mut self) -> PRO_CMMU_FORCE_ON_W<'_>

Bit 11

pub fn pro_cmmu_flash_page_mode(&mut self) -> PRO_CMMU_FLASH_PAGE_MODE_W<'_>

Bits 9:10

pub fn pro_cmmu_sram_page_mode(&mut self) -> PRO_CMMU_SRAM_PAGE_MODE_W<'_>

Bits 6:8

pub fn pro_cache_mask_opsdram(&mut self) -> PRO_CACHE_MASK_OPSDRAM_W<'_>

Bit 5

pub fn pro_cache_mask_drom0(&mut self) -> PRO_CACHE_MASK_DROM0_W<'_>

Bit 4

pub fn pro_cache_mask_dram1(&mut self) -> PRO_CACHE_MASK_DRAM1_W<'_>

Bit 3

pub fn pro_cache_mask_irom0(&mut self) -> PRO_CACHE_MASK_IROM0_W<'_>

Bit 2

pub fn pro_cache_mask_iram1(&mut self) -> PRO_CACHE_MASK_IRAM1_W<'_>

Bit 1

pub fn pro_cache_mask_iram0(&mut self) -> PRO_CACHE_MASK_IRAM0_W<'_>

Bit 0

impl W<u32, Reg<u32, _PRO_CACHE_LOCK_0_ADDR>>

pub fn pro_cache_lock_0_addr_max(&mut self) -> PRO_CACHE_LOCK_0_ADDR_MAX_W<'_>

Bits 18:21

pub fn pro_cache_lock_0_addr_min(&mut self) -> PRO_CACHE_LOCK_0_ADDR_MIN_W<'_>

Bits 14:17

pub fn pro_cache_lock_0_addr_pre(&mut self) -> PRO_CACHE_LOCK_0_ADDR_PRE_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _PRO_CACHE_LOCK_1_ADDR>>

pub fn pro_cache_lock_1_addr_max(&mut self) -> PRO_CACHE_LOCK_1_ADDR_MAX_W<'_>

Bits 18:21

pub fn pro_cache_lock_1_addr_min(&mut self) -> PRO_CACHE_LOCK_1_ADDR_MIN_W<'_>

Bits 14:17

pub fn pro_cache_lock_1_addr_pre(&mut self) -> PRO_CACHE_LOCK_1_ADDR_PRE_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _PRO_CACHE_LOCK_2_ADDR>>

pub fn pro_cache_lock_2_addr_max(&mut self) -> PRO_CACHE_LOCK_2_ADDR_MAX_W<'_>

Bits 18:21

pub fn pro_cache_lock_2_addr_min(&mut self) -> PRO_CACHE_LOCK_2_ADDR_MIN_W<'_>

Bits 14:17

pub fn pro_cache_lock_2_addr_pre(&mut self) -> PRO_CACHE_LOCK_2_ADDR_PRE_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _PRO_CACHE_LOCK_3_ADDR>>

pub fn pro_cache_lock_3_addr_max(&mut self) -> PRO_CACHE_LOCK_3_ADDR_MAX_W<'_>

Bits 18:21

pub fn pro_cache_lock_3_addr_min(&mut self) -> PRO_CACHE_LOCK_3_ADDR_MIN_W<'_>

Bits 14:17

pub fn pro_cache_lock_3_addr_pre(&mut self) -> PRO_CACHE_LOCK_3_ADDR_PRE_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _APP_CACHE_CTRL>>

pub fn app_dram_hl(&mut self) -> APP_DRAM_HL_W<'_>

Bit 14

pub fn app_slave_req(&mut self) -> APP_SLAVE_REQ_W<'_>

Bit 13

pub fn app_ahb_spi_req(&mut self) -> APP_AHB_SPI_REQ_W<'_>

Bit 12

pub fn app_dram_split(&mut self) -> APP_DRAM_SPLIT_W<'_>

Bit 11

pub fn app_single_iram_ena(&mut self) -> APP_SINGLE_IRAM_ENA_W<'_>

Bit 10

pub fn app_cache_lock_3_en(&mut self) -> APP_CACHE_LOCK_3_EN_W<'_>

Bit 9

pub fn app_cache_lock_2_en(&mut self) -> APP_CACHE_LOCK_2_EN_W<'_>

Bit 8

pub fn app_cache_lock_1_en(&mut self) -> APP_CACHE_LOCK_1_EN_W<'_>

Bit 7

pub fn app_cache_lock_0_en(&mut self) -> APP_CACHE_LOCK_0_EN_W<'_>

Bit 6

pub fn app_cache_flush_done(&mut self) -> APP_CACHE_FLUSH_DONE_W<'_>

Bit 5

pub fn app_cache_flush_ena(&mut self) -> APP_CACHE_FLUSH_ENA_W<'_>

Bit 4

pub fn app_cache_enable(&mut self) -> APP_CACHE_ENABLE_W<'_>

Bit 3

pub fn app_cache_mode(&mut self) -> APP_CACHE_MODE_W<'_>

Bit 2

impl W<u32, Reg<u32, _APP_CACHE_CTRL1>>

pub fn app_cache_mmu_ia_clr(&mut self) -> APP_CACHE_MMU_IA_CLR_W<'_>

Bit 13

pub fn app_cmmu_pd(&mut self) -> APP_CMMU_PD_W<'_>

Bit 12

pub fn app_cmmu_force_on(&mut self) -> APP_CMMU_FORCE_ON_W<'_>

Bit 11

pub fn app_cmmu_flash_page_mode(&mut self) -> APP_CMMU_FLASH_PAGE_MODE_W<'_>

Bits 9:10

pub fn app_cmmu_sram_page_mode(&mut self) -> APP_CMMU_SRAM_PAGE_MODE_W<'_>

Bits 6:8

pub fn app_cache_mask_opsdram(&mut self) -> APP_CACHE_MASK_OPSDRAM_W<'_>

Bit 5

pub fn app_cache_mask_drom0(&mut self) -> APP_CACHE_MASK_DROM0_W<'_>

Bit 4

pub fn app_cache_mask_dram1(&mut self) -> APP_CACHE_MASK_DRAM1_W<'_>

Bit 3

pub fn app_cache_mask_irom0(&mut self) -> APP_CACHE_MASK_IROM0_W<'_>

Bit 2

pub fn app_cache_mask_iram1(&mut self) -> APP_CACHE_MASK_IRAM1_W<'_>

Bit 1

pub fn app_cache_mask_iram0(&mut self) -> APP_CACHE_MASK_IRAM0_W<'_>

Bit 0

impl W<u32, Reg<u32, _APP_CACHE_LOCK_0_ADDR>>

pub fn app_cache_lock_0_addr_max(&mut self) -> APP_CACHE_LOCK_0_ADDR_MAX_W<'_>

Bits 18:21

pub fn app_cache_lock_0_addr_min(&mut self) -> APP_CACHE_LOCK_0_ADDR_MIN_W<'_>

Bits 14:17

pub fn app_cache_lock_0_addr_pre(&mut self) -> APP_CACHE_LOCK_0_ADDR_PRE_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _APP_CACHE_LOCK_1_ADDR>>

pub fn app_cache_lock_1_addr_max(&mut self) -> APP_CACHE_LOCK_1_ADDR_MAX_W<'_>

Bits 18:21

pub fn app_cache_lock_1_addr_min(&mut self) -> APP_CACHE_LOCK_1_ADDR_MIN_W<'_>

Bits 14:17

pub fn app_cache_lock_1_addr_pre(&mut self) -> APP_CACHE_LOCK_1_ADDR_PRE_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _APP_CACHE_LOCK_2_ADDR>>

pub fn app_cache_lock_2_addr_max(&mut self) -> APP_CACHE_LOCK_2_ADDR_MAX_W<'_>

Bits 18:21

pub fn app_cache_lock_2_addr_min(&mut self) -> APP_CACHE_LOCK_2_ADDR_MIN_W<'_>

Bits 14:17

pub fn app_cache_lock_2_addr_pre(&mut self) -> APP_CACHE_LOCK_2_ADDR_PRE_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _APP_CACHE_LOCK_3_ADDR>>

pub fn app_cache_lock_3_addr_max(&mut self) -> APP_CACHE_LOCK_3_ADDR_MAX_W<'_>

Bits 18:21

pub fn app_cache_lock_3_addr_min(&mut self) -> APP_CACHE_LOCK_3_ADDR_MIN_W<'_>

Bits 14:17

pub fn app_cache_lock_3_addr_pre(&mut self) -> APP_CACHE_LOCK_3_ADDR_PRE_W<'_>

Bits 0:13

impl W<u32, Reg<u32, _TRACEMEM_MUX_MODE>>

pub fn tracemem_mux_mode(&mut self) -> TRACEMEM_MUX_MODE_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _PRO_TRACEMEM_ENA>>

pub fn pro_tracemem_ena(&mut self) -> PRO_TRACEMEM_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _APP_TRACEMEM_ENA>>

pub fn app_tracemem_ena(&mut self) -> APP_TRACEMEM_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _CACHE_MUX_MODE>>

pub fn cache_mux_mode(&mut self) -> CACHE_MUX_MODE_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _IMMU_PAGE_MODE>>

pub fn immu_page_mode(&mut self) -> IMMU_PAGE_MODE_W<'_>

Bits 1:2

pub fn internal_sram_immu_ena(&mut self) -> INTERNAL_SRAM_IMMU_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _DMMU_PAGE_MODE>>

pub fn dmmu_page_mode(&mut self) -> DMMU_PAGE_MODE_W<'_>

Bits 1:2

pub fn internal_sram_dmmu_ena(&mut self) -> INTERNAL_SRAM_DMMU_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _ROM_MPU_ENA>>

pub fn app_rom_mpu_ena(&mut self) -> APP_ROM_MPU_ENA_W<'_>

Bit 2

pub fn pro_rom_mpu_ena(&mut self) -> PRO_ROM_MPU_ENA_W<'_>

Bit 1

pub fn share_rom_mpu_ena(&mut self) -> SHARE_ROM_MPU_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _MEM_PD_MASK>>

pub fn lslp_mem_pd_mask(&mut self) -> LSLP_MEM_PD_MASK_W<'_>

Bit 0

impl W<u32, Reg<u32, _ROM_PD_CTRL>>

pub fn share_rom_pd(&mut self) -> SHARE_ROM_PD_W<'_>

Bits 2:7

pub fn app_rom_pd(&mut self) -> APP_ROM_PD_W<'_>

Bit 1

pub fn pro_rom_pd(&mut self) -> PRO_ROM_PD_W<'_>

Bit 0

impl W<u32, Reg<u32, _ROM_FO_CTRL>>

pub fn share_rom_fo(&mut self) -> SHARE_ROM_FO_W<'_>

Bits 2:7

pub fn app_rom_fo(&mut self) -> APP_ROM_FO_W<'_>

Bit 1

pub fn pro_rom_fo(&mut self) -> PRO_ROM_FO_W<'_>

Bit 0

impl W<u32, Reg<u32, _SRAM_PD_CTRL_0>>

pub fn sram_pd_0(&mut self) -> SRAM_PD_0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SRAM_PD_CTRL_1>>

pub fn sram_pd_1(&mut self) -> SRAM_PD_1_W<'_>

Bit 0

impl W<u32, Reg<u32, _SRAM_FO_CTRL_0>>

pub fn sram_fo_0(&mut self) -> SRAM_FO_0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SRAM_FO_CTRL_1>>

pub fn sram_fo_1(&mut self) -> SRAM_FO_1_W<'_>

Bit 0

impl W<u32, Reg<u32, _IRAM_DRAM_AHB_SEL>>

pub fn mac_dump_mode(&mut self) -> MAC_DUMP_MODE_W<'_>

Bits 5:6

pub fn mask_ahb(&mut self) -> MASK_AHB_W<'_>

Bit 4

pub fn mask_app_dram(&mut self) -> MASK_APP_DRAM_W<'_>

Bit 3

pub fn mask_pro_dram(&mut self) -> MASK_PRO_DRAM_W<'_>

Bit 2

pub fn mask_app_iram(&mut self) -> MASK_APP_IRAM_W<'_>

Bit 1

pub fn mask_pro_iram(&mut self) -> MASK_PRO_IRAM_W<'_>

Bit 0

impl W<u32, Reg<u32, _TAG_FO_CTRL>>

pub fn app_cache_tag_pd(&mut self) -> APP_CACHE_TAG_PD_W<'_>

Bit 9

pub fn app_cache_tag_force_on(&mut self) -> APP_CACHE_TAG_FORCE_ON_W<'_>

Bit 8

pub fn pro_cache_tag_pd(&mut self) -> PRO_CACHE_TAG_PD_W<'_>

Bit 1

pub fn pro_cache_tag_force_on(&mut self) -> PRO_CACHE_TAG_FORCE_ON_W<'_>

Bit 0

impl W<u32, Reg<u32, _AHB_LITE_MASK>>

pub fn ahb_lite_sdhost_pid_reg(&mut self) -> AHB_LITE_SDHOST_PID_REG_W<'_>

Bits 11:13

pub fn ahb_lite_mask_appdport(&mut self) -> AHB_LITE_MASK_APPDPORT_W<'_>

Bit 10

pub fn ahb_lite_mask_prodport(&mut self) -> AHB_LITE_MASK_PRODPORT_W<'_>

Bit 9

pub fn ahb_lite_mask_sdio(&mut self) -> AHB_LITE_MASK_SDIO_W<'_>

Bit 8

pub fn ahb_lite_mask_app(&mut self) -> AHB_LITE_MASK_APP_W<'_>

Bit 4

pub fn ahb_lite_mask_pro(&mut self) -> AHB_LITE_MASK_PRO_W<'_>

Bit 0

impl W<u32, Reg<u32, _AHB_MPU_TABLE_0>>

pub fn ahb_access_grant_0(&mut self) -> AHB_ACCESS_GRANT_0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _AHB_MPU_TABLE_1>>

pub fn ahb_access_grant_1(&mut self) -> AHB_ACCESS_GRANT_1_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _HOST_INF_SEL>>

pub fn link_device_sel(&mut self) -> LINK_DEVICE_SEL_W<'_>

Bits 8:15

pub fn peri_io_swap(&mut self) -> PERI_IO_SWAP_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _PERIP_CLK_EN>>

pub fn perip_clk_en(&mut self) -> PERIP_CLK_EN_W<'_>

Bits 0:31

pub fn pwm3(&mut self) -> PWM3_W<'_>

Bit 26

pub fn pwm2(&mut self) -> PWM2_W<'_>

Bit 25

pub fn uart_mem(&mut self) -> UART_MEM_W<'_>

Bit 24

pub fn uart2(&mut self) -> UART2_W<'_>

Bit 23

pub fn spi_dma(&mut self) -> SPI_DMA_W<'_>

Bit 22

pub fn i2s1(&mut self) -> I2S1_W<'_>

Bit 21

pub fn pwm1(&mut self) -> PWM1_W<'_>

Bit 20

pub fn can(&mut self) -> CAN_W<'_>

Bit 19

pub fn i2c1(&mut self) -> I2C1_W<'_>

Bit 18

pub fn pwm0(&mut self) -> PWM0_W<'_>

Bit 17

pub fn spi3(&mut self) -> SPI3_W<'_>

Bit 16

pub fn timer_group1(&mut self) -> TIMER_GROUP1_W<'_>

Bit 15

pub fn efuse(&mut self) -> EFUSE_W<'_>

Bit 14

pub fn timer_group0(&mut self) -> TIMER_GROUP0_W<'_>

Bit 13

pub fn uhci1(&mut self) -> UHCI1_W<'_>

Bit 12

pub fn led_pwm(&mut self) -> LED_PWM_W<'_>

Bit 11

pub fn pulse_cnt(&mut self) -> PULSE_CNT_W<'_>

Bit 10

pub fn remote_controller(&mut self) -> REMOTE_CONTROLLER_W<'_>

Bit 9

pub fn uhci0(&mut self) -> UHCI0_W<'_>

Bit 8

pub fn i2c0(&mut self) -> I2C0_W<'_>

Bit 7

pub fn spi2(&mut self) -> SPI2_W<'_>

Bit 6

pub fn uart1(&mut self) -> UART1_W<'_>

Bit 5

pub fn i2s0(&mut self) -> I2S0_W<'_>

Bit 4

pub fn wdg(&mut self) -> WDG_W<'_>

Bit 3

pub fn uart0(&mut self) -> UART0_W<'_>

Bit 2

pub fn spi0(&mut self) -> SPI0_W<'_>

Bit 1

pub fn timers(&mut self) -> TIMERS_W<'_>

Bit 0

impl W<u32, Reg<u32, _PERIP_RST_EN>>

pub fn perip_rst(&mut self) -> PERIP_RST_W<'_>

Bits 0:31

pub fn spi_decrypt_enable(&mut self) -> SPI_DECRYPT_ENABLE_W<'_>

Bit 12

pub fn spi_encrypt_enable(&mut self) -> SPI_ENCRYPT_ENABLE_W<'_>

Bit 8

pub fn slave_spi_mask_app(&mut self) -> SLAVE_SPI_MASK_APP_W<'_>

Bit 4

pub fn slave_spi_mask_pro(&mut self) -> SLAVE_SPI_MASK_PRO_W<'_>

Bit 0

pub fn pwm3(&mut self) -> PWM3_W<'_>

Bit 26

pub fn pwm2(&mut self) -> PWM2_W<'_>

Bit 25

pub fn uart_mem(&mut self) -> UART_MEM_W<'_>

Bit 24

pub fn uart2(&mut self) -> UART2_W<'_>

Bit 23

pub fn spi_dma(&mut self) -> SPI_DMA_W<'_>

Bit 22

pub fn i2s1(&mut self) -> I2S1_W<'_>

Bit 21

pub fn pwm1(&mut self) -> PWM1_W<'_>

Bit 20

pub fn can(&mut self) -> CAN_W<'_>

Bit 19

pub fn i2c1(&mut self) -> I2C1_W<'_>

Bit 18

pub fn pwm0(&mut self) -> PWM0_W<'_>

Bit 17

pub fn spi3(&mut self) -> SPI3_W<'_>

Bit 16

pub fn timer_group1(&mut self) -> TIMER_GROUP1_W<'_>

Bit 15

pub fn efuse(&mut self) -> EFUSE_W<'_>

Bit 14

pub fn timer_group0(&mut self) -> TIMER_GROUP0_W<'_>

Bit 13

pub fn uhci1(&mut self) -> UHCI1_W<'_>

Bit 12

pub fn led_pwm(&mut self) -> LED_PWM_W<'_>

Bit 11

pub fn pulse_cnt(&mut self) -> PULSE_CNT_W<'_>

Bit 10

pub fn remote_controller(&mut self) -> REMOTE_CONTROLLER_W<'_>

Bit 9

pub fn uhci0(&mut self) -> UHCI0_W<'_>

Bit 8

pub fn i2c0(&mut self) -> I2C0_W<'_>

Bit 7

pub fn spi2(&mut self) -> SPI2_W<'_>

Bit 6

pub fn uart1(&mut self) -> UART1_W<'_>

Bit 5

pub fn i2s0(&mut self) -> I2S0_W<'_>

Bit 4

pub fn wdg(&mut self) -> WDG_W<'_>

Bit 3

pub fn uart0(&mut self) -> UART0_W<'_>

Bit 2

pub fn spi0(&mut self) -> SPI0_W<'_>

Bit 1

pub fn timers(&mut self) -> TIMERS_W<'_>

Bit 0

impl W<u32, Reg<u32, _WIFI_CLK_EN>>

pub fn wifi_clk_en(&mut self) -> WIFI_CLK_EN_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CORE_RST_EN>>

pub fn core_rst(&mut self) -> CORE_RST_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _BT_LPCK_DIV_INT>>

pub fn btextwakeup_req(&mut self) -> BTEXTWAKEUP_REQ_W<'_>

Bit 12

pub fn bt_lpck_div_num(&mut self) -> BT_LPCK_DIV_NUM_W<'_>

Bits 0:11

impl W<u32, Reg<u32, _BT_LPCK_DIV_FRAC>>

pub fn lpclk_sel_xtal32k(&mut self) -> LPCLK_SEL_XTAL32K_W<'_>

Bit 27

pub fn lpclk_sel_xtal(&mut self) -> LPCLK_SEL_XTAL_W<'_>

Bit 26

pub fn lpclk_sel_8m(&mut self) -> LPCLK_SEL_8M_W<'_>

Bit 25

pub fn lpclk_sel_rtc_slow(&mut self) -> LPCLK_SEL_RTC_SLOW_W<'_>

Bit 24

pub fn bt_lpck_div_a(&mut self) -> BT_LPCK_DIV_A_W<'_>

Bits 12:23

pub fn bt_lpck_div_b(&mut self) -> BT_LPCK_DIV_B_W<'_>

Bits 0:11

impl W<u32, Reg<u32, _CPU_INTR_FROM_CPU_0>>

pub fn cpu_intr_from_cpu_0(&mut self) -> CPU_INTR_FROM_CPU_0_W<'_>

Bit 0

impl W<u32, Reg<u32, _CPU_INTR_FROM_CPU_1>>

pub fn cpu_intr_from_cpu_1(&mut self) -> CPU_INTR_FROM_CPU_1_W<'_>

Bit 0

impl W<u32, Reg<u32, _CPU_INTR_FROM_CPU_2>>

pub fn cpu_intr_from_cpu_2(&mut self) -> CPU_INTR_FROM_CPU_2_W<'_>

Bit 0

impl W<u32, Reg<u32, _CPU_INTR_FROM_CPU_3>>

pub fn cpu_intr_from_cpu_3(&mut self) -> CPU_INTR_FROM_CPU_3_W<'_>

Bit 0

impl W<u32, Reg<u32, _PRO_INTR_STATUS_0>>

pub fn pro_intr_status_0(&mut self) -> PRO_INTR_STATUS_0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _PRO_INTR_STATUS_1>>

pub fn pro_intr_status_1(&mut self) -> PRO_INTR_STATUS_1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _PRO_INTR_STATUS_2>>

pub fn pro_intr_status_2(&mut self) -> PRO_INTR_STATUS_2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APP_INTR_STATUS_0>>

pub fn app_intr_status_0(&mut self) -> APP_INTR_STATUS_0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APP_INTR_STATUS_1>>

pub fn app_intr_status_1(&mut self) -> APP_INTR_STATUS_1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APP_INTR_STATUS_2>>

pub fn app_intr_status_2(&mut self) -> APP_INTR_STATUS_2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _PRO_MAC_INTR_MAP>>

pub fn pro_mac_intr_map(&mut self) -> PRO_MAC_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_MAC_NMI_MAP>>

pub fn pro_mac_nmi_map(&mut self) -> PRO_MAC_NMI_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_BB_INT_MAP>>

pub fn pro_bb_int_map(&mut self) -> PRO_BB_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_BT_MAC_INT_MAP>>

pub fn pro_bt_mac_int_map(&mut self) -> PRO_BT_MAC_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_BT_BB_INT_MAP>>

pub fn pro_bt_bb_int_map(&mut self) -> PRO_BT_BB_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_BT_BB_NMI_MAP>>

pub fn pro_bt_bb_nmi_map(&mut self) -> PRO_BT_BB_NMI_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_RWBT_IRQ_MAP>>

pub fn pro_rwbt_irq_map(&mut self) -> PRO_RWBT_IRQ_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_RWBLE_IRQ_MAP>>

pub fn pro_rwble_irq_map(&mut self) -> PRO_RWBLE_IRQ_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_RWBT_NMI_MAP>>

pub fn pro_rwbt_nmi_map(&mut self) -> PRO_RWBT_NMI_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_RWBLE_NMI_MAP>>

pub fn pro_rwble_nmi_map(&mut self) -> PRO_RWBLE_NMI_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_SLC0_INTR_MAP>>

pub fn pro_slc0_intr_map(&mut self) -> PRO_SLC0_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_SLC1_INTR_MAP>>

pub fn pro_slc1_intr_map(&mut self) -> PRO_SLC1_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_UHCI0_INTR_MAP>>

pub fn pro_uhci0_intr_map(&mut self) -> PRO_UHCI0_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_UHCI1_INTR_MAP>>

pub fn pro_uhci1_intr_map(&mut self) -> PRO_UHCI1_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG_T0_LEVEL_INT_MAP>>

pub fn pro_tg_t0_level_int_map(&mut self) -> PRO_TG_T0_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG_T1_LEVEL_INT_MAP>>

pub fn pro_tg_t1_level_int_map(&mut self) -> PRO_TG_T1_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG_WDT_LEVEL_INT_MAP>>

pub fn pro_tg_wdt_level_int_map(&mut self) -> PRO_TG_WDT_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG_LACT_LEVEL_INT_MAP>>

pub fn pro_tg_lact_level_int_map(&mut self) -> PRO_TG_LACT_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG1_T0_LEVEL_INT_MAP>>

pub fn pro_tg1_t0_level_int_map(&mut self) -> PRO_TG1_T0_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG1_T1_LEVEL_INT_MAP>>

pub fn pro_tg1_t1_level_int_map(&mut self) -> PRO_TG1_T1_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG1_WDT_LEVEL_INT_MAP>>

pub fn pro_tg1_wdt_level_int_map(&mut self) -> PRO_TG1_WDT_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG1_LACT_LEVEL_INT_MAP>>

pub fn pro_tg1_lact_level_int_map(&mut self) -> PRO_TG1_LACT_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_GPIO_INTERRUPT_MAP>>

pub fn pro_gpio_interrupt_pro_map(&mut self) -> PRO_GPIO_INTERRUPT_PRO_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_GPIO_INTERRUPT_NMI_MAP>>

pub fn pro_gpio_interrupt_pro_nmi_map(
    &mut self
) -> PRO_GPIO_INTERRUPT_PRO_NMI_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_CPU_INTR_FROM_CPU_0_MAP>>

pub fn pro_cpu_intr_from_cpu_0_map(
    &mut self
) -> PRO_CPU_INTR_FROM_CPU_0_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_CPU_INTR_FROM_CPU_1_MAP>>

pub fn pro_cpu_intr_from_cpu_1_map(
    &mut self
) -> PRO_CPU_INTR_FROM_CPU_1_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_CPU_INTR_FROM_CPU_2_MAP>>

pub fn pro_cpu_intr_from_cpu_2_map(
    &mut self
) -> PRO_CPU_INTR_FROM_CPU_2_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_CPU_INTR_FROM_CPU_3_MAP>>

pub fn pro_cpu_intr_from_cpu_3_map(
    &mut self
) -> PRO_CPU_INTR_FROM_CPU_3_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_SPI_INTR_0_MAP>>

pub fn pro_spi_intr_0_map(&mut self) -> PRO_SPI_INTR_0_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_SPI_INTR_1_MAP>>

pub fn pro_spi_intr_1_map(&mut self) -> PRO_SPI_INTR_1_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_SPI_INTR_2_MAP>>

pub fn pro_spi_intr_2_map(&mut self) -> PRO_SPI_INTR_2_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_SPI_INTR_3_MAP>>

pub fn pro_spi_intr_3_map(&mut self) -> PRO_SPI_INTR_3_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_I2S0_INT_MAP>>

pub fn pro_i2s0_int_map(&mut self) -> PRO_I2S0_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_I2S1_INT_MAP>>

pub fn pro_i2s1_int_map(&mut self) -> PRO_I2S1_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_UART_INTR_MAP>>

pub fn pro_uart_intr_map(&mut self) -> PRO_UART_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_UART1_INTR_MAP>>

pub fn pro_uart1_intr_map(&mut self) -> PRO_UART1_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_UART2_INTR_MAP>>

pub fn pro_uart2_intr_map(&mut self) -> PRO_UART2_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_SDIO_HOST_INTERRUPT_MAP>>

pub fn pro_sdio_host_interrupt_map(
    &mut self
) -> PRO_SDIO_HOST_INTERRUPT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_EMAC_INT_MAP>>

pub fn pro_emac_int_map(&mut self) -> PRO_EMAC_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_PWM0_INTR_MAP>>

pub fn pro_pwm0_intr_map(&mut self) -> PRO_PWM0_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_PWM1_INTR_MAP>>

pub fn pro_pwm1_intr_map(&mut self) -> PRO_PWM1_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_PWM2_INTR_MAP>>

pub fn pro_pwm2_intr_map(&mut self) -> PRO_PWM2_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_PWM3_INTR_MAP>>

pub fn pro_pwm3_intr_map(&mut self) -> PRO_PWM3_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_LEDC_INT_MAP>>

pub fn pro_ledc_int_map(&mut self) -> PRO_LEDC_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_EFUSE_INT_MAP>>

pub fn pro_efuse_int_map(&mut self) -> PRO_EFUSE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_CAN_INT_MAP>>

pub fn pro_can_int_map(&mut self) -> PRO_CAN_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_RTC_CORE_INTR_MAP>>

pub fn pro_rtc_core_intr_map(&mut self) -> PRO_RTC_CORE_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_RMT_INTR_MAP>>

pub fn pro_rmt_intr_map(&mut self) -> PRO_RMT_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_PCNT_INTR_MAP>>

pub fn pro_pcnt_intr_map(&mut self) -> PRO_PCNT_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_I2C_EXT0_INTR_MAP>>

pub fn pro_i2c_ext0_intr_map(&mut self) -> PRO_I2C_EXT0_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_I2C_EXT1_INTR_MAP>>

pub fn pro_i2c_ext1_intr_map(&mut self) -> PRO_I2C_EXT1_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_RSA_INTR_MAP>>

pub fn pro_rsa_intr_map(&mut self) -> PRO_RSA_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_SPI1_DMA_INT_MAP>>

pub fn pro_spi1_dma_int_map(&mut self) -> PRO_SPI1_DMA_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_SPI2_DMA_INT_MAP>>

pub fn pro_spi2_dma_int_map(&mut self) -> PRO_SPI2_DMA_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_SPI3_DMA_INT_MAP>>

pub fn pro_spi3_dma_int_map(&mut self) -> PRO_SPI3_DMA_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_WDG_INT_MAP>>

pub fn pro_wdg_int_map(&mut self) -> PRO_WDG_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TIMER_INT1_MAP>>

pub fn pro_timer_int1_map(&mut self) -> PRO_TIMER_INT1_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TIMER_INT2_MAP>>

pub fn pro_timer_int2_map(&mut self) -> PRO_TIMER_INT2_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG_T0_EDGE_INT_MAP>>

pub fn pro_tg_t0_edge_int_map(&mut self) -> PRO_TG_T0_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG_T1_EDGE_INT_MAP>>

pub fn pro_tg_t1_edge_int_map(&mut self) -> PRO_TG_T1_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG_WDT_EDGE_INT_MAP>>

pub fn pro_tg_wdt_edge_int_map(&mut self) -> PRO_TG_WDT_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG_LACT_EDGE_INT_MAP>>

pub fn pro_tg_lact_edge_int_map(&mut self) -> PRO_TG_LACT_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG1_T0_EDGE_INT_MAP>>

pub fn pro_tg1_t0_edge_int_map(&mut self) -> PRO_TG1_T0_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG1_T1_EDGE_INT_MAP>>

pub fn pro_tg1_t1_edge_int_map(&mut self) -> PRO_TG1_T1_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG1_WDT_EDGE_INT_MAP>>

pub fn pro_tg1_wdt_edge_int_map(&mut self) -> PRO_TG1_WDT_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_TG1_LACT_EDGE_INT_MAP>>

pub fn pro_tg1_lact_edge_int_map(&mut self) -> PRO_TG1_LACT_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_MMU_IA_INT_MAP>>

pub fn pro_mmu_ia_int_map(&mut self) -> PRO_MMU_IA_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_MPU_IA_INT_MAP>>

pub fn pro_mpu_ia_int_map(&mut self) -> PRO_MPU_IA_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _PRO_CACHE_IA_INT_MAP>>

pub fn pro_cache_ia_int_map(&mut self) -> PRO_CACHE_IA_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_MAC_INTR_MAP>>

pub fn app_mac_intr_map(&mut self) -> APP_MAC_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_MAC_NMI_MAP>>

pub fn app_mac_nmi_map(&mut self) -> APP_MAC_NMI_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_BB_INT_MAP>>

pub fn app_bb_int_map(&mut self) -> APP_BB_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_BT_MAC_INT_MAP>>

pub fn app_bt_mac_int_map(&mut self) -> APP_BT_MAC_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_BT_BB_INT_MAP>>

pub fn app_bt_bb_int_map(&mut self) -> APP_BT_BB_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_BT_BB_NMI_MAP>>

pub fn app_bt_bb_nmi_map(&mut self) -> APP_BT_BB_NMI_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_RWBT_IRQ_MAP>>

pub fn app_rwbt_irq_map(&mut self) -> APP_RWBT_IRQ_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_RWBLE_IRQ_MAP>>

pub fn app_rwble_irq_map(&mut self) -> APP_RWBLE_IRQ_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_RWBT_NMI_MAP>>

pub fn app_rwbt_nmi_map(&mut self) -> APP_RWBT_NMI_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_RWBLE_NMI_MAP>>

pub fn app_rwble_nmi_map(&mut self) -> APP_RWBLE_NMI_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_SLC0_INTR_MAP>>

pub fn app_slc0_intr_map(&mut self) -> APP_SLC0_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_SLC1_INTR_MAP>>

pub fn app_slc1_intr_map(&mut self) -> APP_SLC1_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_UHCI0_INTR_MAP>>

pub fn app_uhci0_intr_map(&mut self) -> APP_UHCI0_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_UHCI1_INTR_MAP>>

pub fn app_uhci1_intr_map(&mut self) -> APP_UHCI1_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG_T0_LEVEL_INT_MAP>>

pub fn app_tg_t0_level_int_map(&mut self) -> APP_TG_T0_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG_T1_LEVEL_INT_MAP>>

pub fn app_tg_t1_level_int_map(&mut self) -> APP_TG_T1_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG_WDT_LEVEL_INT_MAP>>

pub fn app_tg_wdt_level_int_map(&mut self) -> APP_TG_WDT_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG_LACT_LEVEL_INT_MAP>>

pub fn app_tg_lact_level_int_map(&mut self) -> APP_TG_LACT_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG1_T0_LEVEL_INT_MAP>>

pub fn app_tg1_t0_level_int_map(&mut self) -> APP_TG1_T0_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG1_T1_LEVEL_INT_MAP>>

pub fn app_tg1_t1_level_int_map(&mut self) -> APP_TG1_T1_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG1_WDT_LEVEL_INT_MAP>>

pub fn app_tg1_wdt_level_int_map(&mut self) -> APP_TG1_WDT_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG1_LACT_LEVEL_INT_MAP>>

pub fn app_tg1_lact_level_int_map(&mut self) -> APP_TG1_LACT_LEVEL_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_GPIO_INTERRUPT_MAP>>

pub fn app_gpio_interrupt_app_map(&mut self) -> APP_GPIO_INTERRUPT_APP_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_GPIO_INTERRUPT_NMI_MAP>>

pub fn app_gpio_interrupt_app_nmi_map(
    &mut self
) -> APP_GPIO_INTERRUPT_APP_NMI_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_CPU_INTR_FROM_CPU_0_MAP>>

pub fn app_cpu_intr_from_cpu_0_map(
    &mut self
) -> APP_CPU_INTR_FROM_CPU_0_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_CPU_INTR_FROM_CPU_1_MAP>>

pub fn app_cpu_intr_from_cpu_1_map(
    &mut self
) -> APP_CPU_INTR_FROM_CPU_1_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_CPU_INTR_FROM_CPU_2_MAP>>

pub fn app_cpu_intr_from_cpu_2_map(
    &mut self
) -> APP_CPU_INTR_FROM_CPU_2_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_CPU_INTR_FROM_CPU_3_MAP>>

pub fn app_cpu_intr_from_cpu_3_map(
    &mut self
) -> APP_CPU_INTR_FROM_CPU_3_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_SPI_INTR_0_MAP>>

pub fn app_spi_intr_0_map(&mut self) -> APP_SPI_INTR_0_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_SPI_INTR_1_MAP>>

pub fn app_spi_intr_1_map(&mut self) -> APP_SPI_INTR_1_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_SPI_INTR_2_MAP>>

pub fn app_spi_intr_2_map(&mut self) -> APP_SPI_INTR_2_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_SPI_INTR_3_MAP>>

pub fn app_spi_intr_3_map(&mut self) -> APP_SPI_INTR_3_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_I2S0_INT_MAP>>

pub fn app_i2s0_int_map(&mut self) -> APP_I2S0_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_I2S1_INT_MAP>>

pub fn app_i2s1_int_map(&mut self) -> APP_I2S1_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_UART_INTR_MAP>>

pub fn app_uart_intr_map(&mut self) -> APP_UART_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_UART1_INTR_MAP>>

pub fn app_uart1_intr_map(&mut self) -> APP_UART1_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_UART2_INTR_MAP>>

pub fn app_uart2_intr_map(&mut self) -> APP_UART2_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_SDIO_HOST_INTERRUPT_MAP>>

pub fn app_sdio_host_interrupt_map(
    &mut self
) -> APP_SDIO_HOST_INTERRUPT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_EMAC_INT_MAP>>

pub fn app_emac_int_map(&mut self) -> APP_EMAC_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_PWM0_INTR_MAP>>

pub fn app_pwm0_intr_map(&mut self) -> APP_PWM0_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_PWM1_INTR_MAP>>

pub fn app_pwm1_intr_map(&mut self) -> APP_PWM1_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_PWM2_INTR_MAP>>

pub fn app_pwm2_intr_map(&mut self) -> APP_PWM2_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_PWM3_INTR_MAP>>

pub fn app_pwm3_intr_map(&mut self) -> APP_PWM3_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_LEDC_INT_MAP>>

pub fn app_ledc_int_map(&mut self) -> APP_LEDC_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_EFUSE_INT_MAP>>

pub fn app_efuse_int_map(&mut self) -> APP_EFUSE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_CAN_INT_MAP>>

pub fn app_can_int_map(&mut self) -> APP_CAN_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_RTC_CORE_INTR_MAP>>

pub fn app_rtc_core_intr_map(&mut self) -> APP_RTC_CORE_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_RMT_INTR_MAP>>

pub fn app_rmt_intr_map(&mut self) -> APP_RMT_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_PCNT_INTR_MAP>>

pub fn app_pcnt_intr_map(&mut self) -> APP_PCNT_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_I2C_EXT0_INTR_MAP>>

pub fn app_i2c_ext0_intr_map(&mut self) -> APP_I2C_EXT0_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_I2C_EXT1_INTR_MAP>>

pub fn app_i2c_ext1_intr_map(&mut self) -> APP_I2C_EXT1_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_RSA_INTR_MAP>>

pub fn app_rsa_intr_map(&mut self) -> APP_RSA_INTR_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_SPI1_DMA_INT_MAP>>

pub fn app_spi1_dma_int_map(&mut self) -> APP_SPI1_DMA_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_SPI2_DMA_INT_MAP>>

pub fn app_spi2_dma_int_map(&mut self) -> APP_SPI2_DMA_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_SPI3_DMA_INT_MAP>>

pub fn app_spi3_dma_int_map(&mut self) -> APP_SPI3_DMA_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_WDG_INT_MAP>>

pub fn app_wdg_int_map(&mut self) -> APP_WDG_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TIMER_INT1_MAP>>

pub fn app_timer_int1_map(&mut self) -> APP_TIMER_INT1_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TIMER_INT2_MAP>>

pub fn app_timer_int2_map(&mut self) -> APP_TIMER_INT2_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG_T0_EDGE_INT_MAP>>

pub fn app_tg_t0_edge_int_map(&mut self) -> APP_TG_T0_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG_T1_EDGE_INT_MAP>>

pub fn app_tg_t1_edge_int_map(&mut self) -> APP_TG_T1_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG_WDT_EDGE_INT_MAP>>

pub fn app_tg_wdt_edge_int_map(&mut self) -> APP_TG_WDT_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG_LACT_EDGE_INT_MAP>>

pub fn app_tg_lact_edge_int_map(&mut self) -> APP_TG_LACT_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG1_T0_EDGE_INT_MAP>>

pub fn app_tg1_t0_edge_int_map(&mut self) -> APP_TG1_T0_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG1_T1_EDGE_INT_MAP>>

pub fn app_tg1_t1_edge_int_map(&mut self) -> APP_TG1_T1_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG1_WDT_EDGE_INT_MAP>>

pub fn app_tg1_wdt_edge_int_map(&mut self) -> APP_TG1_WDT_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_TG1_LACT_EDGE_INT_MAP>>

pub fn app_tg1_lact_edge_int_map(&mut self) -> APP_TG1_LACT_EDGE_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_MMU_IA_INT_MAP>>

pub fn app_mmu_ia_int_map(&mut self) -> APP_MMU_IA_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_MPU_IA_INT_MAP>>

pub fn app_mpu_ia_int_map(&mut self) -> APP_MPU_IA_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _APP_CACHE_IA_INT_MAP>>

pub fn app_cache_ia_int_map(&mut self) -> APP_CACHE_IA_INT_MAP_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_UART>>

pub fn uart_access_grant_config(&mut self) -> UART_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_SPI1>>

pub fn spi1_access_grant_config(&mut self) -> SPI1_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_SPI0>>

pub fn spi0_access_grant_config(&mut self) -> SPI0_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_GPIO>>

pub fn gpio_access_grant_config(&mut self) -> GPIO_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_FE2>>

pub fn fe2_access_grant_config(&mut self) -> FE2_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_FE>>

pub fn fe_access_grant_config(&mut self) -> FE_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_TIMER>>

pub fn timer_access_grant_config(&mut self) -> TIMER_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_RTC>>

pub fn rtc_access_grant_config(&mut self) -> RTC_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_IO_MUX>>

pub fn iomux_access_grant_config(&mut self) -> IOMUX_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_WDG>>

pub fn wdg_access_grant_config(&mut self) -> WDG_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_HINF>>

pub fn hinf_access_grant_config(&mut self) -> HINF_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_UHCI1>>

pub fn uhci1_access_grant_config(&mut self) -> UHCI1_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_MISC>>

pub fn misc_access_grant_config(&mut self) -> MISC_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_I2C>>

pub fn i2c_access_grant_config(&mut self) -> I2C_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_I2S0>>

pub fn i2s0_access_grant_config(&mut self) -> I2S0_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_UART1>>

pub fn uart1_access_grant_config(&mut self) -> UART1_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_BT>>

pub fn bt_access_grant_config(&mut self) -> BT_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_BT_BUFFER>>

pub fn btbuffer_access_grant_config(
    &mut self
) -> BTBUFFER_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_I2C_EXT0>>

pub fn i2cext0_access_grant_config(
    &mut self
) -> I2CEXT0_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_UHCI0>>

pub fn uhci0_access_grant_config(&mut self) -> UHCI0_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_SLCHOST>>

pub fn slchost_access_grant_config(
    &mut self
) -> SLCHOST_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_RMT>>

pub fn rmt_access_grant_config(&mut self) -> RMT_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_PCNT>>

pub fn pcnt_access_grant_config(&mut self) -> PCNT_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_SLC>>

pub fn slc_access_grant_config(&mut self) -> SLC_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_LEDC>>

pub fn ledc_access_grant_config(&mut self) -> LEDC_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_EFUSE>>

pub fn efuse_access_grant_config(&mut self) -> EFUSE_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_SPI_ENCRYPT>>

pub fn spi_encrypy_access_grant_config(
    &mut self
) -> SPI_ENCRYPY_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_BB>>

pub fn bb_access_grant_config(&mut self) -> BB_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_PWM0>>

pub fn pwm0_access_grant_config(&mut self) -> PWM0_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_TIMERGROUP>>

pub fn timergroup_access_grant_config(
    &mut self
) -> TIMERGROUP_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_TIMERGROUP1>>

pub fn timergroup1_access_grant_config(
    &mut self
) -> TIMERGROUP1_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_SPI2>>

pub fn spi2_access_grant_config(&mut self) -> SPI2_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_SPI3>>

pub fn spi3_access_grant_config(&mut self) -> SPI3_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_APB_CTRL>>

pub fn apbctrl_access_grant_config(
    &mut self
) -> APBCTRL_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_I2C_EXT1>>

pub fn i2cext1_access_grant_config(
    &mut self
) -> I2CEXT1_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_SDIO_HOST>>

pub fn sdiohost_access_grant_config(
    &mut self
) -> SDIOHOST_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_EMAC>>

pub fn emac_access_grant_config(&mut self) -> EMAC_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_CAN>>

pub fn can_access_grant_config(&mut self) -> CAN_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_PWM1>>

pub fn pwm1_access_grant_config(&mut self) -> PWM1_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_I2S1>>

pub fn i2s1_access_grant_config(&mut self) -> I2S1_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_UART2>>

pub fn uart2_access_grant_config(&mut self) -> UART2_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_PWM2>>

pub fn pwm2_access_grant_config(&mut self) -> PWM2_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_PWM3>>

pub fn pwm3_access_grant_config(&mut self) -> PWM3_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_RWBT>>

pub fn rwbt_access_grant_config(&mut self) -> RWBT_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_BTMAC>>

pub fn btmac_access_grant_config(&mut self) -> BTMAC_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_WIFIMAC>>

pub fn wifimac_access_grant_config(
    &mut self
) -> WIFIMAC_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _AHBLITE_MPU_TABLE_PWR>>

pub fn pwr_access_grant_config(&mut self) -> PWR_ACCESS_GRANT_CONFIG_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _MEM_ACCESS_DBUG0>>

pub fn internal_sram_mmu_multi_hit(
    &mut self
) -> INTERNAL_SRAM_MMU_MULTI_HIT_W<'_>

Bits 26:29

pub fn internal_sram_ia(&mut self) -> INTERNAL_SRAM_IA_W<'_>

Bits 14:25

pub fn internal_sram_mmu_ad(&mut self) -> INTERNAL_SRAM_MMU_AD_W<'_>

Bits 10:13

pub fn share_rom_ia(&mut self) -> SHARE_ROM_IA_W<'_>

Bits 6:9

pub fn share_rom_mpu_ad(&mut self) -> SHARE_ROM_MPU_AD_W<'_>

Bits 4:5

pub fn app_rom_ia(&mut self) -> APP_ROM_IA_W<'_>

Bit 3

pub fn app_rom_mpu_ad(&mut self) -> APP_ROM_MPU_AD_W<'_>

Bit 2

pub fn pro_rom_ia(&mut self) -> PRO_ROM_IA_W<'_>

Bit 1

pub fn pro_rom_mpu_ad(&mut self) -> PRO_ROM_MPU_AD_W<'_>

Bit 0

impl W<u32, Reg<u32, _MEM_ACCESS_DBUG1>>

pub fn ahblite_ia(&mut self) -> AHBLITE_IA_W<'_>

Bit 10

pub fn ahblite_access_deny(&mut self) -> AHBLITE_ACCESS_DENY_W<'_>

Bit 9

pub fn ahb_access_deny(&mut self) -> AHB_ACCESS_DENY_W<'_>

Bit 8

pub fn pidgen_ia(&mut self) -> PIDGEN_IA_W<'_>

Bits 6:7

pub fn arb_ia(&mut self) -> ARB_IA_W<'_>

Bits 4:5

pub fn internal_sram_mmu_miss(&mut self) -> INTERNAL_SRAM_MMU_MISS_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _PRO_DCACHE_DBUG0>>

pub fn pro_rx_end(&mut self) -> PRO_RX_END_W<'_>

Bit 23

pub fn pro_slave_wdata_v(&mut self) -> PRO_SLAVE_WDATA_V_W<'_>

Bit 22

pub fn pro_slave_wr(&mut self) -> PRO_SLAVE_WR_W<'_>

Bit 21

pub fn pro_tx_end(&mut self) -> PRO_TX_END_W<'_>

Bit 20

pub fn pro_wr_bak_to_read(&mut self) -> PRO_WR_BAK_TO_READ_W<'_>

Bit 19

pub fn pro_cache_state(&mut self) -> PRO_CACHE_STATE_W<'_>

Bits 7:18

pub fn pro_cache_ia(&mut self) -> PRO_CACHE_IA_W<'_>

Bits 1:6

pub fn pro_cache_mmu_ia(&mut self) -> PRO_CACHE_MMU_IA_W<'_>

Bit 0

impl W<u32, Reg<u32, _PRO_DCACHE_DBUG1>>

pub fn pro_ctag_ram_rdata(&mut self) -> PRO_CTAG_RAM_RDATA_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _PRO_DCACHE_DBUG2>>

pub fn pro_cache_vaddr(&mut self) -> PRO_CACHE_VADDR_W<'_>

Bits 0:26

impl W<u32, Reg<u32, _PRO_DCACHE_DBUG3>>

pub fn pro_cache_iram0_pid_error(&mut self) -> PRO_CACHE_IRAM0_PID_ERROR_W<'_>

Bit 15

pub fn pro_cpu_disabled_cache_ia(&mut self) -> PRO_CPU_DISABLED_CACHE_IA_W<'_>

Bits 9:14

impl W<u32, Reg<u32, _PRO_DCACHE_DBUG4>>

pub fn pro_dram1addr0_ia(&mut self) -> PRO_DRAM1ADDR0_IA_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _PRO_DCACHE_DBUG5>>

pub fn pro_drom0addr0_ia(&mut self) -> PRO_DROM0ADDR0_IA_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _PRO_DCACHE_DBUG6>>

pub fn pro_iram0addr_ia(&mut self) -> PRO_IRAM0ADDR_IA_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _PRO_DCACHE_DBUG7>>

pub fn pro_iram1addr_ia(&mut self) -> PRO_IRAM1ADDR_IA_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _PRO_DCACHE_DBUG8>>

pub fn pro_irom0addr_ia(&mut self) -> PRO_IROM0ADDR_IA_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _PRO_DCACHE_DBUG9>>

pub fn pro_opsdramaddr_ia(&mut self) -> PRO_OPSDRAMADDR_IA_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _APP_DCACHE_DBUG0>>

pub fn app_rx_end(&mut self) -> APP_RX_END_W<'_>

Bit 23

pub fn app_slave_wdata_v(&mut self) -> APP_SLAVE_WDATA_V_W<'_>

Bit 22

pub fn app_slave_wr(&mut self) -> APP_SLAVE_WR_W<'_>

Bit 21

pub fn app_tx_end(&mut self) -> APP_TX_END_W<'_>

Bit 20

pub fn app_wr_bak_to_read(&mut self) -> APP_WR_BAK_TO_READ_W<'_>

Bit 19

pub fn app_cache_state(&mut self) -> APP_CACHE_STATE_W<'_>

Bits 7:18

pub fn app_cache_ia(&mut self) -> APP_CACHE_IA_W<'_>

Bits 1:6

pub fn app_cache_mmu_ia(&mut self) -> APP_CACHE_MMU_IA_W<'_>

Bit 0

impl W<u32, Reg<u32, _APP_DCACHE_DBUG1>>

pub fn app_ctag_ram_rdata(&mut self) -> APP_CTAG_RAM_RDATA_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APP_DCACHE_DBUG2>>

pub fn app_cache_vaddr(&mut self) -> APP_CACHE_VADDR_W<'_>

Bits 0:26

impl W<u32, Reg<u32, _APP_DCACHE_DBUG3>>

pub fn app_cache_iram0_pid_error(&mut self) -> APP_CACHE_IRAM0_PID_ERROR_W<'_>

Bit 15

pub fn app_cpu_disabled_cache_ia(&mut self) -> APP_CPU_DISABLED_CACHE_IA_W<'_>

Bits 9:14

impl W<u32, Reg<u32, _APP_DCACHE_DBUG4>>

pub fn app_dram1addr0_ia(&mut self) -> APP_DRAM1ADDR0_IA_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _APP_DCACHE_DBUG5>>

pub fn app_drom0addr0_ia(&mut self) -> APP_DROM0ADDR0_IA_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _APP_DCACHE_DBUG6>>

pub fn app_iram0addr_ia(&mut self) -> APP_IRAM0ADDR_IA_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _APP_DCACHE_DBUG7>>

pub fn app_iram1addr_ia(&mut self) -> APP_IRAM1ADDR_IA_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _APP_DCACHE_DBUG8>>

pub fn app_irom0addr_ia(&mut self) -> APP_IROM0ADDR_IA_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _APP_DCACHE_DBUG9>>

pub fn app_opsdramaddr_ia(&mut self) -> APP_OPSDRAMADDR_IA_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _PRO_CPU_RECORD_CTRL>>

pub fn pro_cpu_pdebug_enable(&mut self) -> PRO_CPU_PDEBUG_ENABLE_W<'_>

Bit 8

pub fn pro_cpu_record_disable(&mut self) -> PRO_CPU_RECORD_DISABLE_W<'_>

Bit 4

pub fn pro_cpu_record_enable(&mut self) -> PRO_CPU_RECORD_ENABLE_W<'_>

Bit 0

impl W<u32, Reg<u32, _PRO_CPU_RECORD_STATUS>>

pub fn pro_cpu_recording(&mut self) -> PRO_CPU_RECORDING_W<'_>

Bit 0

impl W<u32, Reg<u32, _PRO_CPU_RECORD_PID>>

pub fn record_pro_pid(&mut self) -> RECORD_PRO_PID_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _PRO_CPU_RECORD_PDEBUGINST>>

pub fn record_pro_pdebuginst(&mut self) -> RECORD_PRO_PDEBUGINST_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _PRO_CPU_RECORD_PDEBUGSTATUS>>

pub fn record_pro_pdebugstatus(&mut self) -> RECORD_PRO_PDEBUGSTATUS_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _PRO_CPU_RECORD_PDEBUGDATA>>

pub fn record_pro_pdebugdata(&mut self) -> RECORD_PRO_PDEBUGDATA_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _PRO_CPU_RECORD_PDEBUGPC>>

pub fn record_pro_pdebugpc(&mut self) -> RECORD_PRO_PDEBUGPC_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _PRO_CPU_RECORD_PDEBUGLS0STAT>>

pub fn record_pro_pdebugls0stat(&mut self) -> RECORD_PRO_PDEBUGLS0STAT_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _PRO_CPU_RECORD_PDEBUGLS0ADDR>>

pub fn record_pro_pdebugls0addr(&mut self) -> RECORD_PRO_PDEBUGLS0ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _PRO_CPU_RECORD_PDEBUGLS0DATA>>

pub fn record_pro_pdebugls0data(&mut self) -> RECORD_PRO_PDEBUGLS0DATA_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APP_CPU_RECORD_CTRL>>

pub fn app_cpu_pdebug_enable(&mut self) -> APP_CPU_PDEBUG_ENABLE_W<'_>

Bit 8

pub fn app_cpu_record_disable(&mut self) -> APP_CPU_RECORD_DISABLE_W<'_>

Bit 4

pub fn app_cpu_record_enable(&mut self) -> APP_CPU_RECORD_ENABLE_W<'_>

Bit 0

impl W<u32, Reg<u32, _APP_CPU_RECORD_STATUS>>

pub fn app_cpu_recording(&mut self) -> APP_CPU_RECORDING_W<'_>

Bit 0

impl W<u32, Reg<u32, _APP_CPU_RECORD_PID>>

pub fn record_app_pid(&mut self) -> RECORD_APP_PID_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _APP_CPU_RECORD_PDEBUGINST>>

pub fn record_app_pdebuginst(&mut self) -> RECORD_APP_PDEBUGINST_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APP_CPU_RECORD_PDEBUGSTATUS>>

pub fn record_app_pdebugstatus(&mut self) -> RECORD_APP_PDEBUGSTATUS_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _APP_CPU_RECORD_PDEBUGDATA>>

pub fn record_app_pdebugdata(&mut self) -> RECORD_APP_PDEBUGDATA_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APP_CPU_RECORD_PDEBUGPC>>

pub fn record_app_pdebugpc(&mut self) -> RECORD_APP_PDEBUGPC_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APP_CPU_RECORD_PDEBUGLS0STAT>>

pub fn record_app_pdebugls0stat(&mut self) -> RECORD_APP_PDEBUGLS0STAT_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APP_CPU_RECORD_PDEBUGLS0ADDR>>

pub fn record_app_pdebugls0addr(&mut self) -> RECORD_APP_PDEBUGLS0ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APP_CPU_RECORD_PDEBUGLS0DATA>>

pub fn record_app_pdebugls0data(&mut self) -> RECORD_APP_PDEBUGLS0DATA_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _RSA_PD_CTRL>>

pub fn rsa_pd(&mut self) -> RSA_PD_W<'_>

Bit 0

impl W<u32, Reg<u32, _ROM_MPU_TABLE0>>

pub fn rom_mpu_table0(&mut self) -> ROM_MPU_TABLE0_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _ROM_MPU_TABLE1>>

pub fn rom_mpu_table1(&mut self) -> ROM_MPU_TABLE1_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _ROM_MPU_TABLE2>>

pub fn rom_mpu_table2(&mut self) -> ROM_MPU_TABLE2_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _ROM_MPU_TABLE3>>

pub fn rom_mpu_table3(&mut self) -> ROM_MPU_TABLE3_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE0>>

pub fn shrom_mpu_table0(&mut self) -> SHROM_MPU_TABLE0_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE1>>

pub fn shrom_mpu_table1(&mut self) -> SHROM_MPU_TABLE1_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE2>>

pub fn shrom_mpu_table2(&mut self) -> SHROM_MPU_TABLE2_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE3>>

pub fn shrom_mpu_table3(&mut self) -> SHROM_MPU_TABLE3_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE4>>

pub fn shrom_mpu_table4(&mut self) -> SHROM_MPU_TABLE4_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE5>>

pub fn shrom_mpu_table5(&mut self) -> SHROM_MPU_TABLE5_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE6>>

pub fn shrom_mpu_table6(&mut self) -> SHROM_MPU_TABLE6_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE7>>

pub fn shrom_mpu_table7(&mut self) -> SHROM_MPU_TABLE7_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE8>>

pub fn shrom_mpu_table8(&mut self) -> SHROM_MPU_TABLE8_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE9>>

pub fn shrom_mpu_table9(&mut self) -> SHROM_MPU_TABLE9_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE10>>

pub fn shrom_mpu_table10(&mut self) -> SHROM_MPU_TABLE10_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE11>>

pub fn shrom_mpu_table11(&mut self) -> SHROM_MPU_TABLE11_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE12>>

pub fn shrom_mpu_table12(&mut self) -> SHROM_MPU_TABLE12_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE13>>

pub fn shrom_mpu_table13(&mut self) -> SHROM_MPU_TABLE13_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE14>>

pub fn shrom_mpu_table14(&mut self) -> SHROM_MPU_TABLE14_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE15>>

pub fn shrom_mpu_table15(&mut self) -> SHROM_MPU_TABLE15_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE16>>

pub fn shrom_mpu_table16(&mut self) -> SHROM_MPU_TABLE16_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE17>>

pub fn shrom_mpu_table17(&mut self) -> SHROM_MPU_TABLE17_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE18>>

pub fn shrom_mpu_table18(&mut self) -> SHROM_MPU_TABLE18_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE19>>

pub fn shrom_mpu_table19(&mut self) -> SHROM_MPU_TABLE19_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE20>>

pub fn shrom_mpu_table20(&mut self) -> SHROM_MPU_TABLE20_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE21>>

pub fn shrom_mpu_table21(&mut self) -> SHROM_MPU_TABLE21_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE22>>

pub fn shrom_mpu_table22(&mut self) -> SHROM_MPU_TABLE22_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _SHROM_MPU_TABLE23>>

pub fn shrom_mpu_table23(&mut self) -> SHROM_MPU_TABLE23_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _IMMU_TABLE0>>

pub fn immu_table0(&mut self) -> IMMU_TABLE0_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _IMMU_TABLE1>>

pub fn immu_table1(&mut self) -> IMMU_TABLE1_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _IMMU_TABLE2>>

pub fn immu_table2(&mut self) -> IMMU_TABLE2_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _IMMU_TABLE3>>

pub fn immu_table3(&mut self) -> IMMU_TABLE3_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _IMMU_TABLE4>>

pub fn immu_table4(&mut self) -> IMMU_TABLE4_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _IMMU_TABLE5>>

pub fn immu_table5(&mut self) -> IMMU_TABLE5_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _IMMU_TABLE6>>

pub fn immu_table6(&mut self) -> IMMU_TABLE6_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _IMMU_TABLE7>>

pub fn immu_table7(&mut self) -> IMMU_TABLE7_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _IMMU_TABLE8>>

pub fn immu_table8(&mut self) -> IMMU_TABLE8_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _IMMU_TABLE9>>

pub fn immu_table9(&mut self) -> IMMU_TABLE9_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _IMMU_TABLE10>>

pub fn immu_table10(&mut self) -> IMMU_TABLE10_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _IMMU_TABLE11>>

pub fn immu_table11(&mut self) -> IMMU_TABLE11_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _IMMU_TABLE12>>

pub fn immu_table12(&mut self) -> IMMU_TABLE12_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _IMMU_TABLE13>>

pub fn immu_table13(&mut self) -> IMMU_TABLE13_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _IMMU_TABLE14>>

pub fn immu_table14(&mut self) -> IMMU_TABLE14_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _IMMU_TABLE15>>

pub fn immu_table15(&mut self) -> IMMU_TABLE15_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE0>>

pub fn dmmu_table0(&mut self) -> DMMU_TABLE0_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE1>>

pub fn dmmu_table1(&mut self) -> DMMU_TABLE1_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE2>>

pub fn dmmu_table2(&mut self) -> DMMU_TABLE2_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE3>>

pub fn dmmu_table3(&mut self) -> DMMU_TABLE3_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE4>>

pub fn dmmu_table4(&mut self) -> DMMU_TABLE4_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE5>>

pub fn dmmu_table5(&mut self) -> DMMU_TABLE5_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE6>>

pub fn dmmu_table6(&mut self) -> DMMU_TABLE6_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE7>>

pub fn dmmu_table7(&mut self) -> DMMU_TABLE7_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE8>>

pub fn dmmu_table8(&mut self) -> DMMU_TABLE8_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE9>>

pub fn dmmu_table9(&mut self) -> DMMU_TABLE9_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE10>>

pub fn dmmu_table10(&mut self) -> DMMU_TABLE10_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE11>>

pub fn dmmu_table11(&mut self) -> DMMU_TABLE11_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE12>>

pub fn dmmu_table12(&mut self) -> DMMU_TABLE12_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE13>>

pub fn dmmu_table13(&mut self) -> DMMU_TABLE13_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE14>>

pub fn dmmu_table14(&mut self) -> DMMU_TABLE14_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _DMMU_TABLE15>>

pub fn dmmu_table15(&mut self) -> DMMU_TABLE15_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _PRO_INTRUSION_CTRL>>

pub fn pro_intrusion_record_reset_n(
    &mut self
) -> PRO_INTRUSION_RECORD_RESET_N_W<'_>

Bit 0

impl W<u32, Reg<u32, _PRO_INTRUSION_STATUS>>

pub fn pro_intrusion_record(&mut self) -> PRO_INTRUSION_RECORD_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _APP_INTRUSION_CTRL>>

pub fn app_intrusion_record_reset_n(
    &mut self
) -> APP_INTRUSION_RECORD_RESET_N_W<'_>

Bit 0

impl W<u32, Reg<u32, _APP_INTRUSION_STATUS>>

pub fn app_intrusion_record(&mut self) -> APP_INTRUSION_RECORD_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _FRONT_END_MEM_PD>>

pub fn pbus_mem_force_pd(&mut self) -> PBUS_MEM_FORCE_PD_W<'_>

Bit 3

pub fn pbus_mem_force_pu(&mut self) -> PBUS_MEM_FORCE_PU_W<'_>

Bit 2

pub fn agc_mem_force_pd(&mut self) -> AGC_MEM_FORCE_PD_W<'_>

Bit 1

pub fn agc_mem_force_pu(&mut self) -> AGC_MEM_FORCE_PU_W<'_>

Bit 0

impl W<u32, Reg<u32, _MMU_IA_INT_EN>>

pub fn mmu_ia_int_en(&mut self) -> MMU_IA_INT_EN_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _MPU_IA_INT_EN>>

pub fn mpu_ia_int_en(&mut self) -> MPU_IA_INT_EN_W<'_>

Bits 0:16

impl W<u32, Reg<u32, _CACHE_IA_INT_EN>>

pub fn cache_ia_int_en(&mut self) -> CACHE_IA_INT_EN_W<'_>

Bits 0:27

pub fn cache_ia_int_pro_opposite(&mut self) -> CACHE_IA_INT_PRO_OPPOSITE_W<'_>

Bit 19

pub fn cache_ia_int_pro_dram1(&mut self) -> CACHE_IA_INT_PRO_DRAM1_W<'_>

Bit 18

pub fn cache_ia_int_pro_irom0(&mut self) -> CACHE_IA_INT_PRO_IROM0_W<'_>

Bit 17

pub fn cache_ia_int_pro_iram1(&mut self) -> CACHE_IA_INT_PRO_IRAM1_W<'_>

Bit 16

pub fn cache_ia_int_pro_iram0(&mut self) -> CACHE_IA_INT_PRO_IRAM0_W<'_>

Bit 15

pub fn cache_ia_int_pro_drom0(&mut self) -> CACHE_IA_INT_PRO_DROM0_W<'_>

Bit 14

pub fn cache_ia_int_app_opposite(&mut self) -> CACHE_IA_INT_APP_OPPOSITE_W<'_>

Bit 5

pub fn cache_ia_int_app_irom0(&mut self) -> CACHE_IA_INT_APP_IROM0_W<'_>

Bit 3

pub fn cache_ia_int_app_iram1(&mut self) -> CACHE_IA_INT_APP_IRAM1_W<'_>

Bit 2

pub fn cache_ia_int_app_iram0(&mut self) -> CACHE_IA_INT_APP_IRAM0_W<'_>

Bit 1

pub fn cache_ia_int_app_drom0(&mut self) -> CACHE_IA_INT_APP_DROM0_W<'_>

Bit 0

impl W<u32, Reg<u32, _SECURE_BOOT_CTRL>>

pub fn sw_bootloader_sel(&mut self) -> SW_BOOTLOADER_SEL_W<'_>

Bit 0

impl W<u32, Reg<u32, _SPI_DMA_CHAN_SEL>>

pub fn spi3_dma_chan_sel(&mut self) -> SPI3_DMA_CHAN_SEL_W<'_>

Bits 4:5

pub fn spi2_dma_chan_sel(&mut self) -> SPI2_DMA_CHAN_SEL_W<'_>

Bits 2:3

pub fn spi1_dma_chan_sel(&mut self) -> SPI1_DMA_CHAN_SEL_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _PRO_VECBASE_CTRL>>

pub fn pro_out_vecbase_sel(&mut self) -> PRO_OUT_VECBASE_SEL_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _PRO_VECBASE_SET>>

pub fn pro_out_vecbase_reg(&mut self) -> PRO_OUT_VECBASE_REG_W<'_>

Bits 0:21

impl W<u32, Reg<u32, _APP_VECBASE_CTRL>>

pub fn app_out_vecbase_sel(&mut self) -> APP_OUT_VECBASE_SEL_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _APP_VECBASE_SET>>

pub fn app_out_vecbase_reg(&mut self) -> APP_OUT_VECBASE_REG_W<'_>

Bits 0:21

impl W<u32, Reg<u32, _DATE>>

pub fn date(&mut self) -> DATE_W<'_>

Bits 0:27

impl W<u32, Reg<u32, _T0CONFIG>>

pub fn t0_en(&mut self) -> T0_EN_W<'_>

Bit 31

pub fn t0_increase(&mut self) -> T0_INCREASE_W<'_>

Bit 30

pub fn t0_autoreload(&mut self) -> T0_AUTORELOAD_W<'_>

Bit 29

pub fn t0_divider(&mut self) -> T0_DIVIDER_W<'_>

Bits 13:28

pub fn t0_edge_int_en(&mut self) -> T0_EDGE_INT_EN_W<'_>

Bit 12

pub fn t0_level_int_en(&mut self) -> T0_LEVEL_INT_EN_W<'_>

Bit 11

pub fn t0_alarm_en(&mut self) -> T0_ALARM_EN_W<'_>

Bit 10

impl W<u32, Reg<u32, _T0LO>>

pub fn t0_lo(&mut self) -> T0_LO_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _T0HI>>

pub fn t0_hi(&mut self) -> T0_HI_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _T0UPDATE>>

pub fn t0_update(&mut self) -> T0_UPDATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _T0ALARMLO>>

pub fn t0_alarm_lo(&mut self) -> T0_ALARM_LO_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _T0ALARMHI>>

pub fn t0_alarm_hi(&mut self) -> T0_ALARM_HI_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _T0LOADLO>>

pub fn t0_load_lo(&mut self) -> T0_LOAD_LO_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _T0LOADHI>>

pub fn t0_load_hi(&mut self) -> T0_LOAD_HI_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _T0LOAD>>

pub fn t0_load(&mut self) -> T0_LOAD_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _T1CONFIG>>

pub fn t1_en(&mut self) -> T1_EN_W<'_>

Bit 31

pub fn t1_increase(&mut self) -> T1_INCREASE_W<'_>

Bit 30

pub fn t1_autoreload(&mut self) -> T1_AUTORELOAD_W<'_>

Bit 29

pub fn t1_divider(&mut self) -> T1_DIVIDER_W<'_>

Bits 13:28

pub fn t1_edge_int_en(&mut self) -> T1_EDGE_INT_EN_W<'_>

Bit 12

pub fn t1_level_int_en(&mut self) -> T1_LEVEL_INT_EN_W<'_>

Bit 11

pub fn t1_alarm_en(&mut self) -> T1_ALARM_EN_W<'_>

Bit 10

impl W<u32, Reg<u32, _T1LO>>

pub fn t1_lo(&mut self) -> T1_LO_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _T1HI>>

pub fn t1_hi(&mut self) -> T1_HI_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _T1UPDATE>>

pub fn t1_update(&mut self) -> T1_UPDATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _T1ALARMLO>>

pub fn t1_alarm_lo(&mut self) -> T1_ALARM_LO_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _T1ALARMHI>>

pub fn t1_alarm_hi(&mut self) -> T1_ALARM_HI_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _T1LOADLO>>

pub fn t1_load_lo(&mut self) -> T1_LOAD_LO_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _T1LOADHI>>

pub fn t1_load_hi(&mut self) -> T1_LOAD_HI_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _T1LOAD>>

pub fn t1_load(&mut self) -> T1_LOAD_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _WDTCONFIG0>>

pub fn wdt_en(&mut self) -> WDT_EN_W<'_>

Bit 31

pub fn wdt_stg0(&mut self) -> WDT_STG0_W<'_>

Bits 29:30

pub fn wdt_stg1(&mut self) -> WDT_STG1_W<'_>

Bits 27:28

pub fn wdt_stg2(&mut self) -> WDT_STG2_W<'_>

Bits 25:26

pub fn wdt_stg3(&mut self) -> WDT_STG3_W<'_>

Bits 23:24

pub fn wdt_edge_int_en(&mut self) -> WDT_EDGE_INT_EN_W<'_>

Bit 22

pub fn wdt_level_int_en(&mut self) -> WDT_LEVEL_INT_EN_W<'_>

Bit 21

pub fn wdt_cpu_reset_length(&mut self) -> WDT_CPU_RESET_LENGTH_W<'_>

Bits 18:20

pub fn wdt_sys_reset_length(&mut self) -> WDT_SYS_RESET_LENGTH_W<'_>

Bits 15:17

pub fn wdt_flashboot_mod_en(&mut self) -> WDT_FLASHBOOT_MOD_EN_W<'_>

Bit 14

impl W<u32, Reg<u32, _WDTCONFIG1>>

pub fn wdt_clk_prescale(&mut self) -> WDT_CLK_PRESCALE_W<'_>

Bits 16:31

impl W<u32, Reg<u32, _WDTCONFIG2>>

pub fn wdt_stg0_hold(&mut self) -> WDT_STG0_HOLD_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _WDTCONFIG3>>

pub fn wdt_stg1_hold(&mut self) -> WDT_STG1_HOLD_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _WDTCONFIG4>>

pub fn wdt_stg2_hold(&mut self) -> WDT_STG2_HOLD_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _WDTCONFIG5>>

pub fn wdt_stg3_hold(&mut self) -> WDT_STG3_HOLD_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _WDTFEED>>

pub fn wdt_feed(&mut self) -> WDT_FEED_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _WDTWPROTECT>>

pub fn wdt_wkey(&mut self) -> WDT_WKEY_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _RTCCALICFG>>

pub fn start(&mut self) -> START_W<'_>

Bit 31

pub fn max(&mut self) -> MAX_W<'_>

Bits 16:30

pub fn rdy(&mut self) -> RDY_W<'_>

Bit 15

pub fn clk_sel(&mut self) -> CLK_SEL_W<'_>

Bits 13:14

pub fn start_cycling(&mut self) -> START_CYCLING_W<'_>

Bit 12

impl W<u32, Reg<u32, _RTCCALICFG1>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 7:31

impl W<u32, Reg<u32, _LACTCONFIG>>

pub fn lact_en(&mut self) -> LACT_EN_W<'_>

Bit 31

pub fn lact_increase(&mut self) -> LACT_INCREASE_W<'_>

Bit 30

pub fn lact_autoreload(&mut self) -> LACT_AUTORELOAD_W<'_>

Bit 29

pub fn lact_divider(&mut self) -> LACT_DIVIDER_W<'_>

Bits 13:28

pub fn lact_edge_int_en(&mut self) -> LACT_EDGE_INT_EN_W<'_>

Bit 12

pub fn lact_level_int_en(&mut self) -> LACT_LEVEL_INT_EN_W<'_>

Bit 11

pub fn lact_alarm_en(&mut self) -> LACT_ALARM_EN_W<'_>

Bit 10

pub fn lact_lac_en(&mut self) -> LACT_LAC_EN_W<'_>

Bit 9

pub fn lact_cpst_en(&mut self) -> LACT_CPST_EN_W<'_>

Bit 8

pub fn lact_rtc_only(&mut self) -> LACT_RTC_ONLY_W<'_>

Bit 7

impl W<u32, Reg<u32, _LACTRTC>>

pub fn lact_rtc_step_len(&mut self) -> LACT_RTC_STEP_LEN_W<'_>

Bits 6:31

impl W<u32, Reg<u32, _LACTLO>>

pub fn lact_lo(&mut self) -> LACT_LO_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _LACTHI>>

pub fn lact_hi(&mut self) -> LACT_HI_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _LACTUPDATE>>

pub fn lact_update(&mut self) -> LACT_UPDATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _LACTALARMLO>>

pub fn lact_alarm_lo(&mut self) -> LACT_ALARM_LO_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _LACTALARMHI>>

pub fn lact_alarm_hi(&mut self) -> LACT_ALARM_HI_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _LACTLOADLO>>

pub fn lact_load_lo(&mut self) -> LACT_LOAD_LO_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _LACTLOADHI>>

pub fn lact_load_hi(&mut self) -> LACT_LOAD_HI_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _LACTLOAD>>

pub fn lact_load(&mut self) -> LACT_LOAD_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _INT_ENA_TIMERS>>

pub fn lact_int_ena(&mut self) -> LACT_INT_ENA_W<'_>

Bit 3

pub fn wdt_int_ena(&mut self) -> WDT_INT_ENA_W<'_>

Bit 2

pub fn t1_int_ena(&mut self) -> T1_INT_ENA_W<'_>

Bit 1

pub fn t0_int_ena(&mut self) -> T0_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_RAW_TIMERS>>

pub fn lact_int_raw(&mut self) -> LACT_INT_RAW_W<'_>

Bit 3

pub fn wdt_int_raw(&mut self) -> WDT_INT_RAW_W<'_>

Bit 2

pub fn t1_int_raw(&mut self) -> T1_INT_RAW_W<'_>

Bit 1

pub fn t0_int_raw(&mut self) -> T0_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ST_TIMERS>>

pub fn lact_int_st(&mut self) -> LACT_INT_ST_W<'_>

Bit 3

pub fn wdt_int_st(&mut self) -> WDT_INT_ST_W<'_>

Bit 2

pub fn t1_int_st(&mut self) -> T1_INT_ST_W<'_>

Bit 1

pub fn t0_int_st(&mut self) -> T0_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_CLR_TIMERS>>

pub fn lact_int_clr(&mut self) -> LACT_INT_CLR_W<'_>

Bit 3

pub fn wdt_int_clr(&mut self) -> WDT_INT_CLR_W<'_>

Bit 2

pub fn t1_int_clr(&mut self) -> T1_INT_CLR_W<'_>

Bit 1

pub fn t0_int_clr(&mut self) -> T0_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, _NTIMERS_DATE>>

pub fn ntimers_date(&mut self) -> NTIMERS_DATE_W<'_>

Bits 0:27

impl W<u32, Reg<u32, _TIMGCLK>>

pub fn clk_en(&mut self) -> CLK_EN_W<'_>

Bit 31

impl W<u32, Reg<u32, _SIGMADELTA0>>

pub fn sd0_prescale(&mut self) -> SD0_PRESCALE_W<'_>

Bits 8:15

pub fn sd0_in(&mut self) -> SD0_IN_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SIGMADELTA1>>

pub fn sd1_prescale(&mut self) -> SD1_PRESCALE_W<'_>

Bits 8:15

pub fn sd1_in(&mut self) -> SD1_IN_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SIGMADELTA2>>

pub fn sd2_prescale(&mut self) -> SD2_PRESCALE_W<'_>

Bits 8:15

pub fn sd2_in(&mut self) -> SD2_IN_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SIGMADELTA3>>

pub fn sd3_prescale(&mut self) -> SD3_PRESCALE_W<'_>

Bits 8:15

pub fn sd3_in(&mut self) -> SD3_IN_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SIGMADELTA4>>

pub fn sd4_prescale(&mut self) -> SD4_PRESCALE_W<'_>

Bits 8:15

pub fn sd4_in(&mut self) -> SD4_IN_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SIGMADELTA5>>

pub fn sd5_prescale(&mut self) -> SD5_PRESCALE_W<'_>

Bits 8:15

pub fn sd5_in(&mut self) -> SD5_IN_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SIGMADELTA6>>

pub fn sd6_prescale(&mut self) -> SD6_PRESCALE_W<'_>

Bits 8:15

pub fn sd6_in(&mut self) -> SD6_IN_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SIGMADELTA7>>

pub fn sd7_prescale(&mut self) -> SD7_PRESCALE_W<'_>

Bits 8:15

pub fn sd7_in(&mut self) -> SD7_IN_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SIGMADELTA_CG>>

pub fn sd_clk_en(&mut self) -> SD_CLK_EN_W<'_>

Bit 31

impl W<u32, Reg<u32, _SIGMADELTA_MISC>>

pub fn spi_swap(&mut self) -> SPI_SWAP_W<'_>

Bit 31

impl W<u32, Reg<u32, _SIGMADELTA_VERSION>>

pub fn sd_date(&mut self) -> SD_DATE_W<'_>

Bits 0:27

impl W<u32, Reg<u32, _PIN_CTRL>>

pub fn pin_ctrl_clk3(&mut self) -> PIN_CTRL_CLK3_W<'_>

Bits 8:10

pub fn pin_ctrl_clk2(&mut self) -> PIN_CTRL_CLK2_W<'_>

Bits 4:6

pub fn pin_ctrl_clk1(&mut self) -> PIN_CTRL_CLK1_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _GPIO36>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO37>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO38>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO39>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO34>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures drive strength during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO35>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO32>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO33>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO25>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO26>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO27>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _MTMS>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _MTDI>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _MTCK>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _MTDO>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO2>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO0>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO4>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO16>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO17>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _SD_DATA2>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _SD_DATA3>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _SD_CMD>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _SD_CLK>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _SD_DATA0>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _SD_DATA1>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO5>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO18>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO19>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO20>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO21>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO22>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _U0RXD>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _U0TXD>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO23>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _GPIO24>>

pub fn mcu_sel(&mut self) -> MCU_SEL_W<'_>

Bits 12:13 - configures IO_MUX function

pub fn fun_drv(&mut self) -> FUN_DRV_W<'_>

Bits 10:11 - configures drive strength

pub fn fun_ie(&mut self) -> FUN_IE_W<'_>

Bit 9 - configures input enable

pub fn fun_wpu(&mut self) -> FUN_WPU_W<'_>

Bit 8 - configures pull up

pub fn fun_wpd(&mut self) -> FUN_WPD_W<'_>

Bit 7 - configures pull down

pub fn mcu_drv(&mut self) -> MCU_DRV_W<'_>

Bits 5:6 - configures drive strength during sleep mode

pub fn mcu_ie(&mut self) -> MCU_IE_W<'_>

Bit 4 - configures input enable during sleep mode

pub fn mcu_wpu(&mut self) -> MCU_WPU_W<'_>

Bit 3 - configures pull up during sleep mode

pub fn mcu_wpd(&mut self) -> MCU_WPD_W<'_>

Bit 2 - configures pull down during sleep mode

pub fn slp_sel(&mut self) -> SLP_SEL_W<'_>

Bit 1 - configures sleep mode selection

pub fn mcu_oe(&mut self) -> MCU_OE_W<'_>

Bit 0 - configures output enable during sleep mode

impl W<u32, Reg<u32, _CONF>>

pub fn sig_loopback(&mut self) -> SIG_LOOPBACK_W<'_>

Bit 18

pub fn rx_msb_right(&mut self) -> RX_MSB_RIGHT_W<'_>

Bit 17

pub fn tx_msb_right(&mut self) -> TX_MSB_RIGHT_W<'_>

Bit 16

pub fn rx_mono(&mut self) -> RX_MONO_W<'_>

Bit 15

pub fn tx_mono(&mut self) -> TX_MONO_W<'_>

Bit 14

pub fn rx_short_sync(&mut self) -> RX_SHORT_SYNC_W<'_>

Bit 13

pub fn tx_short_sync(&mut self) -> TX_SHORT_SYNC_W<'_>

Bit 12

pub fn rx_msb_shift(&mut self) -> RX_MSB_SHIFT_W<'_>

Bit 11

pub fn tx_msb_shift(&mut self) -> TX_MSB_SHIFT_W<'_>

Bit 10

pub fn rx_right_first(&mut self) -> RX_RIGHT_FIRST_W<'_>

Bit 9

pub fn tx_right_first(&mut self) -> TX_RIGHT_FIRST_W<'_>

Bit 8

pub fn rx_slave_mod(&mut self) -> RX_SLAVE_MOD_W<'_>

Bit 7

pub fn tx_slave_mod(&mut self) -> TX_SLAVE_MOD_W<'_>

Bit 6

pub fn rx_start(&mut self) -> RX_START_W<'_>

Bit 5

pub fn tx_start(&mut self) -> TX_START_W<'_>

Bit 4

pub fn rx_fifo_reset(&mut self) -> RX_FIFO_RESET_W<'_>

Bit 3

pub fn tx_fifo_reset(&mut self) -> TX_FIFO_RESET_W<'_>

Bit 2

pub fn rx_reset(&mut self) -> RX_RESET_W<'_>

Bit 1

pub fn tx_reset(&mut self) -> TX_RESET_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_RAW>>

pub fn out_total_eof_int_raw(&mut self) -> OUT_TOTAL_EOF_INT_RAW_W<'_>

Bit 16

pub fn in_dscr_empty_int_raw(&mut self) -> IN_DSCR_EMPTY_INT_RAW_W<'_>

Bit 15

pub fn out_dscr_err_int_raw(&mut self) -> OUT_DSCR_ERR_INT_RAW_W<'_>

Bit 14

pub fn in_dscr_err_int_raw(&mut self) -> IN_DSCR_ERR_INT_RAW_W<'_>

Bit 13

pub fn out_eof_int_raw(&mut self) -> OUT_EOF_INT_RAW_W<'_>

Bit 12

pub fn out_done_int_raw(&mut self) -> OUT_DONE_INT_RAW_W<'_>

Bit 11

pub fn in_err_eof_int_raw(&mut self) -> IN_ERR_EOF_INT_RAW_W<'_>

Bit 10

pub fn in_suc_eof_int_raw(&mut self) -> IN_SUC_EOF_INT_RAW_W<'_>

Bit 9

pub fn in_done_int_raw(&mut self) -> IN_DONE_INT_RAW_W<'_>

Bit 8

pub fn tx_hung_int_raw(&mut self) -> TX_HUNG_INT_RAW_W<'_>

Bit 7

pub fn rx_hung_int_raw(&mut self) -> RX_HUNG_INT_RAW_W<'_>

Bit 6

pub fn tx_rempty_int_raw(&mut self) -> TX_REMPTY_INT_RAW_W<'_>

Bit 5

pub fn tx_wfull_int_raw(&mut self) -> TX_WFULL_INT_RAW_W<'_>

Bit 4

pub fn rx_rempty_int_raw(&mut self) -> RX_REMPTY_INT_RAW_W<'_>

Bit 3

pub fn rx_wfull_int_raw(&mut self) -> RX_WFULL_INT_RAW_W<'_>

Bit 2

pub fn tx_put_data_int_raw(&mut self) -> TX_PUT_DATA_INT_RAW_W<'_>

Bit 1

pub fn rx_take_data_int_raw(&mut self) -> RX_TAKE_DATA_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ST>>

pub fn out_total_eof_int_st(&mut self) -> OUT_TOTAL_EOF_INT_ST_W<'_>

Bit 16

pub fn in_dscr_empty_int_st(&mut self) -> IN_DSCR_EMPTY_INT_ST_W<'_>

Bit 15

pub fn out_dscr_err_int_st(&mut self) -> OUT_DSCR_ERR_INT_ST_W<'_>

Bit 14

pub fn in_dscr_err_int_st(&mut self) -> IN_DSCR_ERR_INT_ST_W<'_>

Bit 13

pub fn out_eof_int_st(&mut self) -> OUT_EOF_INT_ST_W<'_>

Bit 12

pub fn out_done_int_st(&mut self) -> OUT_DONE_INT_ST_W<'_>

Bit 11

pub fn in_err_eof_int_st(&mut self) -> IN_ERR_EOF_INT_ST_W<'_>

Bit 10

pub fn in_suc_eof_int_st(&mut self) -> IN_SUC_EOF_INT_ST_W<'_>

Bit 9

pub fn in_done_int_st(&mut self) -> IN_DONE_INT_ST_W<'_>

Bit 8

pub fn tx_hung_int_st(&mut self) -> TX_HUNG_INT_ST_W<'_>

Bit 7

pub fn rx_hung_int_st(&mut self) -> RX_HUNG_INT_ST_W<'_>

Bit 6

pub fn tx_rempty_int_st(&mut self) -> TX_REMPTY_INT_ST_W<'_>

Bit 5

pub fn tx_wfull_int_st(&mut self) -> TX_WFULL_INT_ST_W<'_>

Bit 4

pub fn rx_rempty_int_st(&mut self) -> RX_REMPTY_INT_ST_W<'_>

Bit 3

pub fn rx_wfull_int_st(&mut self) -> RX_WFULL_INT_ST_W<'_>

Bit 2

pub fn tx_put_data_int_st(&mut self) -> TX_PUT_DATA_INT_ST_W<'_>

Bit 1

pub fn rx_take_data_int_st(&mut self) -> RX_TAKE_DATA_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ENA>>

pub fn out_total_eof_int_ena(&mut self) -> OUT_TOTAL_EOF_INT_ENA_W<'_>

Bit 16

pub fn in_dscr_empty_int_ena(&mut self) -> IN_DSCR_EMPTY_INT_ENA_W<'_>

Bit 15

pub fn out_dscr_err_int_ena(&mut self) -> OUT_DSCR_ERR_INT_ENA_W<'_>

Bit 14

pub fn in_dscr_err_int_ena(&mut self) -> IN_DSCR_ERR_INT_ENA_W<'_>

Bit 13

pub fn out_eof_int_ena(&mut self) -> OUT_EOF_INT_ENA_W<'_>

Bit 12

pub fn out_done_int_ena(&mut self) -> OUT_DONE_INT_ENA_W<'_>

Bit 11

pub fn in_err_eof_int_ena(&mut self) -> IN_ERR_EOF_INT_ENA_W<'_>

Bit 10

pub fn in_suc_eof_int_ena(&mut self) -> IN_SUC_EOF_INT_ENA_W<'_>

Bit 9

pub fn in_done_int_ena(&mut self) -> IN_DONE_INT_ENA_W<'_>

Bit 8

pub fn tx_hung_int_ena(&mut self) -> TX_HUNG_INT_ENA_W<'_>

Bit 7

pub fn rx_hung_int_ena(&mut self) -> RX_HUNG_INT_ENA_W<'_>

Bit 6

pub fn tx_rempty_int_ena(&mut self) -> TX_REMPTY_INT_ENA_W<'_>

Bit 5

pub fn tx_wfull_int_ena(&mut self) -> TX_WFULL_INT_ENA_W<'_>

Bit 4

pub fn rx_rempty_int_ena(&mut self) -> RX_REMPTY_INT_ENA_W<'_>

Bit 3

pub fn rx_wfull_int_ena(&mut self) -> RX_WFULL_INT_ENA_W<'_>

Bit 2

pub fn tx_put_data_int_ena(&mut self) -> TX_PUT_DATA_INT_ENA_W<'_>

Bit 1

pub fn rx_take_data_int_ena(&mut self) -> RX_TAKE_DATA_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_CLR>>

pub fn out_total_eof_int_clr(&mut self) -> OUT_TOTAL_EOF_INT_CLR_W<'_>

Bit 16

pub fn in_dscr_empty_int_clr(&mut self) -> IN_DSCR_EMPTY_INT_CLR_W<'_>

Bit 15

pub fn out_dscr_err_int_clr(&mut self) -> OUT_DSCR_ERR_INT_CLR_W<'_>

Bit 14

pub fn in_dscr_err_int_clr(&mut self) -> IN_DSCR_ERR_INT_CLR_W<'_>

Bit 13

pub fn out_eof_int_clr(&mut self) -> OUT_EOF_INT_CLR_W<'_>

Bit 12

pub fn out_done_int_clr(&mut self) -> OUT_DONE_INT_CLR_W<'_>

Bit 11

pub fn in_err_eof_int_clr(&mut self) -> IN_ERR_EOF_INT_CLR_W<'_>

Bit 10

pub fn in_suc_eof_int_clr(&mut self) -> IN_SUC_EOF_INT_CLR_W<'_>

Bit 9

pub fn in_done_int_clr(&mut self) -> IN_DONE_INT_CLR_W<'_>

Bit 8

pub fn tx_hung_int_clr(&mut self) -> TX_HUNG_INT_CLR_W<'_>

Bit 7

pub fn rx_hung_int_clr(&mut self) -> RX_HUNG_INT_CLR_W<'_>

Bit 6

pub fn tx_rempty_int_clr(&mut self) -> TX_REMPTY_INT_CLR_W<'_>

Bit 5

pub fn tx_wfull_int_clr(&mut self) -> TX_WFULL_INT_CLR_W<'_>

Bit 4

pub fn rx_rempty_int_clr(&mut self) -> RX_REMPTY_INT_CLR_W<'_>

Bit 3

pub fn rx_wfull_int_clr(&mut self) -> RX_WFULL_INT_CLR_W<'_>

Bit 2

pub fn put_data_int_clr(&mut self) -> PUT_DATA_INT_CLR_W<'_>

Bit 1

pub fn take_data_int_clr(&mut self) -> TAKE_DATA_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, _TIMING>>

pub fn tx_bck_in_inv(&mut self) -> TX_BCK_IN_INV_W<'_>

Bit 24

pub fn data_enable_delay(&mut self) -> DATA_ENABLE_DELAY_W<'_>

Bits 22:23

pub fn rx_dsync_sw(&mut self) -> RX_DSYNC_SW_W<'_>

Bit 21

pub fn tx_dsync_sw(&mut self) -> TX_DSYNC_SW_W<'_>

Bit 20

pub fn rx_bck_out_delay(&mut self) -> RX_BCK_OUT_DELAY_W<'_>

Bits 18:19

pub fn rx_ws_out_delay(&mut self) -> RX_WS_OUT_DELAY_W<'_>

Bits 16:17

pub fn tx_sd_out_delay(&mut self) -> TX_SD_OUT_DELAY_W<'_>

Bits 14:15

pub fn tx_ws_out_delay(&mut self) -> TX_WS_OUT_DELAY_W<'_>

Bits 12:13

pub fn tx_bck_out_delay(&mut self) -> TX_BCK_OUT_DELAY_W<'_>

Bits 10:11

pub fn rx_sd_in_delay(&mut self) -> RX_SD_IN_DELAY_W<'_>

Bits 8:9

pub fn rx_ws_in_delay(&mut self) -> RX_WS_IN_DELAY_W<'_>

Bits 6:7

pub fn rx_bck_in_delay(&mut self) -> RX_BCK_IN_DELAY_W<'_>

Bits 4:5

pub fn tx_ws_in_delay(&mut self) -> TX_WS_IN_DELAY_W<'_>

Bits 2:3

pub fn tx_bck_in_delay(&mut self) -> TX_BCK_IN_DELAY_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _FIFO_CONF>>

pub fn rx_fifo_mod_force_en(&mut self) -> RX_FIFO_MOD_FORCE_EN_W<'_>

Bit 20

pub fn tx_fifo_mod_force_en(&mut self) -> TX_FIFO_MOD_FORCE_EN_W<'_>

Bit 19

pub fn rx_fifo_mod(&mut self) -> RX_FIFO_MOD_W<'_>

Bits 16:18

pub fn tx_fifo_mod(&mut self) -> TX_FIFO_MOD_W<'_>

Bits 13:15

pub fn dscr_en(&mut self) -> DSCR_EN_W<'_>

Bit 12

pub fn tx_data_num(&mut self) -> TX_DATA_NUM_W<'_>

Bits 6:11

pub fn rx_data_num(&mut self) -> RX_DATA_NUM_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _RXEOF_NUM>>

pub fn rx_eof_num(&mut self) -> RX_EOF_NUM_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CONF_SIGLE_DATA>>

pub fn sigle_data(&mut self) -> SIGLE_DATA_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CONF_CHAN>>

pub fn rx_chan_mod(&mut self) -> RX_CHAN_MOD_W<'_>

Bits 3:4

pub fn tx_chan_mod(&mut self) -> TX_CHAN_MOD_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _OUT_LINK>>

pub fn outlink_park(&mut self) -> OUTLINK_PARK_W<'_>

Bit 31

pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<'_>

Bit 30

pub fn outlink_start(&mut self) -> OUTLINK_START_W<'_>

Bit 29

pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<'_>

Bit 28

pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _IN_LINK>>

pub fn inlink_park(&mut self) -> INLINK_PARK_W<'_>

Bit 31

pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<'_>

Bit 30

pub fn inlink_start(&mut self) -> INLINK_START_W<'_>

Bit 29

pub fn inlink_stop(&mut self) -> INLINK_STOP_W<'_>

Bit 28

pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _OUT_EOF_DES_ADDR>>

pub fn out_eof_des_addr(&mut self) -> OUT_EOF_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _IN_EOF_DES_ADDR>>

pub fn in_suc_eof_des_addr(&mut self) -> IN_SUC_EOF_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _OUT_EOF_BFR_DES_ADDR>>

pub fn out_eof_bfr_des_addr(&mut self) -> OUT_EOF_BFR_DES_ADDR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _AHB_TEST>>

pub fn ahb_testaddr(&mut self) -> AHB_TESTADDR_W<'_>

Bits 4:5

pub fn ahb_testmode(&mut self) -> AHB_TESTMODE_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _INLINK_DSCR>>

pub fn inlink_dscr(&mut self) -> INLINK_DSCR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _INLINK_DSCR_BF0>>

pub fn inlink_dscr_bf0(&mut self) -> INLINK_DSCR_BF0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _INLINK_DSCR_BF1>>

pub fn inlink_dscr_bf1(&mut self) -> INLINK_DSCR_BF1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _OUTLINK_DSCR>>

pub fn outlink_dscr(&mut self) -> OUTLINK_DSCR_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _OUTLINK_DSCR_BF0>>

pub fn outlink_dscr_bf0(&mut self) -> OUTLINK_DSCR_BF0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _OUTLINK_DSCR_BF1>>

pub fn outlink_dscr_bf1(&mut self) -> OUTLINK_DSCR_BF1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _LC_CONF>>

pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<'_>

Bit 13

pub fn check_owner(&mut self) -> CHECK_OWNER_W<'_>

Bit 12

pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<'_>

Bit 11

pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<'_>

Bit 10

pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<'_>

Bit 9

pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<'_>

Bit 8

pub fn out_no_restart_clr(&mut self) -> OUT_NO_RESTART_CLR_W<'_>

Bit 7

pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<'_>

Bit 6

pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<'_>

Bit 5

pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<'_>

Bit 4

pub fn ahbm_rst(&mut self) -> AHBM_RST_W<'_>

Bit 3

pub fn ahbm_fifo_rst(&mut self) -> AHBM_FIFO_RST_W<'_>

Bit 2

pub fn out_rst(&mut self) -> OUT_RST_W<'_>

Bit 1

pub fn in_rst(&mut self) -> IN_RST_W<'_>

Bit 0

impl W<u32, Reg<u32, _OUTFIFO_PUSH>>

pub fn outfifo_push(&mut self) -> OUTFIFO_PUSH_W<'_>

Bit 16

pub fn outfifo_wdata(&mut self) -> OUTFIFO_WDATA_W<'_>

Bits 0:8

impl W<u32, Reg<u32, _INFIFO_POP>>

pub fn infifo_pop(&mut self) -> INFIFO_POP_W<'_>

Bit 16

pub fn infifo_rdata(&mut self) -> INFIFO_RDATA_W<'_>

Bits 0:11

impl W<u32, Reg<u32, _LC_STATE0>>

pub fn lc_state0(&mut self) -> LC_STATE0_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _LC_STATE1>>

pub fn lc_state1(&mut self) -> LC_STATE1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _LC_HUNG_CONF>>

pub fn lc_fifo_timeout_ena(&mut self) -> LC_FIFO_TIMEOUT_ENA_W<'_>

Bit 11

pub fn lc_fifo_timeout_shift(&mut self) -> LC_FIFO_TIMEOUT_SHIFT_W<'_>

Bits 8:10

pub fn lc_fifo_timeout(&mut self) -> LC_FIFO_TIMEOUT_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CVSD_CONF0>>

pub fn cvsd_y_min(&mut self) -> CVSD_Y_MIN_W<'_>

Bits 16:31

pub fn cvsd_y_max(&mut self) -> CVSD_Y_MAX_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CVSD_CONF1>>

pub fn cvsd_sigma_min(&mut self) -> CVSD_SIGMA_MIN_W<'_>

Bits 16:31

pub fn cvsd_sigma_max(&mut self) -> CVSD_SIGMA_MAX_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CVSD_CONF2>>

pub fn cvsd_h(&mut self) -> CVSD_H_W<'_>

Bits 16:18

pub fn cvsd_beta(&mut self) -> CVSD_BETA_W<'_>

Bits 6:15

pub fn cvsd_j(&mut self) -> CVSD_J_W<'_>

Bits 3:5

pub fn cvsd_k(&mut self) -> CVSD_K_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _PLC_CONF0>>

pub fn n_min_err(&mut self) -> N_MIN_ERR_W<'_>

Bits 25:27

pub fn pack_len_8k(&mut self) -> PACK_LEN_8K_W<'_>

Bits 20:24

pub fn max_slide_sample(&mut self) -> MAX_SLIDE_SAMPLE_W<'_>

Bits 12:19

pub fn shift_rate(&mut self) -> SHIFT_RATE_W<'_>

Bits 9:11

pub fn n_err_seg(&mut self) -> N_ERR_SEG_W<'_>

Bits 6:8

pub fn good_pack_max(&mut self) -> GOOD_PACK_MAX_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _PLC_CONF1>>

pub fn slide_win_len(&mut self) -> SLIDE_WIN_LEN_W<'_>

Bits 24:31

pub fn bad_ola_win2_para(&mut self) -> BAD_OLA_WIN2_PARA_W<'_>

Bits 16:23

pub fn bad_ola_win2_para_shift(&mut self) -> BAD_OLA_WIN2_PARA_SHIFT_W<'_>

Bits 12:15

pub fn bad_cef_atten_para_shift(&mut self) -> BAD_CEF_ATTEN_PARA_SHIFT_W<'_>

Bits 8:11

pub fn bad_cef_atten_para(&mut self) -> BAD_CEF_ATTEN_PARA_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _PLC_CONF2>>

pub fn min_period(&mut self) -> MIN_PERIOD_W<'_>

Bits 2:6

pub fn cvsd_seg_mod(&mut self) -> CVSD_SEG_MOD_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _ESCO_CONF0>>

pub fn plc2dma_en(&mut self) -> PLC2DMA_EN_W<'_>

Bit 12

pub fn plc_en(&mut self) -> PLC_EN_W<'_>

Bit 11

pub fn cvsd_dec_reset(&mut self) -> CVSD_DEC_RESET_W<'_>

Bit 10

pub fn cvsd_dec_start(&mut self) -> CVSD_DEC_START_W<'_>

Bit 9

pub fn esco_cvsd_inf_en(&mut self) -> ESCO_CVSD_INF_EN_W<'_>

Bit 8

pub fn esco_cvsd_pack_len_8k(&mut self) -> ESCO_CVSD_PACK_LEN_8K_W<'_>

Bits 3:7

pub fn esco_cvsd_dec_pack_err(&mut self) -> ESCO_CVSD_DEC_PACK_ERR_W<'_>

Bit 2

pub fn esco_chan_mod(&mut self) -> ESCO_CHAN_MOD_W<'_>

Bit 1

pub fn esco_en(&mut self) -> ESCO_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _SCO_CONF0>>

pub fn cvsd_enc_reset(&mut self) -> CVSD_ENC_RESET_W<'_>

Bit 3

pub fn cvsd_enc_start(&mut self) -> CVSD_ENC_START_W<'_>

Bit 2

pub fn sco_no_i2s_en(&mut self) -> SCO_NO_I2S_EN_W<'_>

Bit 1

pub fn sco_with_i2s_en(&mut self) -> SCO_WITH_I2S_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _CONF1>>

pub fn tx_zeros_rm_en(&mut self) -> TX_ZEROS_RM_EN_W<'_>

Bit 9

pub fn tx_stop_en(&mut self) -> TX_STOP_EN_W<'_>

Bit 8

pub fn rx_pcm_bypass(&mut self) -> RX_PCM_BYPASS_W<'_>

Bit 7

pub fn rx_pcm_conf(&mut self) -> RX_PCM_CONF_W<'_>

Bits 4:6

pub fn tx_pcm_bypass(&mut self) -> TX_PCM_BYPASS_W<'_>

Bit 3

pub fn tx_pcm_conf(&mut self) -> TX_PCM_CONF_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _PD_CONF>>

pub fn plc_mem_force_pu(&mut self) -> PLC_MEM_FORCE_PU_W<'_>

Bit 3

pub fn plc_mem_force_pd(&mut self) -> PLC_MEM_FORCE_PD_W<'_>

Bit 2

pub fn fifo_force_pu(&mut self) -> FIFO_FORCE_PU_W<'_>

Bit 1

pub fn fifo_force_pd(&mut self) -> FIFO_FORCE_PD_W<'_>

Bit 0

impl W<u32, Reg<u32, _CONF2>>

pub fn inter_valid_en(&mut self) -> INTER_VALID_EN_W<'_>

Bit 7

pub fn ext_adc_start_en(&mut self) -> EXT_ADC_START_EN_W<'_>

Bit 6

pub fn lcd_en(&mut self) -> LCD_EN_W<'_>

Bit 5

pub fn data_enable(&mut self) -> DATA_ENABLE_W<'_>

Bit 4

pub fn data_enable_test_en(&mut self) -> DATA_ENABLE_TEST_EN_W<'_>

Bit 3

pub fn lcd_tx_sdx2_en(&mut self) -> LCD_TX_SDX2_EN_W<'_>

Bit 2

pub fn lcd_tx_wrx2_en(&mut self) -> LCD_TX_WRX2_EN_W<'_>

Bit 1

pub fn camera_en(&mut self) -> CAMERA_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _CLKM_CONF>>

pub fn clka_ena(&mut self) -> CLKA_ENA_W<'_>

Bit 21

pub fn clk_en(&mut self) -> CLK_EN_W<'_>

Bit 20

pub fn clkm_div_a(&mut self) -> CLKM_DIV_A_W<'_>

Bits 14:19

pub fn clkm_div_b(&mut self) -> CLKM_DIV_B_W<'_>

Bits 8:13

pub fn clkm_div_num(&mut self) -> CLKM_DIV_NUM_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SAMPLE_RATE_CONF>>

pub fn rx_bits_mod(&mut self) -> RX_BITS_MOD_W<'_>

Bits 18:23

pub fn tx_bits_mod(&mut self) -> TX_BITS_MOD_W<'_>

Bits 12:17

pub fn rx_bck_div_num(&mut self) -> RX_BCK_DIV_NUM_W<'_>

Bits 6:11

pub fn tx_bck_div_num(&mut self) -> TX_BCK_DIV_NUM_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _PDM_CONF>>

pub fn tx_pdm_hp_bypass(&mut self) -> TX_PDM_HP_BYPASS_W<'_>

Bit 25

pub fn rx_pdm_sinc_dsr_16_en(&mut self) -> RX_PDM_SINC_DSR_16_EN_W<'_>

Bit 24

pub fn tx_pdm_sigmadelta_in_shift(&mut self) -> TX_PDM_SIGMADELTA_IN_SHIFT_W<'_>

Bits 22:23

pub fn tx_pdm_sinc_in_shift(&mut self) -> TX_PDM_SINC_IN_SHIFT_W<'_>

Bits 20:21

pub fn tx_pdm_lp_in_shift(&mut self) -> TX_PDM_LP_IN_SHIFT_W<'_>

Bits 18:19

pub fn tx_pdm_hp_in_shift(&mut self) -> TX_PDM_HP_IN_SHIFT_W<'_>

Bits 16:17

pub fn tx_pdm_prescale(&mut self) -> TX_PDM_PRESCALE_W<'_>

Bits 8:15

pub fn tx_pdm_sinc_osr2(&mut self) -> TX_PDM_SINC_OSR2_W<'_>

Bits 4:7

pub fn pdm2pcm_conv_en(&mut self) -> PDM2PCM_CONV_EN_W<'_>

Bit 3

pub fn pcm2pdm_conv_en(&mut self) -> PCM2PDM_CONV_EN_W<'_>

Bit 2

pub fn rx_pdm_en(&mut self) -> RX_PDM_EN_W<'_>

Bit 1

pub fn tx_pdm_en(&mut self) -> TX_PDM_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _PDM_FREQ_CONF>>

pub fn tx_pdm_fp(&mut self) -> TX_PDM_FP_W<'_>

Bits 10:19

pub fn tx_pdm_fs(&mut self) -> TX_PDM_FS_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _STATE>>

pub fn rx_fifo_reset_back(&mut self) -> RX_FIFO_RESET_BACK_W<'_>

Bit 2

pub fn tx_fifo_reset_back(&mut self) -> TX_FIFO_RESET_BACK_W<'_>

Bit 1

pub fn tx_idle(&mut self) -> TX_IDLE_W<'_>

Bit 0

impl W<u32, Reg<u32, _DATE>>

pub fn i2sdate(&mut self) -> I2SDATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SYSCLK_CONF>>

pub fn quick_clk_chng(&mut self) -> QUICK_CLK_CHNG_W<'_>

Bit 13

pub fn rst_tick_cnt(&mut self) -> RST_TICK_CNT_W<'_>

Bit 12

pub fn clk_en(&mut self) -> CLK_EN_W<'_>

Bit 11

pub fn clk_320m_en(&mut self) -> CLK_320M_EN_W<'_>

Bit 10

pub fn pre_div_cnt(&mut self) -> PRE_DIV_CNT_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _XTAL_TICK_CONF>>

pub fn xtal_tick_num(&mut self) -> XTAL_TICK_NUM_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _PLL_TICK_CONF>>

pub fn pll_tick_num(&mut self) -> PLL_TICK_NUM_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CK8M_TICK_CONF>>

pub fn ck8m_tick_num(&mut self) -> CK8M_TICK_NUM_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _APB_SARADC_CTRL>>

pub fn saradc_data_to_i2s(&mut self) -> SARADC_DATA_TO_I2S_W<'_>

Bit 26

pub fn saradc_data_sar_sel(&mut self) -> SARADC_DATA_SAR_SEL_W<'_>

Bit 25

pub fn saradc_sar2_patt_p_clear(&mut self) -> SARADC_SAR2_PATT_P_CLEAR_W<'_>

Bit 24

pub fn saradc_sar1_patt_p_clear(&mut self) -> SARADC_SAR1_PATT_P_CLEAR_W<'_>

Bit 23

pub fn saradc_sar2_patt_len(&mut self) -> SARADC_SAR2_PATT_LEN_W<'_>

Bits 19:22

pub fn saradc_sar1_patt_len(&mut self) -> SARADC_SAR1_PATT_LEN_W<'_>

Bits 15:18

pub fn saradc_sar_clk_div(&mut self) -> SARADC_SAR_CLK_DIV_W<'_>

Bits 7:14

pub fn saradc_sar_clk_gated(&mut self) -> SARADC_SAR_CLK_GATED_W<'_>

Bit 6

pub fn saradc_sar_sel(&mut self) -> SARADC_SAR_SEL_W<'_>

Bit 5

pub fn saradc_work_mode(&mut self) -> SARADC_WORK_MODE_W<'_>

Bits 3:4

pub fn saradc_sar2_mux(&mut self) -> SARADC_SAR2_MUX_W<'_>

Bit 2

pub fn saradc_start(&mut self) -> SARADC_START_W<'_>

Bit 1

pub fn saradc_start_force(&mut self) -> SARADC_START_FORCE_W<'_>

Bit 0

impl W<u32, Reg<u32, _APB_SARADC_CTRL2>>

pub fn saradc_sar2_inv(&mut self) -> SARADC_SAR2_INV_W<'_>

Bit 10

pub fn saradc_sar1_inv(&mut self) -> SARADC_SAR1_INV_W<'_>

Bit 9

pub fn saradc_max_meas_num(&mut self) -> SARADC_MAX_MEAS_NUM_W<'_>

Bits 1:8

pub fn saradc_meas_num_limit(&mut self) -> SARADC_MEAS_NUM_LIMIT_W<'_>

Bit 0

impl W<u32, Reg<u32, _APB_SARADC_FSM>>

pub fn saradc_sample_cycle(&mut self) -> SARADC_SAMPLE_CYCLE_W<'_>

Bits 24:31

pub fn saradc_start_wait(&mut self) -> SARADC_START_WAIT_W<'_>

Bits 16:23

pub fn saradc_standby_wait(&mut self) -> SARADC_STANDBY_WAIT_W<'_>

Bits 8:15

pub fn saradc_rstb_wait(&mut self) -> SARADC_RSTB_WAIT_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _APB_SARADC_SAR1_PATT_TAB1>>

pub fn saradc_sar1_patt_tab1(&mut self) -> SARADC_SAR1_PATT_TAB1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APB_SARADC_SAR1_PATT_TAB2>>

pub fn saradc_sar1_patt_tab2(&mut self) -> SARADC_SAR1_PATT_TAB2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APB_SARADC_SAR1_PATT_TAB3>>

pub fn saradc_sar1_patt_tab3(&mut self) -> SARADC_SAR1_PATT_TAB3_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APB_SARADC_SAR1_PATT_TAB4>>

pub fn saradc_sar1_patt_tab4(&mut self) -> SARADC_SAR1_PATT_TAB4_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APB_SARADC_SAR2_PATT_TAB1>>

pub fn saradc_sar2_patt_tab1(&mut self) -> SARADC_SAR2_PATT_TAB1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APB_SARADC_SAR2_PATT_TAB2>>

pub fn saradc_sar2_patt_tab2(&mut self) -> SARADC_SAR2_PATT_TAB2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APB_SARADC_SAR2_PATT_TAB3>>

pub fn saradc_sar2_patt_tab3(&mut self) -> SARADC_SAR2_PATT_TAB3_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APB_SARADC_SAR2_PATT_TAB4>>

pub fn saradc_sar2_patt_tab4(&mut self) -> SARADC_SAR2_PATT_TAB4_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APLL_TICK_CONF>>

pub fn apll_tick_num(&mut self) -> APLL_TICK_NUM_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _DATE>>

pub fn date(&mut self) -> DATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SYSCLK_CONF>>

pub fn quick_clk_chng(&mut self) -> QUICK_CLK_CHNG_W<'_>

Bit 13

pub fn rst_tick_cnt(&mut self) -> RST_TICK_CNT_W<'_>

Bit 12

pub fn clk_en(&mut self) -> CLK_EN_W<'_>

Bit 11

pub fn clk_320m_en(&mut self) -> CLK_320M_EN_W<'_>

Bit 10

pub fn pre_div_cnt(&mut self) -> PRE_DIV_CNT_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _XTAL_TICK_CONF>>

pub fn xtal_tick_num(&mut self) -> XTAL_TICK_NUM_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _PLL_TICK_CONF>>

pub fn pll_tick_num(&mut self) -> PLL_TICK_NUM_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CK8M_TICK_CONF>>

pub fn ck8m_tick_num(&mut self) -> CK8M_TICK_NUM_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SARADC_CTRL>>

pub fn saradc_data_to_i2s(&mut self) -> SARADC_DATA_TO_I2S_W<'_>

Bit 26

pub fn saradc_data_sar_sel(&mut self) -> SARADC_DATA_SAR_SEL_W<'_>

Bit 25

pub fn saradc_sar2_patt_p_clear(&mut self) -> SARADC_SAR2_PATT_P_CLEAR_W<'_>

Bit 24

pub fn saradc_sar1_patt_p_clear(&mut self) -> SARADC_SAR1_PATT_P_CLEAR_W<'_>

Bit 23

pub fn saradc_sar2_patt_len(&mut self) -> SARADC_SAR2_PATT_LEN_W<'_>

Bits 19:22

pub fn saradc_sar1_patt_len(&mut self) -> SARADC_SAR1_PATT_LEN_W<'_>

Bits 15:18

pub fn saradc_sar_clk_div(&mut self) -> SARADC_SAR_CLK_DIV_W<'_>

Bits 7:14

pub fn saradc_sar_clk_gated(&mut self) -> SARADC_SAR_CLK_GATED_W<'_>

Bit 6

pub fn saradc_sar_sel(&mut self) -> SARADC_SAR_SEL_W<'_>

Bit 5

pub fn saradc_work_mode(&mut self) -> SARADC_WORK_MODE_W<'_>

Bits 3:4

pub fn saradc_sar2_mux(&mut self) -> SARADC_SAR2_MUX_W<'_>

Bit 2

pub fn saradc_start(&mut self) -> SARADC_START_W<'_>

Bit 1

pub fn saradc_start_force(&mut self) -> SARADC_START_FORCE_W<'_>

Bit 0

impl W<u32, Reg<u32, _SARADC_CTRL2>>

pub fn saradc_sar2_inv(&mut self) -> SARADC_SAR2_INV_W<'_>

Bit 10

pub fn saradc_sar1_inv(&mut self) -> SARADC_SAR1_INV_W<'_>

Bit 9

pub fn saradc_max_meas_num(&mut self) -> SARADC_MAX_MEAS_NUM_W<'_>

Bits 1:8

pub fn saradc_meas_num_limit(&mut self) -> SARADC_MEAS_NUM_LIMIT_W<'_>

Bit 0

impl W<u32, Reg<u32, _SARADC_FSM>>

pub fn saradc_sample_cycle(&mut self) -> SARADC_SAMPLE_CYCLE_W<'_>

Bits 24:31

pub fn saradc_start_wait(&mut self) -> SARADC_START_WAIT_W<'_>

Bits 16:23

pub fn saradc_standby_wait(&mut self) -> SARADC_STANDBY_WAIT_W<'_>

Bits 8:15

pub fn saradc_rstb_wait(&mut self) -> SARADC_RSTB_WAIT_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _SARADC_SAR1_PATT_TAB1>>

pub fn saradc_sar1_patt_tab1(&mut self) -> SARADC_SAR1_PATT_TAB1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SARADC_SAR1_PATT_TAB2>>

pub fn saradc_sar1_patt_tab2(&mut self) -> SARADC_SAR1_PATT_TAB2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SARADC_SAR1_PATT_TAB3>>

pub fn saradc_sar1_patt_tab3(&mut self) -> SARADC_SAR1_PATT_TAB3_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SARADC_SAR1_PATT_TAB4>>

pub fn saradc_sar1_patt_tab4(&mut self) -> SARADC_SAR1_PATT_TAB4_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SARADC_SAR2_PATT_TAB1>>

pub fn saradc_sar2_patt_tab1(&mut self) -> SARADC_SAR2_PATT_TAB1_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SARADC_SAR2_PATT_TAB2>>

pub fn saradc_sar2_patt_tab2(&mut self) -> SARADC_SAR2_PATT_TAB2_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SARADC_SAR2_PATT_TAB3>>

pub fn saradc_sar2_patt_tab3(&mut self) -> SARADC_SAR2_PATT_TAB3_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SARADC_SAR2_PATT_TAB4>>

pub fn saradc_sar2_patt_tab4(&mut self) -> SARADC_SAR2_PATT_TAB4_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _APLL_TICK_CONF>>

pub fn apll_tick_num(&mut self) -> APLL_TICK_NUM_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _DATE>>

pub fn date(&mut self) -> DATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _SCL_LOW_PERIOD>>

pub fn scl_low_period(&mut self) -> SCL_LOW_PERIOD_W<'_>

Bits 0:18

impl W<u32, Reg<u32, _CTRL>>

pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<'_>

Bit 7

pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<'_>

Bit 6

pub fn trans_start(&mut self) -> TRANS_START_W<'_>

Bit 5

pub fn ms_mode(&mut self) -> MS_MODE_W<'_>

Bit 4

pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<'_>

Bit 1

pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<'_>

Bit 0

impl W<u32, Reg<u32, _DEBUG_STATUS>>

pub fn scl_state(&mut self) -> SCL_STATE_W<'_>

Bits 28:30

pub fn main_state(&mut self) -> MAIN_STATE_W<'_>

Bits 25:27

pub fn byte_trans(&mut self) -> BYTE_TRANS_W<'_>

Bit 6

pub fn slave_addr_match(&mut self) -> SLAVE_ADDR_MATCH_W<'_>

Bit 5

pub fn bus_busy(&mut self) -> BUS_BUSY_W<'_>

Bit 4

pub fn arb_lost(&mut self) -> ARB_LOST_W<'_>

Bit 3

pub fn timed_out(&mut self) -> TIMED_OUT_W<'_>

Bit 2

pub fn slave_rw(&mut self) -> SLAVE_RW_W<'_>

Bit 1

pub fn ack_val(&mut self) -> ACK_VAL_W<'_>

Bit 0

impl W<u32, Reg<u32, _TIMEOUT>>

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _SLAVE_ADDR>>

pub fn slave_addr_10bit(&mut self) -> SLAVE_ADDR_10BIT_W<'_>

Bit 31

pub fn slave_addr(&mut self) -> SLAVE_ADDR_W<'_>

Bits 0:14

impl W<u32, Reg<u32, _INT_RAW>>

pub fn time_out_int_raw(&mut self) -> TIME_OUT_INT_RAW_W<'_>

Bit 7

pub fn trans_complete_int_raw(&mut self) -> TRANS_COMPLETE_INT_RAW_W<'_>

Bit 6

pub fn master_trans_complete_int_raw(
    &mut self
) -> MASTER_TRANS_COMPLETE_INT_RAW_W<'_>

Bit 5

pub fn arbitration_lost_int_raw(&mut self) -> ARBITRATION_LOST_INT_RAW_W<'_>

Bit 4

pub fn slave_trans_complete_int_raw(
    &mut self
) -> SLAVE_TRANS_COMPLETE_INT_RAW_W<'_>

Bit 3

impl W<u32, Reg<u32, _INT_CLR>>

pub fn time_out_int_clr(&mut self) -> TIME_OUT_INT_CLR_W<'_>

Bit 8

pub fn trans_complete_int_clr(&mut self) -> TRANS_COMPLETE_INT_CLR_W<'_>

Bit 7

pub fn master_trans_complete_int_clr(
    &mut self
) -> MASTER_TRANS_COMPLETE_INT_CLR_W<'_>

Bit 6

pub fn arbitration_lost_int_clr(&mut self) -> ARBITRATION_LOST_INT_CLR_W<'_>

Bit 5

pub fn slave_trans_complete_int_clr(
    &mut self
) -> SLAVE_TRANS_COMPLETE_INT_CLR_W<'_>

Bit 4

impl W<u32, Reg<u32, _SDA_DUTY>>

pub fn sda_duty(&mut self) -> SDA_DUTY_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _SCL_HIGH_PERIOD>>

pub fn scl_high_period(&mut self) -> SCL_HIGH_PERIOD_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _SCL_START_PERIOD>>

pub fn scl_start_period(&mut self) -> SCL_START_PERIOD_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _SCL_STOP_PERIOD>>

pub fn scl_stop_period(&mut self) -> SCL_STOP_PERIOD_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _INT_RAW>>

pub fn at_cmd_char_det_int_raw(&mut self) -> AT_CMD_CHAR_DET_INT_RAW_W<'_>

Bit 18

pub fn rs485_clash_int_raw(&mut self) -> RS485_CLASH_INT_RAW_W<'_>

Bit 17

pub fn rs485_frm_err_int_raw(&mut self) -> RS485_FRM_ERR_INT_RAW_W<'_>

Bit 16

pub fn rs485_parity_err_int_raw(&mut self) -> RS485_PARITY_ERR_INT_RAW_W<'_>

Bit 15

pub fn tx_done_int_raw(&mut self) -> TX_DONE_INT_RAW_W<'_>

Bit 14

pub fn tx_brk_idle_done_int_raw(&mut self) -> TX_BRK_IDLE_DONE_INT_RAW_W<'_>

Bit 13

pub fn tx_brk_done_int_raw(&mut self) -> TX_BRK_DONE_INT_RAW_W<'_>

Bit 12

pub fn glitch_det_int_raw(&mut self) -> GLITCH_DET_INT_RAW_W<'_>

Bit 11

pub fn sw_xoff_int_raw(&mut self) -> SW_XOFF_INT_RAW_W<'_>

Bit 10

pub fn sw_xon_int_raw(&mut self) -> SW_XON_INT_RAW_W<'_>

Bit 9

pub fn rxfifo_tout_int_raw(&mut self) -> RXFIFO_TOUT_INT_RAW_W<'_>

Bit 8

pub fn brk_det_int_raw(&mut self) -> BRK_DET_INT_RAW_W<'_>

Bit 7

pub fn cts_chg_int_raw(&mut self) -> CTS_CHG_INT_RAW_W<'_>

Bit 6

pub fn dsr_chg_int_raw(&mut self) -> DSR_CHG_INT_RAW_W<'_>

Bit 5

pub fn rxfifo_ovf_int_raw(&mut self) -> RXFIFO_OVF_INT_RAW_W<'_>

Bit 4

pub fn frm_err_int_raw(&mut self) -> FRM_ERR_INT_RAW_W<'_>

Bit 3

pub fn parity_err_int_raw(&mut self) -> PARITY_ERR_INT_RAW_W<'_>

Bit 2

pub fn txfifo_empty_int_raw(&mut self) -> TXFIFO_EMPTY_INT_RAW_W<'_>

Bit 1

pub fn rxfifo_full_int_raw(&mut self) -> RXFIFO_FULL_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ST>>

pub fn at_cmd_char_det_int_st(&mut self) -> AT_CMD_CHAR_DET_INT_ST_W<'_>

Bit 18

pub fn rs485_clash_int_st(&mut self) -> RS485_CLASH_INT_ST_W<'_>

Bit 17

pub fn rs485_frm_err_int_st(&mut self) -> RS485_FRM_ERR_INT_ST_W<'_>

Bit 16

pub fn rs485_parity_err_int_st(&mut self) -> RS485_PARITY_ERR_INT_ST_W<'_>

Bit 15

pub fn tx_done_int_st(&mut self) -> TX_DONE_INT_ST_W<'_>

Bit 14

pub fn tx_brk_idle_done_int_st(&mut self) -> TX_BRK_IDLE_DONE_INT_ST_W<'_>

Bit 13

pub fn tx_brk_done_int_st(&mut self) -> TX_BRK_DONE_INT_ST_W<'_>

Bit 12

pub fn glitch_det_int_st(&mut self) -> GLITCH_DET_INT_ST_W<'_>

Bit 11

pub fn sw_xoff_int_st(&mut self) -> SW_XOFF_INT_ST_W<'_>

Bit 10

pub fn sw_xon_int_st(&mut self) -> SW_XON_INT_ST_W<'_>

Bit 9

pub fn rxfifo_tout_int_st(&mut self) -> RXFIFO_TOUT_INT_ST_W<'_>

Bit 8

pub fn brk_det_int_st(&mut self) -> BRK_DET_INT_ST_W<'_>

Bit 7

pub fn cts_chg_int_st(&mut self) -> CTS_CHG_INT_ST_W<'_>

Bit 6

pub fn dsr_chg_int_st(&mut self) -> DSR_CHG_INT_ST_W<'_>

Bit 5

pub fn rxfifo_ovf_int_st(&mut self) -> RXFIFO_OVF_INT_ST_W<'_>

Bit 4

pub fn frm_err_int_st(&mut self) -> FRM_ERR_INT_ST_W<'_>

Bit 3

pub fn parity_err_int_st(&mut self) -> PARITY_ERR_INT_ST_W<'_>

Bit 2

pub fn txfifo_empty_int_st(&mut self) -> TXFIFO_EMPTY_INT_ST_W<'_>

Bit 1

pub fn rxfifo_full_int_st(&mut self) -> RXFIFO_FULL_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ENA>>

pub fn at_cmd_char_det_int_ena(&mut self) -> AT_CMD_CHAR_DET_INT_ENA_W<'_>

Bit 18

pub fn rs485_clash_int_ena(&mut self) -> RS485_CLASH_INT_ENA_W<'_>

Bit 17

pub fn rs485_frm_err_int_ena(&mut self) -> RS485_FRM_ERR_INT_ENA_W<'_>

Bit 16

pub fn rs485_parity_err_int_ena(&mut self) -> RS485_PARITY_ERR_INT_ENA_W<'_>

Bit 15

pub fn tx_done_int_ena(&mut self) -> TX_DONE_INT_ENA_W<'_>

Bit 14

pub fn tx_brk_idle_done_int_ena(&mut self) -> TX_BRK_IDLE_DONE_INT_ENA_W<'_>

Bit 13

pub fn tx_brk_done_int_ena(&mut self) -> TX_BRK_DONE_INT_ENA_W<'_>

Bit 12

pub fn glitch_det_int_ena(&mut self) -> GLITCH_DET_INT_ENA_W<'_>

Bit 11

pub fn sw_xoff_int_ena(&mut self) -> SW_XOFF_INT_ENA_W<'_>

Bit 10

pub fn sw_xon_int_ena(&mut self) -> SW_XON_INT_ENA_W<'_>

Bit 9

pub fn rxfifo_tout_int_ena(&mut self) -> RXFIFO_TOUT_INT_ENA_W<'_>

Bit 8

pub fn brk_det_int_ena(&mut self) -> BRK_DET_INT_ENA_W<'_>

Bit 7

pub fn cts_chg_int_ena(&mut self) -> CTS_CHG_INT_ENA_W<'_>

Bit 6

pub fn dsr_chg_int_ena(&mut self) -> DSR_CHG_INT_ENA_W<'_>

Bit 5

pub fn rxfifo_ovf_int_ena(&mut self) -> RXFIFO_OVF_INT_ENA_W<'_>

Bit 4

pub fn frm_err_int_ena(&mut self) -> FRM_ERR_INT_ENA_W<'_>

Bit 3

pub fn parity_err_int_ena(&mut self) -> PARITY_ERR_INT_ENA_W<'_>

Bit 2

pub fn txfifo_empty_int_ena(&mut self) -> TXFIFO_EMPTY_INT_ENA_W<'_>

Bit 1

pub fn rxfifo_full_int_ena(&mut self) -> RXFIFO_FULL_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_CLR>>

pub fn at_cmd_char_det_int_clr(&mut self) -> AT_CMD_CHAR_DET_INT_CLR_W<'_>

Bit 18

pub fn rs485_clash_int_clr(&mut self) -> RS485_CLASH_INT_CLR_W<'_>

Bit 17

pub fn rs485_frm_err_int_clr(&mut self) -> RS485_FRM_ERR_INT_CLR_W<'_>

Bit 16

pub fn rs485_parity_err_int_clr(&mut self) -> RS485_PARITY_ERR_INT_CLR_W<'_>

Bit 15

pub fn tx_done_int_clr(&mut self) -> TX_DONE_INT_CLR_W<'_>

Bit 14

pub fn tx_brk_idle_done_int_clr(&mut self) -> TX_BRK_IDLE_DONE_INT_CLR_W<'_>

Bit 13

pub fn tx_brk_done_int_clr(&mut self) -> TX_BRK_DONE_INT_CLR_W<'_>

Bit 12

pub fn glitch_det_int_clr(&mut self) -> GLITCH_DET_INT_CLR_W<'_>

Bit 11

pub fn sw_xoff_int_clr(&mut self) -> SW_XOFF_INT_CLR_W<'_>

Bit 10

pub fn sw_xon_int_clr(&mut self) -> SW_XON_INT_CLR_W<'_>

Bit 9

pub fn rxfifo_tout_int_clr(&mut self) -> RXFIFO_TOUT_INT_CLR_W<'_>

Bit 8

pub fn brk_det_int_clr(&mut self) -> BRK_DET_INT_CLR_W<'_>

Bit 7

pub fn cts_chg_int_clr(&mut self) -> CTS_CHG_INT_CLR_W<'_>

Bit 6

pub fn dsr_chg_int_clr(&mut self) -> DSR_CHG_INT_CLR_W<'_>

Bit 5

pub fn rxfifo_ovf_int_clr(&mut self) -> RXFIFO_OVF_INT_CLR_W<'_>

Bit 4

pub fn frm_err_int_clr(&mut self) -> FRM_ERR_INT_CLR_W<'_>

Bit 3

pub fn parity_err_int_clr(&mut self) -> PARITY_ERR_INT_CLR_W<'_>

Bit 2

pub fn txfifo_empty_int_clr(&mut self) -> TXFIFO_EMPTY_INT_CLR_W<'_>

Bit 1

pub fn rxfifo_full_int_clr(&mut self) -> RXFIFO_FULL_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, _CLKDIV>>

pub fn clkdiv_frag(&mut self) -> CLKDIV_FRAG_W<'_>

Bits 20:23

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _AUTOBAUD>>

pub fn glitch_filt(&mut self) -> GLITCH_FILT_W<'_>

Bits 8:15

pub fn autobaud_en(&mut self) -> AUTOBAUD_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _STATUS>>

pub fn txd(&mut self) -> TXD_W<'_>

Bit 31

pub fn rtsn(&mut self) -> RTSN_W<'_>

Bit 30

pub fn dtrn(&mut self) -> DTRN_W<'_>

Bit 29

pub fn st_utx_out(&mut self) -> ST_UTX_OUT_W<'_>

Bits 24:27

pub fn txfifo_cnt(&mut self) -> TXFIFO_CNT_W<'_>

Bits 16:23

pub fn rxd(&mut self) -> RXD_W<'_>

Bit 15

pub fn ctsn(&mut self) -> CTSN_W<'_>

Bit 14

pub fn dsrn(&mut self) -> DSRN_W<'_>

Bit 13

pub fn st_urx_out(&mut self) -> ST_URX_OUT_W<'_>

Bits 8:11

pub fn rxfifo_cnt(&mut self) -> RXFIFO_CNT_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _CONF0>>

pub fn tick_ref_always_on(&mut self) -> TICK_REF_ALWAYS_ON_W<'_>

Bit 27

pub fn err_wr_mask(&mut self) -> ERR_WR_MASK_W<'_>

Bit 26

pub fn clk_en(&mut self) -> CLK_EN_W<'_>

Bit 25

pub fn dtr_inv(&mut self) -> DTR_INV_W<'_>

Bit 24

pub fn rts_inv(&mut self) -> RTS_INV_W<'_>

Bit 23

pub fn txd_inv(&mut self) -> TXD_INV_W<'_>

Bit 22

pub fn dsr_inv(&mut self) -> DSR_INV_W<'_>

Bit 21

pub fn cts_inv(&mut self) -> CTS_INV_W<'_>

Bit 20

pub fn rxd_inv(&mut self) -> RXD_INV_W<'_>

Bit 19

pub fn txfifo_rst(&mut self) -> TXFIFO_RST_W<'_>

Bit 18

pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W<'_>

Bit 17

pub fn irda_en(&mut self) -> IRDA_EN_W<'_>

Bit 16

pub fn tx_flow_en(&mut self) -> TX_FLOW_EN_W<'_>

Bit 15

pub fn loopback(&mut self) -> LOOPBACK_W<'_>

Bit 14

pub fn irda_rx_inv(&mut self) -> IRDA_RX_INV_W<'_>

Bit 13

pub fn irda_tx_inv(&mut self) -> IRDA_TX_INV_W<'_>

Bit 12

pub fn irda_wctl(&mut self) -> IRDA_WCTL_W<'_>

Bit 11

pub fn irda_tx_en(&mut self) -> IRDA_TX_EN_W<'_>

Bit 10

pub fn irda_dplx(&mut self) -> IRDA_DPLX_W<'_>

Bit 9

pub fn txd_brk(&mut self) -> TXD_BRK_W<'_>

Bit 8

pub fn sw_dtr(&mut self) -> SW_DTR_W<'_>

Bit 7

pub fn sw_rts(&mut self) -> SW_RTS_W<'_>

Bit 6

pub fn stop_bit_num(&mut self) -> STOP_BIT_NUM_W<'_>

Bits 4:5

pub fn bit_num(&mut self) -> BIT_NUM_W<'_>

Bits 2:3

pub fn parity_en(&mut self) -> PARITY_EN_W<'_>

Bit 1

pub fn parity(&mut self) -> PARITY_W<'_>

Bit 0

impl W<u32, Reg<u32, _CONF1>>

pub fn rx_tout_en(&mut self) -> RX_TOUT_EN_W<'_>

Bit 31

pub fn rx_tout_thrhd(&mut self) -> RX_TOUT_THRHD_W<'_>

Bits 24:30

pub fn rx_flow_en(&mut self) -> RX_FLOW_EN_W<'_>

Bit 23

pub fn rx_flow_thrhd(&mut self) -> RX_FLOW_THRHD_W<'_>

Bits 16:22

pub fn txfifo_empty_thrhd(&mut self) -> TXFIFO_EMPTY_THRHD_W<'_>

Bits 8:14

pub fn rxfifo_full_thrhd(&mut self) -> RXFIFO_FULL_THRHD_W<'_>

Bits 0:6

impl W<u32, Reg<u32, _LOWPULSE>>

pub fn lowpulse_min_cnt(&mut self) -> LOWPULSE_MIN_CNT_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HIGHPULSE>>

pub fn highpulse_min_cnt(&mut self) -> HIGHPULSE_MIN_CNT_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _RXD_CNT>>

pub fn rxd_edge_cnt(&mut self) -> RXD_EDGE_CNT_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _FLOW_CONF>>

pub fn send_xoff(&mut self) -> SEND_XOFF_W<'_>

Bit 5

pub fn send_xon(&mut self) -> SEND_XON_W<'_>

Bit 4

pub fn force_xoff(&mut self) -> FORCE_XOFF_W<'_>

Bit 3

pub fn force_xon(&mut self) -> FORCE_XON_W<'_>

Bit 2

pub fn xonoff_del(&mut self) -> XONOFF_DEL_W<'_>

Bit 1

pub fn sw_flow_con_en(&mut self) -> SW_FLOW_CON_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _SLEEP_CONF>>

pub fn active_threshold(&mut self) -> ACTIVE_THRESHOLD_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _SWFC_CONF>>

pub fn xoff_char(&mut self) -> XOFF_CHAR_W<'_>

Bits 24:31

pub fn xon_char(&mut self) -> XON_CHAR_W<'_>

Bits 16:23

pub fn xoff_threshold(&mut self) -> XOFF_THRESHOLD_W<'_>

Bits 8:15

pub fn xon_threshold(&mut self) -> XON_THRESHOLD_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _IDLE_CONF>>

pub fn tx_brk_num(&mut self) -> TX_BRK_NUM_W<'_>

Bits 20:27

pub fn tx_idle_num(&mut self) -> TX_IDLE_NUM_W<'_>

Bits 10:19

pub fn rx_idle_thrhd(&mut self) -> RX_IDLE_THRHD_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _RS485_CONF>>

pub fn rs485_tx_dly_num(&mut self) -> RS485_TX_DLY_NUM_W<'_>

Bits 6:9

pub fn rs485_rx_dly_num(&mut self) -> RS485_RX_DLY_NUM_W<'_>

Bit 5

pub fn rs485rxby_tx_en(&mut self) -> RS485RXBY_TX_EN_W<'_>

Bit 4

pub fn rs485tx_rx_en(&mut self) -> RS485TX_RX_EN_W<'_>

Bit 3

pub fn dl1_en(&mut self) -> DL1_EN_W<'_>

Bit 2

pub fn dl0_en(&mut self) -> DL0_EN_W<'_>

Bit 1

pub fn rs485_en(&mut self) -> RS485_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _AT_CMD_PRECNT>>

pub fn pre_idle_num(&mut self) -> PRE_IDLE_NUM_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _AT_CMD_POSTCNT>>

pub fn post_idle_num(&mut self) -> POST_IDLE_NUM_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _AT_CMD_GAPTOUT>>

pub fn rx_gap_tout(&mut self) -> RX_GAP_TOUT_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _AT_CMD_CHAR>>

pub fn char_num(&mut self) -> CHAR_NUM_W<'_>

Bits 8:15

pub fn at_cmd_char(&mut self) -> AT_CMD_CHAR_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _MEM_CONF>>

pub fn tx_mem_empty_thrhd(&mut self) -> TX_MEM_EMPTY_THRHD_W<'_>

Bits 28:30

pub fn rx_mem_full_thrhd(&mut self) -> RX_MEM_FULL_THRHD_W<'_>

Bits 25:27

pub fn xoff_threshold_h2(&mut self) -> XOFF_THRESHOLD_H2_W<'_>

Bits 23:24

pub fn xon_threshold_h2(&mut self) -> XON_THRESHOLD_H2_W<'_>

Bits 21:22

pub fn rx_tout_thrhd_h3(&mut self) -> RX_TOUT_THRHD_H3_W<'_>

Bits 18:20

pub fn rx_flow_thrhd_h3(&mut self) -> RX_FLOW_THRHD_H3_W<'_>

Bits 15:17

pub fn tx_size(&mut self) -> TX_SIZE_W<'_>

Bits 7:10

pub fn rx_size(&mut self) -> RX_SIZE_W<'_>

Bits 3:6

pub fn mem_pd(&mut self) -> MEM_PD_W<'_>

Bit 0

impl W<u32, Reg<u32, _MEM_TX_STATUS>>

pub fn mem_tx_status(&mut self) -> MEM_TX_STATUS_W<'_>

Bits 0:23

impl W<u32, Reg<u32, _MEM_RX_STATUS>>

pub fn mem_rx_status(&mut self) -> MEM_RX_STATUS_W<'_>

Bits 0:23

pub fn mem_rx_rd_addr(&mut self) -> MEM_RX_RD_ADDR_W<'_>

Bits 2:12

pub fn mem_rx_wr_addr(&mut self) -> MEM_RX_WR_ADDR_W<'_>

Bits 13:23

impl W<u32, Reg<u32, _MEM_CNT_STATUS>>

pub fn tx_mem_cnt(&mut self) -> TX_MEM_CNT_W<'_>

Bits 3:5

pub fn rx_mem_cnt(&mut self) -> RX_MEM_CNT_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _POSPULSE>>

pub fn posedge_min_cnt(&mut self) -> POSEDGE_MIN_CNT_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _NEGPULSE>>

pub fn negedge_min_cnt(&mut self) -> NEGEDGE_MIN_CNT_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _DATE>>

pub fn date(&mut self) -> DATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _ID>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:31

impl W<u8, Reg<u8, _TX_FIFO>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:7 - TX FIFO Data

impl W<u32, Reg<u32, _HSCH0_CONF0>>

pub fn clk_en(&mut self) -> CLK_EN_W<'_>

Bit 31

pub fn idle_lv_hsch0(&mut self) -> IDLE_LV_HSCH0_W<'_>

Bit 3

pub fn sig_out_en_hsch0(&mut self) -> SIG_OUT_EN_HSCH0_W<'_>

Bit 2

pub fn timer_sel_hsch0(&mut self) -> TIMER_SEL_HSCH0_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _HSCH0_HPOINT>>

pub fn hpoint_hsch0(&mut self) -> HPOINT_HSCH0_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HSCH0_DUTY>>

pub fn duty_hsch0(&mut self) -> DUTY_HSCH0_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSCH0_CONF1>>

pub fn duty_start_hsch0(&mut self) -> DUTY_START_HSCH0_W<'_>

Bit 31

pub fn duty_inc_hsch0(&mut self) -> DUTY_INC_HSCH0_W<'_>

Bit 30

pub fn duty_num_hsch0(&mut self) -> DUTY_NUM_HSCH0_W<'_>

Bits 20:29

pub fn duty_cycle_hsch0(&mut self) -> DUTY_CYCLE_HSCH0_W<'_>

Bits 10:19

pub fn duty_scale_hsch0(&mut self) -> DUTY_SCALE_HSCH0_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _HSCH0_DUTY_R>>

pub fn duty_hsch0(&mut self) -> DUTY_HSCH0_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSCH1_CONF0>>

pub fn idle_lv_hsch1(&mut self) -> IDLE_LV_HSCH1_W<'_>

Bit 3

pub fn sig_out_en_hsch1(&mut self) -> SIG_OUT_EN_HSCH1_W<'_>

Bit 2

pub fn timer_sel_hsch1(&mut self) -> TIMER_SEL_HSCH1_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _HSCH1_HPOINT>>

pub fn hpoint_hsch1(&mut self) -> HPOINT_HSCH1_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HSCH1_DUTY>>

pub fn duty_hsch1(&mut self) -> DUTY_HSCH1_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSCH1_CONF1>>

pub fn duty_start_hsch1(&mut self) -> DUTY_START_HSCH1_W<'_>

Bit 31

pub fn duty_inc_hsch1(&mut self) -> DUTY_INC_HSCH1_W<'_>

Bit 30

pub fn duty_num_hsch1(&mut self) -> DUTY_NUM_HSCH1_W<'_>

Bits 20:29

pub fn duty_cycle_hsch1(&mut self) -> DUTY_CYCLE_HSCH1_W<'_>

Bits 10:19

pub fn duty_scale_hsch1(&mut self) -> DUTY_SCALE_HSCH1_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _HSCH1_DUTY_R>>

pub fn duty_hsch1(&mut self) -> DUTY_HSCH1_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSCH2_CONF0>>

pub fn idle_lv_hsch2(&mut self) -> IDLE_LV_HSCH2_W<'_>

Bit 3

pub fn sig_out_en_hsch2(&mut self) -> SIG_OUT_EN_HSCH2_W<'_>

Bit 2

pub fn timer_sel_hsch2(&mut self) -> TIMER_SEL_HSCH2_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _HSCH2_HPOINT>>

pub fn hpoint_hsch2(&mut self) -> HPOINT_HSCH2_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HSCH2_DUTY>>

pub fn duty_hsch2(&mut self) -> DUTY_HSCH2_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSCH2_CONF1>>

pub fn duty_start_hsch2(&mut self) -> DUTY_START_HSCH2_W<'_>

Bit 31

pub fn duty_inc_hsch2(&mut self) -> DUTY_INC_HSCH2_W<'_>

Bit 30

pub fn duty_num_hsch2(&mut self) -> DUTY_NUM_HSCH2_W<'_>

Bits 20:29

pub fn duty_cycle_hsch2(&mut self) -> DUTY_CYCLE_HSCH2_W<'_>

Bits 10:19

pub fn duty_scale_hsch2(&mut self) -> DUTY_SCALE_HSCH2_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _HSCH2_DUTY_R>>

pub fn duty_hsch2(&mut self) -> DUTY_HSCH2_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSCH3_CONF0>>

pub fn idle_lv_hsch3(&mut self) -> IDLE_LV_HSCH3_W<'_>

Bit 3

pub fn sig_out_en_hsch3(&mut self) -> SIG_OUT_EN_HSCH3_W<'_>

Bit 2

pub fn timer_sel_hsch3(&mut self) -> TIMER_SEL_HSCH3_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _HSCH3_HPOINT>>

pub fn hpoint_hsch3(&mut self) -> HPOINT_HSCH3_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HSCH3_DUTY>>

pub fn duty_hsch3(&mut self) -> DUTY_HSCH3_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSCH3_CONF1>>

pub fn duty_start_hsch3(&mut self) -> DUTY_START_HSCH3_W<'_>

Bit 31

pub fn duty_inc_hsch3(&mut self) -> DUTY_INC_HSCH3_W<'_>

Bit 30

pub fn duty_num_hsch3(&mut self) -> DUTY_NUM_HSCH3_W<'_>

Bits 20:29

pub fn duty_cycle_hsch3(&mut self) -> DUTY_CYCLE_HSCH3_W<'_>

Bits 10:19

pub fn duty_scale_hsch3(&mut self) -> DUTY_SCALE_HSCH3_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _HSCH3_DUTY_R>>

pub fn duty_hsch3(&mut self) -> DUTY_HSCH3_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSCH4_CONF0>>

pub fn idle_lv_hsch4(&mut self) -> IDLE_LV_HSCH4_W<'_>

Bit 3

pub fn sig_out_en_hsch4(&mut self) -> SIG_OUT_EN_HSCH4_W<'_>

Bit 2

pub fn timer_sel_hsch4(&mut self) -> TIMER_SEL_HSCH4_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _HSCH4_HPOINT>>

pub fn hpoint_hsch4(&mut self) -> HPOINT_HSCH4_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HSCH4_DUTY>>

pub fn duty_hsch4(&mut self) -> DUTY_HSCH4_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSCH4_CONF1>>

pub fn duty_start_hsch4(&mut self) -> DUTY_START_HSCH4_W<'_>

Bit 31

pub fn duty_inc_hsch4(&mut self) -> DUTY_INC_HSCH4_W<'_>

Bit 30

pub fn duty_num_hsch4(&mut self) -> DUTY_NUM_HSCH4_W<'_>

Bits 20:29

pub fn duty_cycle_hsch4(&mut self) -> DUTY_CYCLE_HSCH4_W<'_>

Bits 10:19

pub fn duty_scale_hsch4(&mut self) -> DUTY_SCALE_HSCH4_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _HSCH4_DUTY_R>>

pub fn duty_hsch4(&mut self) -> DUTY_HSCH4_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSCH5_CONF0>>

pub fn idle_lv_hsch5(&mut self) -> IDLE_LV_HSCH5_W<'_>

Bit 3

pub fn sig_out_en_hsch5(&mut self) -> SIG_OUT_EN_HSCH5_W<'_>

Bit 2

pub fn timer_sel_hsch5(&mut self) -> TIMER_SEL_HSCH5_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _HSCH5_HPOINT>>

pub fn hpoint_hsch5(&mut self) -> HPOINT_HSCH5_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HSCH5_DUTY>>

pub fn duty_hsch5(&mut self) -> DUTY_HSCH5_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSCH5_CONF1>>

pub fn duty_start_hsch5(&mut self) -> DUTY_START_HSCH5_W<'_>

Bit 31

pub fn duty_inc_hsch5(&mut self) -> DUTY_INC_HSCH5_W<'_>

Bit 30

pub fn duty_num_hsch5(&mut self) -> DUTY_NUM_HSCH5_W<'_>

Bits 20:29

pub fn duty_cycle_hsch5(&mut self) -> DUTY_CYCLE_HSCH5_W<'_>

Bits 10:19

pub fn duty_scale_hsch5(&mut self) -> DUTY_SCALE_HSCH5_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _HSCH5_DUTY_R>>

pub fn duty_hsch5(&mut self) -> DUTY_HSCH5_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSCH6_CONF0>>

pub fn idle_lv_hsch6(&mut self) -> IDLE_LV_HSCH6_W<'_>

Bit 3

pub fn sig_out_en_hsch6(&mut self) -> SIG_OUT_EN_HSCH6_W<'_>

Bit 2

pub fn timer_sel_hsch6(&mut self) -> TIMER_SEL_HSCH6_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _HSCH6_HPOINT>>

pub fn hpoint_hsch6(&mut self) -> HPOINT_HSCH6_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HSCH6_DUTY>>

pub fn duty_hsch6(&mut self) -> DUTY_HSCH6_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSCH6_CONF1>>

pub fn duty_start_hsch6(&mut self) -> DUTY_START_HSCH6_W<'_>

Bit 31

pub fn duty_inc_hsch6(&mut self) -> DUTY_INC_HSCH6_W<'_>

Bit 30

pub fn duty_num_hsch6(&mut self) -> DUTY_NUM_HSCH6_W<'_>

Bits 20:29

pub fn duty_cycle_hsch6(&mut self) -> DUTY_CYCLE_HSCH6_W<'_>

Bits 10:19

pub fn duty_scale_hsch6(&mut self) -> DUTY_SCALE_HSCH6_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _HSCH6_DUTY_R>>

pub fn duty_hsch6(&mut self) -> DUTY_HSCH6_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSCH7_CONF0>>

pub fn idle_lv_hsch7(&mut self) -> IDLE_LV_HSCH7_W<'_>

Bit 3

pub fn sig_out_en_hsch7(&mut self) -> SIG_OUT_EN_HSCH7_W<'_>

Bit 2

pub fn timer_sel_hsch7(&mut self) -> TIMER_SEL_HSCH7_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _HSCH7_HPOINT>>

pub fn hpoint_hsch7(&mut self) -> HPOINT_HSCH7_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HSCH7_DUTY>>

pub fn duty_hsch7(&mut self) -> DUTY_HSCH7_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSCH7_CONF1>>

pub fn duty_start_hsch7(&mut self) -> DUTY_START_HSCH7_W<'_>

Bit 31

pub fn duty_inc_hsch7(&mut self) -> DUTY_INC_HSCH7_W<'_>

Bit 30

pub fn duty_num_hsch7(&mut self) -> DUTY_NUM_HSCH7_W<'_>

Bits 20:29

pub fn duty_cycle_hsch7(&mut self) -> DUTY_CYCLE_HSCH7_W<'_>

Bits 10:19

pub fn duty_scale_hsch7(&mut self) -> DUTY_SCALE_HSCH7_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _HSCH7_DUTY_R>>

pub fn duty_hsch7(&mut self) -> DUTY_HSCH7_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH0_CONF0>>

pub fn para_up_lsch0(&mut self) -> PARA_UP_LSCH0_W<'_>

Bit 4

pub fn idle_lv_lsch0(&mut self) -> IDLE_LV_LSCH0_W<'_>

Bit 3

pub fn sig_out_en_lsch0(&mut self) -> SIG_OUT_EN_LSCH0_W<'_>

Bit 2

pub fn timer_sel_lsch0(&mut self) -> TIMER_SEL_LSCH0_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _LSCH0_HPOINT>>

pub fn hpoint_lsch0(&mut self) -> HPOINT_LSCH0_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _LSCH0_DUTY>>

pub fn duty_lsch0(&mut self) -> DUTY_LSCH0_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH0_CONF1>>

pub fn duty_start_lsch0(&mut self) -> DUTY_START_LSCH0_W<'_>

Bit 31

pub fn duty_inc_lsch0(&mut self) -> DUTY_INC_LSCH0_W<'_>

Bit 30

pub fn duty_num_lsch0(&mut self) -> DUTY_NUM_LSCH0_W<'_>

Bits 20:29

pub fn duty_cycle_lsch0(&mut self) -> DUTY_CYCLE_LSCH0_W<'_>

Bits 10:19

pub fn duty_scale_lsch0(&mut self) -> DUTY_SCALE_LSCH0_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _LSCH0_DUTY_R>>

pub fn duty_lsch0(&mut self) -> DUTY_LSCH0_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH1_CONF0>>

pub fn para_up_lsch1(&mut self) -> PARA_UP_LSCH1_W<'_>

Bit 4

pub fn idle_lv_lsch1(&mut self) -> IDLE_LV_LSCH1_W<'_>

Bit 3

pub fn sig_out_en_lsch1(&mut self) -> SIG_OUT_EN_LSCH1_W<'_>

Bit 2

pub fn timer_sel_lsch1(&mut self) -> TIMER_SEL_LSCH1_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _LSCH1_HPOINT>>

pub fn hpoint_lsch1(&mut self) -> HPOINT_LSCH1_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _LSCH1_DUTY>>

pub fn duty_lsch1(&mut self) -> DUTY_LSCH1_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH1_CONF1>>

pub fn duty_start_lsch1(&mut self) -> DUTY_START_LSCH1_W<'_>

Bit 31

pub fn duty_inc_lsch1(&mut self) -> DUTY_INC_LSCH1_W<'_>

Bit 30

pub fn duty_num_lsch1(&mut self) -> DUTY_NUM_LSCH1_W<'_>

Bits 20:29

pub fn duty_cycle_lsch1(&mut self) -> DUTY_CYCLE_LSCH1_W<'_>

Bits 10:19

pub fn duty_scale_lsch1(&mut self) -> DUTY_SCALE_LSCH1_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _LSCH1_DUTY_R>>

pub fn duty_lsch1(&mut self) -> DUTY_LSCH1_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH2_CONF0>>

pub fn para_up_lsch2(&mut self) -> PARA_UP_LSCH2_W<'_>

Bit 4

pub fn idle_lv_lsch2(&mut self) -> IDLE_LV_LSCH2_W<'_>

Bit 3

pub fn sig_out_en_lsch2(&mut self) -> SIG_OUT_EN_LSCH2_W<'_>

Bit 2

pub fn timer_sel_lsch2(&mut self) -> TIMER_SEL_LSCH2_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _LSCH2_HPOINT>>

pub fn hpoint_lsch2(&mut self) -> HPOINT_LSCH2_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _LSCH2_DUTY>>

pub fn duty_lsch2(&mut self) -> DUTY_LSCH2_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH2_CONF1>>

pub fn duty_start_lsch2(&mut self) -> DUTY_START_LSCH2_W<'_>

Bit 31

pub fn duty_inc_lsch2(&mut self) -> DUTY_INC_LSCH2_W<'_>

Bit 30

pub fn duty_num_lsch2(&mut self) -> DUTY_NUM_LSCH2_W<'_>

Bits 20:29

pub fn duty_cycle_lsch2(&mut self) -> DUTY_CYCLE_LSCH2_W<'_>

Bits 10:19

pub fn duty_scale_lsch2(&mut self) -> DUTY_SCALE_LSCH2_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _LSCH2_DUTY_R>>

pub fn duty_lsch2(&mut self) -> DUTY_LSCH2_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH3_CONF0>>

pub fn para_up_lsch3(&mut self) -> PARA_UP_LSCH3_W<'_>

Bit 4

pub fn idle_lv_lsch3(&mut self) -> IDLE_LV_LSCH3_W<'_>

Bit 3

pub fn sig_out_en_lsch3(&mut self) -> SIG_OUT_EN_LSCH3_W<'_>

Bit 2

pub fn timer_sel_lsch3(&mut self) -> TIMER_SEL_LSCH3_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _LSCH3_HPOINT>>

pub fn hpoint_lsch3(&mut self) -> HPOINT_LSCH3_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _LSCH3_DUTY>>

pub fn duty_lsch3(&mut self) -> DUTY_LSCH3_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH3_CONF1>>

pub fn duty_start_lsch3(&mut self) -> DUTY_START_LSCH3_W<'_>

Bit 31

pub fn duty_inc_lsch3(&mut self) -> DUTY_INC_LSCH3_W<'_>

Bit 30

pub fn duty_num_lsch3(&mut self) -> DUTY_NUM_LSCH3_W<'_>

Bits 20:29

pub fn duty_cycle_lsch3(&mut self) -> DUTY_CYCLE_LSCH3_W<'_>

Bits 10:19

pub fn duty_scale_lsch3(&mut self) -> DUTY_SCALE_LSCH3_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _LSCH3_DUTY_R>>

pub fn duty_lsch3(&mut self) -> DUTY_LSCH3_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH4_CONF0>>

pub fn para_up_lsch4(&mut self) -> PARA_UP_LSCH4_W<'_>

Bit 4

pub fn idle_lv_lsch4(&mut self) -> IDLE_LV_LSCH4_W<'_>

Bit 3

pub fn sig_out_en_lsch4(&mut self) -> SIG_OUT_EN_LSCH4_W<'_>

Bit 2

pub fn timer_sel_lsch4(&mut self) -> TIMER_SEL_LSCH4_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _LSCH4_HPOINT>>

pub fn hpoint_lsch4(&mut self) -> HPOINT_LSCH4_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _LSCH4_DUTY>>

pub fn duty_lsch4(&mut self) -> DUTY_LSCH4_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH4_CONF1>>

pub fn duty_start_lsch4(&mut self) -> DUTY_START_LSCH4_W<'_>

Bit 31

pub fn duty_inc_lsch4(&mut self) -> DUTY_INC_LSCH4_W<'_>

Bit 30

pub fn duty_num_lsch4(&mut self) -> DUTY_NUM_LSCH4_W<'_>

Bits 20:29

pub fn duty_cycle_lsch4(&mut self) -> DUTY_CYCLE_LSCH4_W<'_>

Bits 10:19

pub fn duty_scale_lsch4(&mut self) -> DUTY_SCALE_LSCH4_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _LSCH4_DUTY_R>>

pub fn duty_lsch4(&mut self) -> DUTY_LSCH4_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH5_CONF0>>

pub fn para_up_lsch5(&mut self) -> PARA_UP_LSCH5_W<'_>

Bit 4

pub fn idle_lv_lsch5(&mut self) -> IDLE_LV_LSCH5_W<'_>

Bit 3

pub fn sig_out_en_lsch5(&mut self) -> SIG_OUT_EN_LSCH5_W<'_>

Bit 2

pub fn timer_sel_lsch5(&mut self) -> TIMER_SEL_LSCH5_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _LSCH5_HPOINT>>

pub fn hpoint_lsch5(&mut self) -> HPOINT_LSCH5_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _LSCH5_DUTY>>

pub fn duty_lsch5(&mut self) -> DUTY_LSCH5_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH5_CONF1>>

pub fn duty_start_lsch5(&mut self) -> DUTY_START_LSCH5_W<'_>

Bit 31

pub fn duty_inc_lsch5(&mut self) -> DUTY_INC_LSCH5_W<'_>

Bit 30

pub fn duty_num_lsch5(&mut self) -> DUTY_NUM_LSCH5_W<'_>

Bits 20:29

pub fn duty_cycle_lsch5(&mut self) -> DUTY_CYCLE_LSCH5_W<'_>

Bits 10:19

pub fn duty_scale_lsch5(&mut self) -> DUTY_SCALE_LSCH5_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _LSCH5_DUTY_R>>

pub fn duty_lsch5(&mut self) -> DUTY_LSCH5_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH6_CONF0>>

pub fn para_up_lsch6(&mut self) -> PARA_UP_LSCH6_W<'_>

Bit 4

pub fn idle_lv_lsch6(&mut self) -> IDLE_LV_LSCH6_W<'_>

Bit 3

pub fn sig_out_en_lsch6(&mut self) -> SIG_OUT_EN_LSCH6_W<'_>

Bit 2

pub fn timer_sel_lsch6(&mut self) -> TIMER_SEL_LSCH6_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _LSCH6_HPOINT>>

pub fn hpoint_lsch6(&mut self) -> HPOINT_LSCH6_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _LSCH6_DUTY>>

pub fn duty_lsch6(&mut self) -> DUTY_LSCH6_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH6_CONF1>>

pub fn duty_start_lsch6(&mut self) -> DUTY_START_LSCH6_W<'_>

Bit 31

pub fn duty_inc_lsch6(&mut self) -> DUTY_INC_LSCH6_W<'_>

Bit 30

pub fn duty_num_lsch6(&mut self) -> DUTY_NUM_LSCH6_W<'_>

Bits 20:29

pub fn duty_cycle_lsch6(&mut self) -> DUTY_CYCLE_LSCH6_W<'_>

Bits 10:19

pub fn duty_scale_lsch6(&mut self) -> DUTY_SCALE_LSCH6_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _LSCH6_DUTY_R>>

pub fn duty_lsch6(&mut self) -> DUTY_LSCH6_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH7_CONF0>>

pub fn para_up_lsch7(&mut self) -> PARA_UP_LSCH7_W<'_>

Bit 4

pub fn idle_lv_lsch7(&mut self) -> IDLE_LV_LSCH7_W<'_>

Bit 3

pub fn sig_out_en_lsch7(&mut self) -> SIG_OUT_EN_LSCH7_W<'_>

Bit 2

pub fn timer_sel_lsch7(&mut self) -> TIMER_SEL_LSCH7_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _LSCH7_HPOINT>>

pub fn hpoint_lsch7(&mut self) -> HPOINT_LSCH7_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _LSCH7_DUTY>>

pub fn duty_lsch7(&mut self) -> DUTY_LSCH7_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _LSCH7_CONF1>>

pub fn duty_start_lsch7(&mut self) -> DUTY_START_LSCH7_W<'_>

Bit 31

pub fn duty_inc_lsch7(&mut self) -> DUTY_INC_LSCH7_W<'_>

Bit 30

pub fn duty_num_lsch7(&mut self) -> DUTY_NUM_LSCH7_W<'_>

Bits 20:29

pub fn duty_cycle_lsch7(&mut self) -> DUTY_CYCLE_LSCH7_W<'_>

Bits 10:19

pub fn duty_scale_lsch7(&mut self) -> DUTY_SCALE_LSCH7_W<'_>

Bits 0:9

impl W<u32, Reg<u32, _LSCH7_DUTY_R>>

pub fn duty_lsch7(&mut self) -> DUTY_LSCH7_W<'_>

Bits 0:24

impl W<u32, Reg<u32, _HSTIMER0_CONF>>

pub fn tick_sel_hstimer0(&mut self) -> TICK_SEL_HSTIMER0_W<'_>

Bit 25

pub fn hstimer0_rst(&mut self) -> HSTIMER0_RST_W<'_>

Bit 24

pub fn hstimer0_pause(&mut self) -> HSTIMER0_PAUSE_W<'_>

Bit 23

pub fn div_num_hstimer0(&mut self) -> DIV_NUM_HSTIMER0_W<'_>

Bits 5:22

pub fn hstimer0_lim(&mut self) -> HSTIMER0_LIM_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _HSTIMER0_VALUE>>

pub fn hstimer0_cnt(&mut self) -> HSTIMER0_CNT_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HSTIMER1_CONF>>

pub fn tick_sel_hstimer1(&mut self) -> TICK_SEL_HSTIMER1_W<'_>

Bit 25

pub fn hstimer1_rst(&mut self) -> HSTIMER1_RST_W<'_>

Bit 24

pub fn hstimer1_pause(&mut self) -> HSTIMER1_PAUSE_W<'_>

Bit 23

pub fn div_num_hstimer1(&mut self) -> DIV_NUM_HSTIMER1_W<'_>

Bits 5:22

pub fn hstimer1_lim(&mut self) -> HSTIMER1_LIM_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _HSTIMER1_VALUE>>

pub fn hstimer1_cnt(&mut self) -> HSTIMER1_CNT_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HSTIMER2_CONF>>

pub fn tick_sel_hstimer2(&mut self) -> TICK_SEL_HSTIMER2_W<'_>

Bit 25

pub fn hstimer2_rst(&mut self) -> HSTIMER2_RST_W<'_>

Bit 24

pub fn hstimer2_pause(&mut self) -> HSTIMER2_PAUSE_W<'_>

Bit 23

pub fn div_num_hstimer2(&mut self) -> DIV_NUM_HSTIMER2_W<'_>

Bits 5:22

pub fn hstimer2_lim(&mut self) -> HSTIMER2_LIM_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _HSTIMER2_VALUE>>

pub fn hstimer2_cnt(&mut self) -> HSTIMER2_CNT_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _HSTIMER3_CONF>>

pub fn tick_sel_hstimer3(&mut self) -> TICK_SEL_HSTIMER3_W<'_>

Bit 25

pub fn hstimer3_rst(&mut self) -> HSTIMER3_RST_W<'_>

Bit 24

pub fn hstimer3_pause(&mut self) -> HSTIMER3_PAUSE_W<'_>

Bit 23

pub fn div_num_hstimer3(&mut self) -> DIV_NUM_HSTIMER3_W<'_>

Bits 5:22

pub fn hstimer3_lim(&mut self) -> HSTIMER3_LIM_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _HSTIMER3_VALUE>>

pub fn hstimer3_cnt(&mut self) -> HSTIMER3_CNT_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _LSTIMER0_CONF>>

pub fn lstimer0_para_up(&mut self) -> LSTIMER0_PARA_UP_W<'_>

Bit 26

pub fn tick_sel_lstimer0(&mut self) -> TICK_SEL_LSTIMER0_W<'_>

Bit 25

pub fn lstimer0_rst(&mut self) -> LSTIMER0_RST_W<'_>

Bit 24

pub fn lstimer0_pause(&mut self) -> LSTIMER0_PAUSE_W<'_>

Bit 23

pub fn div_num_lstimer0(&mut self) -> DIV_NUM_LSTIMER0_W<'_>

Bits 5:22

pub fn lstimer0_lim(&mut self) -> LSTIMER0_LIM_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _LSTIMER0_VALUE>>

pub fn lstimer0_cnt(&mut self) -> LSTIMER0_CNT_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _LSTIMER1_CONF>>

pub fn lstimer1_para_up(&mut self) -> LSTIMER1_PARA_UP_W<'_>

Bit 26

pub fn tick_sel_lstimer1(&mut self) -> TICK_SEL_LSTIMER1_W<'_>

Bit 25

pub fn lstimer1_rst(&mut self) -> LSTIMER1_RST_W<'_>

Bit 24

pub fn lstimer1_pause(&mut self) -> LSTIMER1_PAUSE_W<'_>

Bit 23

pub fn div_num_lstimer1(&mut self) -> DIV_NUM_LSTIMER1_W<'_>

Bits 5:22

pub fn lstimer1_lim(&mut self) -> LSTIMER1_LIM_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _LSTIMER1_VALUE>>

pub fn lstimer1_cnt(&mut self) -> LSTIMER1_CNT_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _LSTIMER2_CONF>>

pub fn lstimer2_para_up(&mut self) -> LSTIMER2_PARA_UP_W<'_>

Bit 26

pub fn tick_sel_lstimer2(&mut self) -> TICK_SEL_LSTIMER2_W<'_>

Bit 25

pub fn lstimer2_rst(&mut self) -> LSTIMER2_RST_W<'_>

Bit 24

pub fn lstimer2_pause(&mut self) -> LSTIMER2_PAUSE_W<'_>

Bit 23

pub fn div_num_lstimer2(&mut self) -> DIV_NUM_LSTIMER2_W<'_>

Bits 5:22

pub fn lstimer2_lim(&mut self) -> LSTIMER2_LIM_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _LSTIMER2_VALUE>>

pub fn lstimer2_cnt(&mut self) -> LSTIMER2_CNT_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _LSTIMER3_CONF>>

pub fn lstimer3_para_up(&mut self) -> LSTIMER3_PARA_UP_W<'_>

Bit 26

pub fn tick_sel_lstimer3(&mut self) -> TICK_SEL_LSTIMER3_W<'_>

Bit 25

pub fn lstimer3_rst(&mut self) -> LSTIMER3_RST_W<'_>

Bit 24

pub fn lstimer3_pause(&mut self) -> LSTIMER3_PAUSE_W<'_>

Bit 23

pub fn div_num_lstimer3(&mut self) -> DIV_NUM_LSTIMER3_W<'_>

Bits 5:22

pub fn lstimer3_lim(&mut self) -> LSTIMER3_LIM_W<'_>

Bits 0:4

impl W<u32, Reg<u32, _LSTIMER3_VALUE>>

pub fn lstimer3_cnt(&mut self) -> LSTIMER3_CNT_W<'_>

Bits 0:19

impl W<u32, Reg<u32, _INT_RAW>>

pub fn duty_chng_end_lsch7_int_raw(
    &mut self
) -> DUTY_CHNG_END_LSCH7_INT_RAW_W<'_>

Bit 23

pub fn duty_chng_end_lsch6_int_raw(
    &mut self
) -> DUTY_CHNG_END_LSCH6_INT_RAW_W<'_>

Bit 22

pub fn duty_chng_end_lsch5_int_raw(
    &mut self
) -> DUTY_CHNG_END_LSCH5_INT_RAW_W<'_>

Bit 21

pub fn duty_chng_end_lsch4_int_raw(
    &mut self
) -> DUTY_CHNG_END_LSCH4_INT_RAW_W<'_>

Bit 20

pub fn duty_chng_end_lsch3_int_raw(
    &mut self
) -> DUTY_CHNG_END_LSCH3_INT_RAW_W<'_>

Bit 19

pub fn duty_chng_end_lsch2_int_raw(
    &mut self
) -> DUTY_CHNG_END_LSCH2_INT_RAW_W<'_>

Bit 18

pub fn duty_chng_end_lsch1_int_raw(
    &mut self
) -> DUTY_CHNG_END_LSCH1_INT_RAW_W<'_>

Bit 17

pub fn duty_chng_end_lsch0_int_raw(
    &mut self
) -> DUTY_CHNG_END_LSCH0_INT_RAW_W<'_>

Bit 16

pub fn duty_chng_end_hsch7_int_raw(
    &mut self
) -> DUTY_CHNG_END_HSCH7_INT_RAW_W<'_>

Bit 15

pub fn duty_chng_end_hsch6_int_raw(
    &mut self
) -> DUTY_CHNG_END_HSCH6_INT_RAW_W<'_>

Bit 14

pub fn duty_chng_end_hsch5_int_raw(
    &mut self
) -> DUTY_CHNG_END_HSCH5_INT_RAW_W<'_>

Bit 13

pub fn duty_chng_end_hsch4_int_raw(
    &mut self
) -> DUTY_CHNG_END_HSCH4_INT_RAW_W<'_>

Bit 12

pub fn duty_chng_end_hsch3_int_raw(
    &mut self
) -> DUTY_CHNG_END_HSCH3_INT_RAW_W<'_>

Bit 11

pub fn duty_chng_end_hsch2_int_raw(
    &mut self
) -> DUTY_CHNG_END_HSCH2_INT_RAW_W<'_>

Bit 10

pub fn duty_chng_end_hsch1_int_raw(
    &mut self
) -> DUTY_CHNG_END_HSCH1_INT_RAW_W<'_>

Bit 9

pub fn duty_chng_end_hsch0_int_raw(
    &mut self
) -> DUTY_CHNG_END_HSCH0_INT_RAW_W<'_>

Bit 8

pub fn lstimer3_ovf_int_raw(&mut self) -> LSTIMER3_OVF_INT_RAW_W<'_>

Bit 7

pub fn lstimer2_ovf_int_raw(&mut self) -> LSTIMER2_OVF_INT_RAW_W<'_>

Bit 6

pub fn lstimer1_ovf_int_raw(&mut self) -> LSTIMER1_OVF_INT_RAW_W<'_>

Bit 5

pub fn lstimer0_ovf_int_raw(&mut self) -> LSTIMER0_OVF_INT_RAW_W<'_>

Bit 4

pub fn hstimer3_ovf_int_raw(&mut self) -> HSTIMER3_OVF_INT_RAW_W<'_>

Bit 3

pub fn hstimer2_ovf_int_raw(&mut self) -> HSTIMER2_OVF_INT_RAW_W<'_>

Bit 2

pub fn hstimer1_ovf_int_raw(&mut self) -> HSTIMER1_OVF_INT_RAW_W<'_>

Bit 1

pub fn hstimer0_ovf_int_raw(&mut self) -> HSTIMER0_OVF_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ST>>

pub fn duty_chng_end_lsch7_int_st(&mut self) -> DUTY_CHNG_END_LSCH7_INT_ST_W<'_>

Bit 23

pub fn duty_chng_end_lsch6_int_st(&mut self) -> DUTY_CHNG_END_LSCH6_INT_ST_W<'_>

Bit 22

pub fn duty_chng_end_lsch5_int_st(&mut self) -> DUTY_CHNG_END_LSCH5_INT_ST_W<'_>

Bit 21

pub fn duty_chng_end_lsch4_int_st(&mut self) -> DUTY_CHNG_END_LSCH4_INT_ST_W<'_>

Bit 20

pub fn duty_chng_end_lsch3_int_st(&mut self) -> DUTY_CHNG_END_LSCH3_INT_ST_W<'_>

Bit 19

pub fn duty_chng_end_lsch2_int_st(&mut self) -> DUTY_CHNG_END_LSCH2_INT_ST_W<'_>

Bit 18

pub fn duty_chng_end_lsch1_int_st(&mut self) -> DUTY_CHNG_END_LSCH1_INT_ST_W<'_>

Bit 17

pub fn duty_chng_end_lsch0_int_st(&mut self) -> DUTY_CHNG_END_LSCH0_INT_ST_W<'_>

Bit 16

pub fn duty_chng_end_hsch7_int_st(&mut self) -> DUTY_CHNG_END_HSCH7_INT_ST_W<'_>

Bit 15

pub fn duty_chng_end_hsch6_int_st(&mut self) -> DUTY_CHNG_END_HSCH6_INT_ST_W<'_>

Bit 14

pub fn duty_chng_end_hsch5_int_st(&mut self) -> DUTY_CHNG_END_HSCH5_INT_ST_W<'_>

Bit 13

pub fn duty_chng_end_hsch4_int_st(&mut self) -> DUTY_CHNG_END_HSCH4_INT_ST_W<'_>

Bit 12

pub fn duty_chng_end_hsch3_int_st(&mut self) -> DUTY_CHNG_END_HSCH3_INT_ST_W<'_>

Bit 11

pub fn duty_chng_end_hsch2_int_st(&mut self) -> DUTY_CHNG_END_HSCH2_INT_ST_W<'_>

Bit 10

pub fn duty_chng_end_hsch1_int_st(&mut self) -> DUTY_CHNG_END_HSCH1_INT_ST_W<'_>

Bit 9

pub fn duty_chng_end_hsch0_int_st(&mut self) -> DUTY_CHNG_END_HSCH0_INT_ST_W<'_>

Bit 8

pub fn lstimer3_ovf_int_st(&mut self) -> LSTIMER3_OVF_INT_ST_W<'_>

Bit 7

pub fn lstimer2_ovf_int_st(&mut self) -> LSTIMER2_OVF_INT_ST_W<'_>

Bit 6

pub fn lstimer1_ovf_int_st(&mut self) -> LSTIMER1_OVF_INT_ST_W<'_>

Bit 5

pub fn lstimer0_ovf_int_st(&mut self) -> LSTIMER0_OVF_INT_ST_W<'_>

Bit 4

pub fn hstimer3_ovf_int_st(&mut self) -> HSTIMER3_OVF_INT_ST_W<'_>

Bit 3

pub fn hstimer2_ovf_int_st(&mut self) -> HSTIMER2_OVF_INT_ST_W<'_>

Bit 2

pub fn hstimer1_ovf_int_st(&mut self) -> HSTIMER1_OVF_INT_ST_W<'_>

Bit 1

pub fn hstimer0_ovf_int_st(&mut self) -> HSTIMER0_OVF_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_ENA>>

pub fn duty_chng_end_lsch7_int_ena(
    &mut self
) -> DUTY_CHNG_END_LSCH7_INT_ENA_W<'_>

Bit 23

pub fn duty_chng_end_lsch6_int_ena(
    &mut self
) -> DUTY_CHNG_END_LSCH6_INT_ENA_W<'_>

Bit 22

pub fn duty_chng_end_lsch5_int_ena(
    &mut self
) -> DUTY_CHNG_END_LSCH5_INT_ENA_W<'_>

Bit 21

pub fn duty_chng_end_lsch4_int_ena(
    &mut self
) -> DUTY_CHNG_END_LSCH4_INT_ENA_W<'_>

Bit 20

pub fn duty_chng_end_lsch3_int_ena(
    &mut self
) -> DUTY_CHNG_END_LSCH3_INT_ENA_W<'_>

Bit 19

pub fn duty_chng_end_lsch2_int_ena(
    &mut self
) -> DUTY_CHNG_END_LSCH2_INT_ENA_W<'_>

Bit 18

pub fn duty_chng_end_lsch1_int_ena(
    &mut self
) -> DUTY_CHNG_END_LSCH1_INT_ENA_W<'_>

Bit 17

pub fn duty_chng_end_lsch0_int_ena(
    &mut self
) -> DUTY_CHNG_END_LSCH0_INT_ENA_W<'_>

Bit 16

pub fn duty_chng_end_hsch7_int_ena(
    &mut self
) -> DUTY_CHNG_END_HSCH7_INT_ENA_W<'_>

Bit 15

pub fn duty_chng_end_hsch6_int_ena(
    &mut self
) -> DUTY_CHNG_END_HSCH6_INT_ENA_W<'_>

Bit 14

pub fn duty_chng_end_hsch5_int_ena(
    &mut self
) -> DUTY_CHNG_END_HSCH5_INT_ENA_W<'_>

Bit 13

pub fn duty_chng_end_hsch4_int_ena(
    &mut self
) -> DUTY_CHNG_END_HSCH4_INT_ENA_W<'_>

Bit 12

pub fn duty_chng_end_hsch3_int_ena(
    &mut self
) -> DUTY_CHNG_END_HSCH3_INT_ENA_W<'_>

Bit 11

pub fn duty_chng_end_hsch2_int_ena(
    &mut self
) -> DUTY_CHNG_END_HSCH2_INT_ENA_W<'_>

Bit 10

pub fn duty_chng_end_hsch1_int_ena(
    &mut self
) -> DUTY_CHNG_END_HSCH1_INT_ENA_W<'_>

Bit 9

pub fn duty_chng_end_hsch0_int_ena(
    &mut self
) -> DUTY_CHNG_END_HSCH0_INT_ENA_W<'_>

Bit 8

pub fn lstimer3_ovf_int_ena(&mut self) -> LSTIMER3_OVF_INT_ENA_W<'_>

Bit 7

pub fn lstimer2_ovf_int_ena(&mut self) -> LSTIMER2_OVF_INT_ENA_W<'_>

Bit 6

pub fn lstimer1_ovf_int_ena(&mut self) -> LSTIMER1_OVF_INT_ENA_W<'_>

Bit 5

pub fn lstimer0_ovf_int_ena(&mut self) -> LSTIMER0_OVF_INT_ENA_W<'_>

Bit 4

pub fn hstimer3_ovf_int_ena(&mut self) -> HSTIMER3_OVF_INT_ENA_W<'_>

Bit 3

pub fn hstimer2_ovf_int_ena(&mut self) -> HSTIMER2_OVF_INT_ENA_W<'_>

Bit 2

pub fn hstimer1_ovf_int_ena(&mut self) -> HSTIMER1_OVF_INT_ENA_W<'_>

Bit 1

pub fn hstimer0_ovf_int_ena(&mut self) -> HSTIMER0_OVF_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _INT_CLR>>

pub fn duty_chng_end_lsch7_int_clr(
    &mut self
) -> DUTY_CHNG_END_LSCH7_INT_CLR_W<'_>

Bit 23

pub fn duty_chng_end_lsch6_int_clr(
    &mut self
) -> DUTY_CHNG_END_LSCH6_INT_CLR_W<'_>

Bit 22

pub fn duty_chng_end_lsch5_int_clr(
    &mut self
) -> DUTY_CHNG_END_LSCH5_INT_CLR_W<'_>

Bit 21

pub fn duty_chng_end_lsch4_int_clr(
    &mut self
) -> DUTY_CHNG_END_LSCH4_INT_CLR_W<'_>

Bit 20

pub fn duty_chng_end_lsch3_int_clr(
    &mut self
) -> DUTY_CHNG_END_LSCH3_INT_CLR_W<'_>

Bit 19

pub fn duty_chng_end_lsch2_int_clr(
    &mut self
) -> DUTY_CHNG_END_LSCH2_INT_CLR_W<'_>

Bit 18

pub fn duty_chng_end_lsch1_int_clr(
    &mut self
) -> DUTY_CHNG_END_LSCH1_INT_CLR_W<'_>

Bit 17

pub fn duty_chng_end_lsch0_int_clr(
    &mut self
) -> DUTY_CHNG_END_LSCH0_INT_CLR_W<'_>

Bit 16

pub fn duty_chng_end_hsch7_int_clr(
    &mut self
) -> DUTY_CHNG_END_HSCH7_INT_CLR_W<'_>

Bit 15

pub fn duty_chng_end_hsch6_int_clr(
    &mut self
) -> DUTY_CHNG_END_HSCH6_INT_CLR_W<'_>

Bit 14

pub fn duty_chng_end_hsch5_int_clr(
    &mut self
) -> DUTY_CHNG_END_HSCH5_INT_CLR_W<'_>

Bit 13

pub fn duty_chng_end_hsch4_int_clr(
    &mut self
) -> DUTY_CHNG_END_HSCH4_INT_CLR_W<'_>

Bit 12

pub fn duty_chng_end_hsch3_int_clr(
    &mut self
) -> DUTY_CHNG_END_HSCH3_INT_CLR_W<'_>

Bit 11

pub fn duty_chng_end_hsch2_int_clr(
    &mut self
) -> DUTY_CHNG_END_HSCH2_INT_CLR_W<'_>

Bit 10

pub fn duty_chng_end_hsch1_int_clr(
    &mut self
) -> DUTY_CHNG_END_HSCH1_INT_CLR_W<'_>

Bit 9

pub fn duty_chng_end_hsch0_int_clr(
    &mut self
) -> DUTY_CHNG_END_HSCH0_INT_CLR_W<'_>

Bit 8

pub fn lstimer3_ovf_int_clr(&mut self) -> LSTIMER3_OVF_INT_CLR_W<'_>

Bit 7

pub fn lstimer2_ovf_int_clr(&mut self) -> LSTIMER2_OVF_INT_CLR_W<'_>

Bit 6

pub fn lstimer1_ovf_int_clr(&mut self) -> LSTIMER1_OVF_INT_CLR_W<'_>

Bit 5

pub fn lstimer0_ovf_int_clr(&mut self) -> LSTIMER0_OVF_INT_CLR_W<'_>

Bit 4

pub fn hstimer3_ovf_int_clr(&mut self) -> HSTIMER3_OVF_INT_CLR_W<'_>

Bit 3

pub fn hstimer2_ovf_int_clr(&mut self) -> HSTIMER2_OVF_INT_CLR_W<'_>

Bit 2

pub fn hstimer1_ovf_int_clr(&mut self) -> HSTIMER1_OVF_INT_CLR_W<'_>

Bit 1

pub fn hstimer0_ovf_int_clr(&mut self) -> HSTIMER0_OVF_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, _CONF>>

pub fn apb_clk_sel(&mut self) -> APB_CLK_SEL_W<'_>

Bit 0

impl W<u32, Reg<u32, _DATE>>

pub fn date(&mut self) -> DATE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CLK_CFG>>

pub fn clk_prescale(&mut self) -> CLK_PRESCALE_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _TIMER0_CFG0>>

pub fn timer0_period_upmethod(&mut self) -> TIMER0_PERIOD_UPMETHOD_W<'_>

Bits 24:25

pub fn timer0_period(&mut self) -> TIMER0_PERIOD_W<'_>

Bits 8:23

pub fn timer0_prescale(&mut self) -> TIMER0_PRESCALE_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _TIMER0_CFG1>>

pub fn timer0_mod(&mut self) -> TIMER0_MOD_W<'_>

Bits 3:4

pub fn timer0_start(&mut self) -> TIMER0_START_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _TIMER0_SYNC>>

pub fn timer0_phase(&mut self) -> TIMER0_PHASE_W<'_>

Bits 4:20

pub fn timer0_synco_sel(&mut self) -> TIMER0_SYNCO_SEL_W<'_>

Bits 2:3

pub fn timer0_sync_sw(&mut self) -> TIMER0_SYNC_SW_W<'_>

Bit 1

pub fn timer0_synci_en(&mut self) -> TIMER0_SYNCI_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _TIMER0_STATUS>>

pub fn timer0_direction(&mut self) -> TIMER0_DIRECTION_W<'_>

Bit 16

pub fn timer0_value(&mut self) -> TIMER0_VALUE_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _TIMER1_CFG0>>

pub fn timer1_period_upmethod(&mut self) -> TIMER1_PERIOD_UPMETHOD_W<'_>

Bits 24:25

pub fn timer1_period(&mut self) -> TIMER1_PERIOD_W<'_>

Bits 8:23

pub fn timer1_prescale(&mut self) -> TIMER1_PRESCALE_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _TIMER1_CFG1>>

pub fn timer1_mod(&mut self) -> TIMER1_MOD_W<'_>

Bits 3:4

pub fn timer1_start(&mut self) -> TIMER1_START_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _TIMER1_SYNC>>

pub fn timer1_phase(&mut self) -> TIMER1_PHASE_W<'_>

Bits 4:20

pub fn timer1_synco_sel(&mut self) -> TIMER1_SYNCO_SEL_W<'_>

Bits 2:3

pub fn timer1_sync_sw(&mut self) -> TIMER1_SYNC_SW_W<'_>

Bit 1

pub fn timer1_synci_en(&mut self) -> TIMER1_SYNCI_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _TIMER1_STATUS>>

pub fn timer1_direction(&mut self) -> TIMER1_DIRECTION_W<'_>

Bit 16

pub fn timer1_value(&mut self) -> TIMER1_VALUE_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _TIMER2_CFG0>>

pub fn timer2_period_upmethod(&mut self) -> TIMER2_PERIOD_UPMETHOD_W<'_>

Bits 24:25

pub fn timer2_period(&mut self) -> TIMER2_PERIOD_W<'_>

Bits 8:23

pub fn timer2_prescale(&mut self) -> TIMER2_PRESCALE_W<'_>

Bits 0:7

impl W<u32, Reg<u32, _TIMER2_CFG1>>

pub fn timer2_mod(&mut self) -> TIMER2_MOD_W<'_>

Bits 3:4

pub fn timer2_start(&mut self) -> TIMER2_START_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _TIMER2_SYNC>>

pub fn timer2_phase(&mut self) -> TIMER2_PHASE_W<'_>

Bits 4:20

pub fn timer2_synco_sel(&mut self) -> TIMER2_SYNCO_SEL_W<'_>

Bits 2:3

pub fn timer2_sync_sw(&mut self) -> TIMER2_SYNC_SW_W<'_>

Bit 1

pub fn timer2_synci_en(&mut self) -> TIMER2_SYNCI_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _TIMER2_STATUS>>

pub fn timer2_direction(&mut self) -> TIMER2_DIRECTION_W<'_>

Bit 16

pub fn timer2_value(&mut self) -> TIMER2_VALUE_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _TIMER_SYNCI_CFG>>

pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI2_INVERT_W<'_>

Bit 11

pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI1_INVERT_W<'_>

Bit 10

pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI0_INVERT_W<'_>

Bit 9

pub fn timer2_syncisel(&mut self) -> TIMER2_SYNCISEL_W<'_>

Bits 6:8

pub fn timer1_syncisel(&mut self) -> TIMER1_SYNCISEL_W<'_>

Bits 3:5

pub fn timer0_syncisel(&mut self) -> TIMER0_SYNCISEL_W<'_>

Bits 0:2

impl W<u32, Reg<u32, _OPERATOR_TIMERSEL>>

pub fn operator2_timersel(&mut self) -> OPERATOR2_TIMERSEL_W<'_>

Bits 4:5

pub fn operator1_timersel(&mut self) -> OPERATOR1_TIMERSEL_W<'_>

Bits 2:3

pub fn operator0_timersel(&mut self) -> OPERATOR0_TIMERSEL_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _GEN0_STMP_CFG>>

pub fn gen0_b_shdw_full(&mut self) -> GEN0_B_SHDW_FULL_W<'_>

Bit 9

pub fn gen0_a_shdw_full(&mut self) -> GEN0_A_SHDW_FULL_W<'_>

Bit 8

pub fn gen0_b_upmethod(&mut self) -> GEN0_B_UPMETHOD_W<'_>

Bits 4:7

pub fn gen0_a_upmethod(&mut self) -> GEN0_A_UPMETHOD_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _GEN0_TSTMP_A>>

pub fn gen0_a(&mut self) -> GEN0_A_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _GEN0_TSTMP_B>>

pub fn gen0_b(&mut self) -> GEN0_B_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _GEN0_CFG0>>

pub fn gen0_t1_sel(&mut self) -> GEN0_T1_SEL_W<'_>

Bits 7:9

pub fn gen0_t0_sel(&mut self) -> GEN0_T0_SEL_W<'_>

Bits 4:6

pub fn gen0_cfg_upmethod(&mut self) -> GEN0_CFG_UPMETHOD_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _GEN0_FORCE>>

pub fn gen0_b_nciforce_mode(&mut self) -> GEN0_B_NCIFORCE_MODE_W<'_>

Bits 14:15

pub fn gen0_b_nciforce(&mut self) -> GEN0_B_NCIFORCE_W<'_>

Bit 13

pub fn gen0_a_nciforce_mode(&mut self) -> GEN0_A_NCIFORCE_MODE_W<'_>

Bits 11:12

pub fn gen0_a_nciforce(&mut self) -> GEN0_A_NCIFORCE_W<'_>

Bit 10

pub fn gen0_b_cntuforce_mode(&mut self) -> GEN0_B_CNTUFORCE_MODE_W<'_>

Bits 8:9

pub fn gen0_a_cntuforce_mode(&mut self) -> GEN0_A_CNTUFORCE_MODE_W<'_>

Bits 6:7

pub fn gen0_cntuforce_upmethod(&mut self) -> GEN0_CNTUFORCE_UPMETHOD_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _GEN0_A>>

pub fn gen0_a_dt1(&mut self) -> GEN0_A_DT1_W<'_>

Bits 22:23

pub fn gen0_a_dt0(&mut self) -> GEN0_A_DT0_W<'_>

Bits 20:21

pub fn gen0_a_dteb(&mut self) -> GEN0_A_DTEB_W<'_>

Bits 18:19

pub fn gen0_a_dtea(&mut self) -> GEN0_A_DTEA_W<'_>

Bits 16:17

pub fn gen0_a_dtep(&mut self) -> GEN0_A_DTEP_W<'_>

Bits 14:15

pub fn gen0_a_dtez(&mut self) -> GEN0_A_DTEZ_W<'_>

Bits 12:13

pub fn gen0_a_ut1(&mut self) -> GEN0_A_UT1_W<'_>

Bits 10:11

pub fn gen0_a_ut0(&mut self) -> GEN0_A_UT0_W<'_>

Bits 8:9

pub fn gen0_a_uteb(&mut self) -> GEN0_A_UTEB_W<'_>

Bits 6:7

pub fn gen0_a_utea(&mut self) -> GEN0_A_UTEA_W<'_>

Bits 4:5

pub fn gen0_a_utep(&mut self) -> GEN0_A_UTEP_W<'_>

Bits 2:3

pub fn gen0_a_utez(&mut self) -> GEN0_A_UTEZ_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _GEN0_B>>

pub fn gen0_b_dt1(&mut self) -> GEN0_B_DT1_W<'_>

Bits 22:23

pub fn gen0_b_dt0(&mut self) -> GEN0_B_DT0_W<'_>

Bits 20:21

pub fn gen0_b_dteb(&mut self) -> GEN0_B_DTEB_W<'_>

Bits 18:19

pub fn gen0_b_dtea(&mut self) -> GEN0_B_DTEA_W<'_>

Bits 16:17

pub fn gen0_b_dtep(&mut self) -> GEN0_B_DTEP_W<'_>

Bits 14:15

pub fn gen0_b_dtez(&mut self) -> GEN0_B_DTEZ_W<'_>

Bits 12:13

pub fn gen0_b_ut1(&mut self) -> GEN0_B_UT1_W<'_>

Bits 10:11

pub fn gen0_b_ut0(&mut self) -> GEN0_B_UT0_W<'_>

Bits 8:9

pub fn gen0_b_uteb(&mut self) -> GEN0_B_UTEB_W<'_>

Bits 6:7

pub fn gen0_b_utea(&mut self) -> GEN0_B_UTEA_W<'_>

Bits 4:5

pub fn gen0_b_utep(&mut self) -> GEN0_B_UTEP_W<'_>

Bits 2:3

pub fn gen0_b_utez(&mut self) -> GEN0_B_UTEZ_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _DT0_CFG>>

pub fn dt0_clk_sel(&mut self) -> DT0_CLK_SEL_W<'_>

Bit 17

pub fn dt0_b_outbypass(&mut self) -> DT0_B_OUTBYPASS_W<'_>

Bit 16

pub fn dt0_a_outbypass(&mut self) -> DT0_A_OUTBYPASS_W<'_>

Bit 15

pub fn dt0_fed_outinvert(&mut self) -> DT0_FED_OUTINVERT_W<'_>

Bit 14

pub fn dt0_red_outinvert(&mut self) -> DT0_RED_OUTINVERT_W<'_>

Bit 13

pub fn dt0_fed_insel(&mut self) -> DT0_FED_INSEL_W<'_>

Bit 12

pub fn dt0_red_insel(&mut self) -> DT0_RED_INSEL_W<'_>

Bit 11

pub fn dt0_b_outswap(&mut self) -> DT0_B_OUTSWAP_W<'_>

Bit 10

pub fn dt0_a_outswap(&mut self) -> DT0_A_OUTSWAP_W<'_>

Bit 9

pub fn dt0_deb_mode(&mut self) -> DT0_DEB_MODE_W<'_>

Bit 8

pub fn dt0_red_upmethod(&mut self) -> DT0_RED_UPMETHOD_W<'_>

Bits 4:7

pub fn dt0_fed_upmethod(&mut self) -> DT0_FED_UPMETHOD_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _DT0_FED_CFG>>

pub fn dt0_fed(&mut self) -> DT0_FED_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _DT0_RED_CFG>>

pub fn dt0_red(&mut self) -> DT0_RED_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CARRIER0_CFG>>

pub fn carrier0_in_invert(&mut self) -> CARRIER0_IN_INVERT_W<'_>

Bit 13

pub fn carrier0_out_invert(&mut self) -> CARRIER0_OUT_INVERT_W<'_>

Bit 12

pub fn carrier0_oshwth(&mut self) -> CARRIER0_OSHWTH_W<'_>

Bits 8:11

pub fn carrier0_duty(&mut self) -> CARRIER0_DUTY_W<'_>

Bits 5:7

pub fn carrier0_prescale(&mut self) -> CARRIER0_PRESCALE_W<'_>

Bits 1:4

pub fn carrier0_en(&mut self) -> CARRIER0_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _FH0_CFG0>>

pub fn fh0_b_ost_u(&mut self) -> FH0_B_OST_U_W<'_>

Bits 22:23

pub fn fh0_b_ost_d(&mut self) -> FH0_B_OST_D_W<'_>

Bits 20:21

pub fn fh0_b_cbc_u(&mut self) -> FH0_B_CBC_U_W<'_>

Bits 18:19

pub fn fh0_b_cbc_d(&mut self) -> FH0_B_CBC_D_W<'_>

Bits 16:17

pub fn fh0_a_ost_u(&mut self) -> FH0_A_OST_U_W<'_>

Bits 14:15

pub fn fh0_a_ost_d(&mut self) -> FH0_A_OST_D_W<'_>

Bits 12:13

pub fn fh0_a_cbc_u(&mut self) -> FH0_A_CBC_U_W<'_>

Bits 10:11

pub fn fh0_a_cbc_d(&mut self) -> FH0_A_CBC_D_W<'_>

Bits 8:9

pub fn fh0_f0_ost(&mut self) -> FH0_F0_OST_W<'_>

Bit 7

pub fn fh0_f1_ost(&mut self) -> FH0_F1_OST_W<'_>

Bit 6

pub fn fh0_f2_ost(&mut self) -> FH0_F2_OST_W<'_>

Bit 5

pub fn fh0_sw_ost(&mut self) -> FH0_SW_OST_W<'_>

Bit 4

pub fn fh0_f0_cbc(&mut self) -> FH0_F0_CBC_W<'_>

Bit 3

pub fn fh0_f1_cbc(&mut self) -> FH0_F1_CBC_W<'_>

Bit 2

pub fn fh0_f2_cbc(&mut self) -> FH0_F2_CBC_W<'_>

Bit 1

pub fn fh0_sw_cbc(&mut self) -> FH0_SW_CBC_W<'_>

Bit 0

impl W<u32, Reg<u32, _FH0_CFG1>>

pub fn fh0_force_ost(&mut self) -> FH0_FORCE_OST_W<'_>

Bit 4

pub fn fh0_force_cbc(&mut self) -> FH0_FORCE_CBC_W<'_>

Bit 3

pub fn fh0_cbcpulse(&mut self) -> FH0_CBCPULSE_W<'_>

Bits 1:2

pub fn fh0_clr_ost(&mut self) -> FH0_CLR_OST_W<'_>

Bit 0

impl W<u32, Reg<u32, _FH0_STATUS>>

pub fn fh0_ost_on(&mut self) -> FH0_OST_ON_W<'_>

Bit 1

pub fn fh0_cbc_on(&mut self) -> FH0_CBC_ON_W<'_>

Bit 0

impl W<u32, Reg<u32, _GEN1_STMP_CFG>>

pub fn gen1_b_shdw_full(&mut self) -> GEN1_B_SHDW_FULL_W<'_>

Bit 9

pub fn gen1_a_shdw_full(&mut self) -> GEN1_A_SHDW_FULL_W<'_>

Bit 8

pub fn gen1_b_upmethod(&mut self) -> GEN1_B_UPMETHOD_W<'_>

Bits 4:7

pub fn gen1_a_upmethod(&mut self) -> GEN1_A_UPMETHOD_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _GEN1_TSTMP_A>>

pub fn gen1_a(&mut self) -> GEN1_A_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _GEN1_TSTMP_B>>

pub fn gen1_b(&mut self) -> GEN1_B_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _GEN1_CFG0>>

pub fn gen1_t1_sel(&mut self) -> GEN1_T1_SEL_W<'_>

Bits 7:9

pub fn gen1_t0_sel(&mut self) -> GEN1_T0_SEL_W<'_>

Bits 4:6

pub fn gen1_cfg_upmethod(&mut self) -> GEN1_CFG_UPMETHOD_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _GEN1_FORCE>>

pub fn gen1_b_nciforce_mode(&mut self) -> GEN1_B_NCIFORCE_MODE_W<'_>

Bits 14:15

pub fn gen1_b_nciforce(&mut self) -> GEN1_B_NCIFORCE_W<'_>

Bit 13

pub fn gen1_a_nciforce_mode(&mut self) -> GEN1_A_NCIFORCE_MODE_W<'_>

Bits 11:12

pub fn gen1_a_nciforce(&mut self) -> GEN1_A_NCIFORCE_W<'_>

Bit 10

pub fn gen1_b_cntuforce_mode(&mut self) -> GEN1_B_CNTUFORCE_MODE_W<'_>

Bits 8:9

pub fn gen1_a_cntuforce_mode(&mut self) -> GEN1_A_CNTUFORCE_MODE_W<'_>

Bits 6:7

pub fn gen1_cntuforce_upmethod(&mut self) -> GEN1_CNTUFORCE_UPMETHOD_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _GEN1_A>>

pub fn gen1_a_dt1(&mut self) -> GEN1_A_DT1_W<'_>

Bits 22:23

pub fn gen1_a_dt0(&mut self) -> GEN1_A_DT0_W<'_>

Bits 20:21

pub fn gen1_a_dteb(&mut self) -> GEN1_A_DTEB_W<'_>

Bits 18:19

pub fn gen1_a_dtea(&mut self) -> GEN1_A_DTEA_W<'_>

Bits 16:17

pub fn gen1_a_dtep(&mut self) -> GEN1_A_DTEP_W<'_>

Bits 14:15

pub fn gen1_a_dtez(&mut self) -> GEN1_A_DTEZ_W<'_>

Bits 12:13

pub fn gen1_a_ut1(&mut self) -> GEN1_A_UT1_W<'_>

Bits 10:11

pub fn gen1_a_ut0(&mut self) -> GEN1_A_UT0_W<'_>

Bits 8:9

pub fn gen1_a_uteb(&mut self) -> GEN1_A_UTEB_W<'_>

Bits 6:7

pub fn gen1_a_utea(&mut self) -> GEN1_A_UTEA_W<'_>

Bits 4:5

pub fn gen1_a_utep(&mut self) -> GEN1_A_UTEP_W<'_>

Bits 2:3

pub fn gen1_a_utez(&mut self) -> GEN1_A_UTEZ_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _GEN1_B>>

pub fn gen1_b_dt1(&mut self) -> GEN1_B_DT1_W<'_>

Bits 22:23

pub fn gen1_b_dt0(&mut self) -> GEN1_B_DT0_W<'_>

Bits 20:21

pub fn gen1_b_dteb(&mut self) -> GEN1_B_DTEB_W<'_>

Bits 18:19

pub fn gen1_b_dtea(&mut self) -> GEN1_B_DTEA_W<'_>

Bits 16:17

pub fn gen1_b_dtep(&mut self) -> GEN1_B_DTEP_W<'_>

Bits 14:15

pub fn gen1_b_dtez(&mut self) -> GEN1_B_DTEZ_W<'_>

Bits 12:13

pub fn gen1_b_ut1(&mut self) -> GEN1_B_UT1_W<'_>

Bits 10:11

pub fn gen1_b_ut0(&mut self) -> GEN1_B_UT0_W<'_>

Bits 8:9

pub fn gen1_b_uteb(&mut self) -> GEN1_B_UTEB_W<'_>

Bits 6:7

pub fn gen1_b_utea(&mut self) -> GEN1_B_UTEA_W<'_>

Bits 4:5

pub fn gen1_b_utep(&mut self) -> GEN1_B_UTEP_W<'_>

Bits 2:3

pub fn gen1_b_utez(&mut self) -> GEN1_B_UTEZ_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _DT1_CFG>>

pub fn dt1_clk_sel(&mut self) -> DT1_CLK_SEL_W<'_>

Bit 17

pub fn dt1_b_outbypass(&mut self) -> DT1_B_OUTBYPASS_W<'_>

Bit 16

pub fn dt1_a_outbypass(&mut self) -> DT1_A_OUTBYPASS_W<'_>

Bit 15

pub fn dt1_fed_outinvert(&mut self) -> DT1_FED_OUTINVERT_W<'_>

Bit 14

pub fn dt1_red_outinvert(&mut self) -> DT1_RED_OUTINVERT_W<'_>

Bit 13

pub fn dt1_fed_insel(&mut self) -> DT1_FED_INSEL_W<'_>

Bit 12

pub fn dt1_red_insel(&mut self) -> DT1_RED_INSEL_W<'_>

Bit 11

pub fn dt1_b_outswap(&mut self) -> DT1_B_OUTSWAP_W<'_>

Bit 10

pub fn dt1_a_outswap(&mut self) -> DT1_A_OUTSWAP_W<'_>

Bit 9

pub fn dt1_deb_mode(&mut self) -> DT1_DEB_MODE_W<'_>

Bit 8

pub fn dt1_red_upmethod(&mut self) -> DT1_RED_UPMETHOD_W<'_>

Bits 4:7

pub fn dt1_fed_upmethod(&mut self) -> DT1_FED_UPMETHOD_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _DT1_FED_CFG>>

pub fn dt1_fed(&mut self) -> DT1_FED_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _DT1_RED_CFG>>

pub fn dt1_red(&mut self) -> DT1_RED_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CARRIER1_CFG>>

pub fn carrier1_in_invert(&mut self) -> CARRIER1_IN_INVERT_W<'_>

Bit 13

pub fn carrier1_out_invert(&mut self) -> CARRIER1_OUT_INVERT_W<'_>

Bit 12

pub fn carrier1_oshwth(&mut self) -> CARRIER1_OSHWTH_W<'_>

Bits 8:11

pub fn carrier1_duty(&mut self) -> CARRIER1_DUTY_W<'_>

Bits 5:7

pub fn carrier1_prescale(&mut self) -> CARRIER1_PRESCALE_W<'_>

Bits 1:4

pub fn carrier1_en(&mut self) -> CARRIER1_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _FH1_CFG0>>

pub fn fh1_b_ost_u(&mut self) -> FH1_B_OST_U_W<'_>

Bits 22:23

pub fn fh1_b_ost_d(&mut self) -> FH1_B_OST_D_W<'_>

Bits 20:21

pub fn fh1_b_cbc_u(&mut self) -> FH1_B_CBC_U_W<'_>

Bits 18:19

pub fn fh1_b_cbc_d(&mut self) -> FH1_B_CBC_D_W<'_>

Bits 16:17

pub fn fh1_a_ost_u(&mut self) -> FH1_A_OST_U_W<'_>

Bits 14:15

pub fn fh1_a_ost_d(&mut self) -> FH1_A_OST_D_W<'_>

Bits 12:13

pub fn fh1_a_cbc_u(&mut self) -> FH1_A_CBC_U_W<'_>

Bits 10:11

pub fn fh1_a_cbc_d(&mut self) -> FH1_A_CBC_D_W<'_>

Bits 8:9

pub fn fh1_f0_ost(&mut self) -> FH1_F0_OST_W<'_>

Bit 7

pub fn fh1_f1_ost(&mut self) -> FH1_F1_OST_W<'_>

Bit 6

pub fn fh1_f2_ost(&mut self) -> FH1_F2_OST_W<'_>

Bit 5

pub fn fh1_sw_ost(&mut self) -> FH1_SW_OST_W<'_>

Bit 4

pub fn fh1_f0_cbc(&mut self) -> FH1_F0_CBC_W<'_>

Bit 3

pub fn fh1_f1_cbc(&mut self) -> FH1_F1_CBC_W<'_>

Bit 2

pub fn fh1_f2_cbc(&mut self) -> FH1_F2_CBC_W<'_>

Bit 1

pub fn fh1_sw_cbc(&mut self) -> FH1_SW_CBC_W<'_>

Bit 0

impl W<u32, Reg<u32, _FH1_CFG1>>

pub fn fh1_force_ost(&mut self) -> FH1_FORCE_OST_W<'_>

Bit 4

pub fn fh1_force_cbc(&mut self) -> FH1_FORCE_CBC_W<'_>

Bit 3

pub fn fh1_cbcpulse(&mut self) -> FH1_CBCPULSE_W<'_>

Bits 1:2

pub fn fh1_clr_ost(&mut self) -> FH1_CLR_OST_W<'_>

Bit 0

impl W<u32, Reg<u32, _FH1_STATUS>>

pub fn fh1_ost_on(&mut self) -> FH1_OST_ON_W<'_>

Bit 1

pub fn fh1_cbc_on(&mut self) -> FH1_CBC_ON_W<'_>

Bit 0

impl W<u32, Reg<u32, _GEN2_STMP_CFG>>

pub fn gen2_b_shdw_full(&mut self) -> GEN2_B_SHDW_FULL_W<'_>

Bit 9

pub fn gen2_a_shdw_full(&mut self) -> GEN2_A_SHDW_FULL_W<'_>

Bit 8

pub fn gen2_b_upmethod(&mut self) -> GEN2_B_UPMETHOD_W<'_>

Bits 4:7

pub fn gen2_a_upmethod(&mut self) -> GEN2_A_UPMETHOD_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _GEN2_TSTMP_A>>

pub fn gen2_a(&mut self) -> GEN2_A_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _GEN2_TSTMP_B>>

pub fn gen2_b(&mut self) -> GEN2_B_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _GEN2_CFG0>>

pub fn gen2_t1_sel(&mut self) -> GEN2_T1_SEL_W<'_>

Bits 7:9

pub fn gen2_t0_sel(&mut self) -> GEN2_T0_SEL_W<'_>

Bits 4:6

pub fn gen2_cfg_upmethod(&mut self) -> GEN2_CFG_UPMETHOD_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _GEN2_FORCE>>

pub fn gen2_b_nciforce_mode(&mut self) -> GEN2_B_NCIFORCE_MODE_W<'_>

Bits 14:15

pub fn gen2_b_nciforce(&mut self) -> GEN2_B_NCIFORCE_W<'_>

Bit 13

pub fn gen2_a_nciforce_mode(&mut self) -> GEN2_A_NCIFORCE_MODE_W<'_>

Bits 11:12

pub fn gen2_a_nciforce(&mut self) -> GEN2_A_NCIFORCE_W<'_>

Bit 10

pub fn gen2_b_cntuforce_mode(&mut self) -> GEN2_B_CNTUFORCE_MODE_W<'_>

Bits 8:9

pub fn gen2_a_cntuforce_mode(&mut self) -> GEN2_A_CNTUFORCE_MODE_W<'_>

Bits 6:7

pub fn gen2_cntuforce_upmethod(&mut self) -> GEN2_CNTUFORCE_UPMETHOD_W<'_>

Bits 0:5

impl W<u32, Reg<u32, _GEN2_A>>

pub fn gen2_a_dt1(&mut self) -> GEN2_A_DT1_W<'_>

Bits 22:23

pub fn gen2_a_dt0(&mut self) -> GEN2_A_DT0_W<'_>

Bits 20:21

pub fn gen2_a_dteb(&mut self) -> GEN2_A_DTEB_W<'_>

Bits 18:19

pub fn gen2_a_dtea(&mut self) -> GEN2_A_DTEA_W<'_>

Bits 16:17

pub fn gen2_a_dtep(&mut self) -> GEN2_A_DTEP_W<'_>

Bits 14:15

pub fn gen2_a_dtez(&mut self) -> GEN2_A_DTEZ_W<'_>

Bits 12:13

pub fn gen2_a_ut1(&mut self) -> GEN2_A_UT1_W<'_>

Bits 10:11

pub fn gen2_a_ut0(&mut self) -> GEN2_A_UT0_W<'_>

Bits 8:9

pub fn gen2_a_uteb(&mut self) -> GEN2_A_UTEB_W<'_>

Bits 6:7

pub fn gen2_a_utea(&mut self) -> GEN2_A_UTEA_W<'_>

Bits 4:5

pub fn gen2_a_utep(&mut self) -> GEN2_A_UTEP_W<'_>

Bits 2:3

pub fn gen2_a_utez(&mut self) -> GEN2_A_UTEZ_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _GEN2_B>>

pub fn gen2_b_dt1(&mut self) -> GEN2_B_DT1_W<'_>

Bits 22:23

pub fn gen2_b_dt0(&mut self) -> GEN2_B_DT0_W<'_>

Bits 20:21

pub fn gen2_b_dteb(&mut self) -> GEN2_B_DTEB_W<'_>

Bits 18:19

pub fn gen2_b_dtea(&mut self) -> GEN2_B_DTEA_W<'_>

Bits 16:17

pub fn gen2_b_dtep(&mut self) -> GEN2_B_DTEP_W<'_>

Bits 14:15

pub fn gen2_b_dtez(&mut self) -> GEN2_B_DTEZ_W<'_>

Bits 12:13

pub fn gen2_b_ut1(&mut self) -> GEN2_B_UT1_W<'_>

Bits 10:11

pub fn gen2_b_ut0(&mut self) -> GEN2_B_UT0_W<'_>

Bits 8:9

pub fn gen2_b_uteb(&mut self) -> GEN2_B_UTEB_W<'_>

Bits 6:7

pub fn gen2_b_utea(&mut self) -> GEN2_B_UTEA_W<'_>

Bits 4:5

pub fn gen2_b_utep(&mut self) -> GEN2_B_UTEP_W<'_>

Bits 2:3

pub fn gen2_b_utez(&mut self) -> GEN2_B_UTEZ_W<'_>

Bits 0:1

impl W<u32, Reg<u32, _DT2_CFG>>

pub fn dt2_clk_sel(&mut self) -> DT2_CLK_SEL_W<'_>

Bit 17

pub fn dt2_b_outbypass(&mut self) -> DT2_B_OUTBYPASS_W<'_>

Bit 16

pub fn dt2_a_outbypass(&mut self) -> DT2_A_OUTBYPASS_W<'_>

Bit 15

pub fn dt2_fed_outinvert(&mut self) -> DT2_FED_OUTINVERT_W<'_>

Bit 14

pub fn dt2_red_outinvert(&mut self) -> DT2_RED_OUTINVERT_W<'_>

Bit 13

pub fn dt2_fed_insel(&mut self) -> DT2_FED_INSEL_W<'_>

Bit 12

pub fn dt2_red_insel(&mut self) -> DT2_RED_INSEL_W<'_>

Bit 11

pub fn dt2_b_outswap(&mut self) -> DT2_B_OUTSWAP_W<'_>

Bit 10

pub fn dt2_a_outswap(&mut self) -> DT2_A_OUTSWAP_W<'_>

Bit 9

pub fn dt2_deb_mode(&mut self) -> DT2_DEB_MODE_W<'_>

Bit 8

pub fn dt2_red_upmethod(&mut self) -> DT2_RED_UPMETHOD_W<'_>

Bits 4:7

pub fn dt2_fed_upmethod(&mut self) -> DT2_FED_UPMETHOD_W<'_>

Bits 0:3

impl W<u32, Reg<u32, _DT2_FED_CFG>>

pub fn dt2_fed(&mut self) -> DT2_FED_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _DT2_RED_CFG>>

pub fn dt2_red(&mut self) -> DT2_RED_W<'_>

Bits 0:15

impl W<u32, Reg<u32, _CARRIER2_CFG>>

pub fn carrier2_in_invert(&mut self) -> CARRIER2_IN_INVERT_W<'_>

Bit 13

pub fn carrier2_out_invert(&mut self) -> CARRIER2_OUT_INVERT_W<'_>

Bit 12

pub fn carrier2_oshwth(&mut self) -> CARRIER2_OSHWTH_W<'_>

Bits 8:11

pub fn carrier2_duty(&mut self) -> CARRIER2_DUTY_W<'_>

Bits 5:7

pub fn carrier2_prescale(&mut self) -> CARRIER2_PRESCALE_W<'_>

Bits 1:4

pub fn carrier2_en(&mut self) -> CARRIER2_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _FH2_CFG0>>

pub fn fh2_b_ost_u(&mut self) -> FH2_B_OST_U_W<'_>

Bits 22:23

pub fn fh2_b_ost_d(&mut self) -> FH2_B_OST_D_W<'_>

Bits 20:21

pub fn fh2_b_cbc_u(&mut self) -> FH2_B_CBC_U_W<'_>

Bits 18:19

pub fn fh2_b_cbc_d(&mut self) -> FH2_B_CBC_D_W<'_>

Bits 16:17

pub fn fh2_a_ost_u(&mut self) -> FH2_A_OST_U_W<'_>

Bits 14:15

pub fn fh2_a_ost_d(&mut self) -> FH2_A_OST_D_W<'_>

Bits 12:13

pub fn fh2_a_cbc_u(&mut self) -> FH2_A_CBC_U_W<'_>

Bits 10:11

pub fn fh2_a_cbc_d(&mut self) -> FH2_A_CBC_D_W<'_>

Bits 8:9

pub fn fh2_f0_ost(&mut self) -> FH2_F0_OST_W<'_>

Bit 7

pub fn fh2_f1_ost(&mut self) -> FH2_F1_OST_W<'_>

Bit 6

pub fn fh2_f2_ost(&mut self) -> FH2_F2_OST_W<'_>

Bit 5

pub fn fh2_sw_ost(&mut self) -> FH2_SW_OST_W<'_>

Bit 4

pub fn fh2_f0_cbc(&mut self) -> FH2_F0_CBC_W<'_>

Bit 3

pub fn fh2_f1_cbc(&mut self) -> FH2_F1_CBC_W<'_>

Bit 2

pub fn fh2_f2_cbc(&mut self) -> FH2_F2_CBC_W<'_>

Bit 1

pub fn fh2_sw_cbc(&mut self) -> FH2_SW_CBC_W<'_>

Bit 0

impl W<u32, Reg<u32, _FH2_CFG1>>

pub fn fh2_force_ost(&mut self) -> FH2_FORCE_OST_W<'_>

Bit 4

pub fn fh2_force_cbc(&mut self) -> FH2_FORCE_CBC_W<'_>

Bit 3

pub fn fh2_cbcpulse(&mut self) -> FH2_CBCPULSE_W<'_>

Bits 1:2

pub fn fh2_clr_ost(&mut self) -> FH2_CLR_OST_W<'_>

Bit 0

impl W<u32, Reg<u32, _FH2_STATUS>>

pub fn fh2_ost_on(&mut self) -> FH2_OST_ON_W<'_>

Bit 1

pub fn fh2_cbc_on(&mut self) -> FH2_CBC_ON_W<'_>

Bit 0

impl W<u32, Reg<u32, _FAULT_DETECT>>

pub fn event_f2(&mut self) -> EVENT_F2_W<'_>

Bit 8

pub fn event_f1(&mut self) -> EVENT_F1_W<'_>

Bit 7

pub fn event_f0(&mut self) -> EVENT_F0_W<'_>

Bit 6

pub fn f2_pole(&mut self) -> F2_POLE_W<'_>

Bit 5

pub fn f1_pole(&mut self) -> F1_POLE_W<'_>

Bit 4

pub fn f0_pole(&mut self) -> F0_POLE_W<'_>

Bit 3

pub fn f2_en(&mut self) -> F2_EN_W<'_>

Bit 2

pub fn f1_en(&mut self) -> F1_EN_W<'_>

Bit 1

pub fn f0_en(&mut self) -> F0_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _CAP_TIMER_CFG>>

pub fn cap_sync_sw(&mut self) -> CAP_SYNC_SW_W<'_>

Bit 5

pub fn cap_synci_sel(&mut self) -> CAP_SYNCI_SEL_W<'_>

Bits 2:4

pub fn cap_synci_en(&mut self) -> CAP_SYNCI_EN_W<'_>

Bit 1

pub fn cap_timer_en(&mut self) -> CAP_TIMER_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _CAP_TIMER_PHASE>>

pub fn cap_phase(&mut self) -> CAP_PHASE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CAP_CH0_CFG>>

pub fn cap0_sw(&mut self) -> CAP0_SW_W<'_>

Bit 12

pub fn cap0_in_invert(&mut self) -> CAP0_IN_INVERT_W<'_>

Bit 11

pub fn cap0_prescale(&mut self) -> CAP0_PRESCALE_W<'_>

Bits 3:10

pub fn cap0_mode(&mut self) -> CAP0_MODE_W<'_>

Bits 1:2

pub fn cap0_en(&mut self) -> CAP0_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _CAP_CH1_CFG>>

pub fn cap1_sw(&mut self) -> CAP1_SW_W<'_>

Bit 12

pub fn cap1_in_invert(&mut self) -> CAP1_IN_INVERT_W<'_>

Bit 11

pub fn cap1_prescale(&mut self) -> CAP1_PRESCALE_W<'_>

Bits 3:10

pub fn cap1_mode(&mut self) -> CAP1_MODE_W<'_>

Bits 1:2

pub fn cap1_en(&mut self) -> CAP1_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _CAP_CH2_CFG>>

pub fn cap2_sw(&mut self) -> CAP2_SW_W<'_>

Bit 12

pub fn cap2_in_invert(&mut self) -> CAP2_IN_INVERT_W<'_>

Bit 11

pub fn cap2_prescale(&mut self) -> CAP2_PRESCALE_W<'_>

Bits 3:10

pub fn cap2_mode(&mut self) -> CAP2_MODE_W<'_>

Bits 1:2

pub fn cap2_en(&mut self) -> CAP2_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _CAP_CH0>>

pub fn cap0_value(&mut self) -> CAP0_VALUE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CAP_CH1>>

pub fn cap1_value(&mut self) -> CAP1_VALUE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CAP_CH2>>

pub fn cap2_value(&mut self) -> CAP2_VALUE_W<'_>

Bits 0:31

impl W<u32, Reg<u32, _CAP_STATUS>>

pub fn cap2_edge(&mut self) -> CAP2_EDGE_W<'_>

Bit 2

pub fn cap1_edge(&mut self) -> CAP1_EDGE_W<'_>

Bit 1

pub fn cap0_edge(&mut self) -> CAP0_EDGE_W<'_>

Bit 0

impl W<u32, Reg<u32, _UPDATE_CFG>>

pub fn op2_force_up(&mut self) -> OP2_FORCE_UP_W<'_>

Bit 7

pub fn op2_up_en(&mut self) -> OP2_UP_EN_W<'_>

Bit 6

pub fn op1_force_up(&mut self) -> OP1_FORCE_UP_W<'_>

Bit 5

pub fn op1_up_en(&mut self) -> OP1_UP_EN_W<'_>

Bit 4

pub fn op0_force_up(&mut self) -> OP0_FORCE_UP_W<'_>

Bit 3

pub fn op0_up_en(&mut self) -> OP0_UP_EN_W<'_>

Bit 2

pub fn global_force_up(&mut self) -> GLOBAL_FORCE_UP_W<'_>

Bit 1

pub fn global_up_en(&mut self) -> GLOBAL_UP_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _MCMCPWM_INT_ENA_MCPWM>>

pub fn cap2_int_ena(&mut self) -> CAP2_INT_ENA_W<'_>

Bit 29

pub fn cap1_int_ena(&mut self) -> CAP1_INT_ENA_W<'_>

Bit 28

pub fn cap0_int_ena(&mut self) -> CAP0_INT_ENA_W<'_>

Bit 27

pub fn fh2_ost_int_ena(&mut self) -> FH2_OST_INT_ENA_W<'_>

Bit 26

pub fn fh1_ost_int_ena(&mut self) -> FH1_OST_INT_ENA_W<'_>

Bit 25

pub fn fh0_ost_int_ena(&mut self) -> FH0_OST_INT_ENA_W<'_>

Bit 24

pub fn fh2_cbc_int_ena(&mut self) -> FH2_CBC_INT_ENA_W<'_>

Bit 23

pub fn fh1_cbc_int_ena(&mut self) -> FH1_CBC_INT_ENA_W<'_>

Bit 22

pub fn fh0_cbc_int_ena(&mut self) -> FH0_CBC_INT_ENA_W<'_>

Bit 21

pub fn op2_teb_int_ena(&mut self) -> OP2_TEB_INT_ENA_W<'_>

Bit 20

pub fn op1_teb_int_ena(&mut self) -> OP1_TEB_INT_ENA_W<'_>

Bit 19

pub fn op0_teb_int_ena(&mut self) -> OP0_TEB_INT_ENA_W<'_>

Bit 18

pub fn op2_tea_int_ena(&mut self) -> OP2_TEA_INT_ENA_W<'_>

Bit 17

pub fn op1_tea_int_ena(&mut self) -> OP1_TEA_INT_ENA_W<'_>

Bit 16

pub fn op0_tea_int_ena(&mut self) -> OP0_TEA_INT_ENA_W<'_>

Bit 15

pub fn fault2_clr_int_ena(&mut self) -> FAULT2_CLR_INT_ENA_W<'_>

Bit 14

pub fn fault1_clr_int_ena(&mut self) -> FAULT1_CLR_INT_ENA_W<'_>

Bit 13

pub fn fault0_clr_int_ena(&mut self) -> FAULT0_CLR_INT_ENA_W<'_>

Bit 12

pub fn fault2_int_ena(&mut self) -> FAULT2_INT_ENA_W<'_>

Bit 11

pub fn fault1_int_ena(&mut self) -> FAULT1_INT_ENA_W<'_>

Bit 10

pub fn fault0_int_ena(&mut self) -> FAULT0_INT_ENA_W<'_>

Bit 9

pub fn timer2_tep_int_ena(&mut self) -> TIMER2_TEP_INT_ENA_W<'_>

Bit 8

pub fn timer1_tep_int_ena(&mut self) -> TIMER1_TEP_INT_ENA_W<'_>

Bit 7

pub fn timer0_tep_int_ena(&mut self) -> TIMER0_TEP_INT_ENA_W<'_>

Bit 6

pub fn timer2_tez_int_ena(&mut self) -> TIMER2_TEZ_INT_ENA_W<'_>

Bit 5

pub fn timer1_tez_int_ena(&mut self) -> TIMER1_TEZ_INT_ENA_W<'_>

Bit 4

pub fn timer0_tez_int_ena(&mut self) -> TIMER0_TEZ_INT_ENA_W<'_>

Bit 3

pub fn timer2_stop_int_ena(&mut self) -> TIMER2_STOP_INT_ENA_W<'_>

Bit 2

pub fn timer1_stop_int_ena(&mut self) -> TIMER1_STOP_INT_ENA_W<'_>

Bit 1

pub fn timer0_stop_int_ena(&mut self) -> TIMER0_STOP_INT_ENA_W<'_>

Bit 0

impl W<u32, Reg<u32, _MCMCPWM_INT_RAW_MCPWM>>

pub fn cap2_int_raw(&mut self) -> CAP2_INT_RAW_W<'_>

Bit 29

pub fn cap1_int_raw(&mut self) -> CAP1_INT_RAW_W<'_>

Bit 28

pub fn cap0_int_raw(&mut self) -> CAP0_INT_RAW_W<'_>

Bit 27

pub fn fh2_ost_int_raw(&mut self) -> FH2_OST_INT_RAW_W<'_>

Bit 26

pub fn fh1_ost_int_raw(&mut self) -> FH1_OST_INT_RAW_W<'_>

Bit 25

pub fn fh0_ost_int_raw(&mut self) -> FH0_OST_INT_RAW_W<'_>

Bit 24

pub fn fh2_cbc_int_raw(&mut self) -> FH2_CBC_INT_RAW_W<'_>

Bit 23

pub fn fh1_cbc_int_raw(&mut self) -> FH1_CBC_INT_RAW_W<'_>

Bit 22

pub fn fh0_cbc_int_raw(&mut self) -> FH0_CBC_INT_RAW_W<'_>

Bit 21

pub fn op2_teb_int_raw(&mut self) -> OP2_TEB_INT_RAW_W<'_>

Bit 20

pub fn op1_teb_int_raw(&mut self) -> OP1_TEB_INT_RAW_W<'_>

Bit 19

pub fn op0_teb_int_raw(&mut self) -> OP0_TEB_INT_RAW_W<'_>

Bit 18

pub fn op2_tea_int_raw(&mut self) -> OP2_TEA_INT_RAW_W<'_>

Bit 17

pub fn op1_tea_int_raw(&mut self) -> OP1_TEA_INT_RAW_W<'_>

Bit 16

pub fn op0_tea_int_raw(&mut self) -> OP0_TEA_INT_RAW_W<'_>

Bit 15

pub fn fault2_clr_int_raw(&mut self) -> FAULT2_CLR_INT_RAW_W<'_>

Bit 14

pub fn fault1_clr_int_raw(&mut self) -> FAULT1_CLR_INT_RAW_W<'_>

Bit 13

pub fn fault0_clr_int_raw(&mut self) -> FAULT0_CLR_INT_RAW_W<'_>

Bit 12

pub fn fault2_int_raw(&mut self) -> FAULT2_INT_RAW_W<'_>

Bit 11

pub fn fault1_int_raw(&mut self) -> FAULT1_INT_RAW_W<'_>

Bit 10

pub fn fault0_int_raw(&mut self) -> FAULT0_INT_RAW_W<'_>

Bit 9

pub fn timer2_tep_int_raw(&mut self) -> TIMER2_TEP_INT_RAW_W<'_>

Bit 8

pub fn timer1_tep_int_raw(&mut self) -> TIMER1_TEP_INT_RAW_W<'_>

Bit 7

pub fn timer0_tep_int_raw(&mut self) -> TIMER0_TEP_INT_RAW_W<'_>

Bit 6

pub fn timer2_tez_int_raw(&mut self) -> TIMER2_TEZ_INT_RAW_W<'_>

Bit 5

pub fn timer1_tez_int_raw(&mut self) -> TIMER1_TEZ_INT_RAW_W<'_>

Bit 4

pub fn timer0_tez_int_raw(&mut self) -> TIMER0_TEZ_INT_RAW_W<'_>

Bit 3

pub fn timer2_stop_int_raw(&mut self) -> TIMER2_STOP_INT_RAW_W<'_>

Bit 2

pub fn timer1_stop_int_raw(&mut self) -> TIMER1_STOP_INT_RAW_W<'_>

Bit 1

pub fn timer0_stop_int_raw(&mut self) -> TIMER0_STOP_INT_RAW_W<'_>

Bit 0

impl W<u32, Reg<u32, _MCMCPWM_INT_ST_MCPWM>>

pub fn cap2_int_st(&mut self) -> CAP2_INT_ST_W<'_>

Bit 29

pub fn cap1_int_st(&mut self) -> CAP1_INT_ST_W<'_>

Bit 28

pub fn cap0_int_st(&mut self) -> CAP0_INT_ST_W<'_>

Bit 27

pub fn fh2_ost_int_st(&mut self) -> FH2_OST_INT_ST_W<'_>

Bit 26

pub fn fh1_ost_int_st(&mut self) -> FH1_OST_INT_ST_W<'_>

Bit 25

pub fn fh0_ost_int_st(&mut self) -> FH0_OST_INT_ST_W<'_>

Bit 24

pub fn fh2_cbc_int_st(&mut self) -> FH2_CBC_INT_ST_W<'_>

Bit 23

pub fn fh1_cbc_int_st(&mut self) -> FH1_CBC_INT_ST_W<'_>

Bit 22

pub fn fh0_cbc_int_st(&mut self) -> FH0_CBC_INT_ST_W<'_>

Bit 21

pub fn op2_teb_int_st(&mut self) -> OP2_TEB_INT_ST_W<'_>

Bit 20

pub fn op1_teb_int_st(&mut self) -> OP1_TEB_INT_ST_W<'_>

Bit 19

pub fn op0_teb_int_st(&mut self) -> OP0_TEB_INT_ST_W<'_>

Bit 18

pub fn op2_tea_int_st(&mut self) -> OP2_TEA_INT_ST_W<'_>

Bit 17

pub fn op1_tea_int_st(&mut self) -> OP1_TEA_INT_ST_W<'_>

Bit 16

pub fn op0_tea_int_st(&mut self) -> OP0_TEA_INT_ST_W<'_>

Bit 15

pub fn fault2_clr_int_st(&mut self) -> FAULT2_CLR_INT_ST_W<'_>

Bit 14

pub fn fault1_clr_int_st(&mut self) -> FAULT1_CLR_INT_ST_W<'_>

Bit 13

pub fn fault0_clr_int_st(&mut self) -> FAULT0_CLR_INT_ST_W<'_>

Bit 12

pub fn fault2_int_st(&mut self) -> FAULT2_INT_ST_W<'_>

Bit 11

pub fn fault1_int_st(&mut self) -> FAULT1_INT_ST_W<'_>

Bit 10

pub fn fault0_int_st(&mut self) -> FAULT0_INT_ST_W<'_>

Bit 9

pub fn timer2_tep_int_st(&mut self) -> TIMER2_TEP_INT_ST_W<'_>

Bit 8

pub fn timer1_tep_int_st(&mut self) -> TIMER1_TEP_INT_ST_W<'_>

Bit 7

pub fn timer0_tep_int_st(&mut self) -> TIMER0_TEP_INT_ST_W<'_>

Bit 6

pub fn timer2_tez_int_st(&mut self) -> TIMER2_TEZ_INT_ST_W<'_>

Bit 5

pub fn timer1_tez_int_st(&mut self) -> TIMER1_TEZ_INT_ST_W<'_>

Bit 4

pub fn timer0_tez_int_st(&mut self) -> TIMER0_TEZ_INT_ST_W<'_>

Bit 3

pub fn timer2_stop_int_st(&mut self) -> TIMER2_STOP_INT_ST_W<'_>

Bit 2

pub fn timer1_stop_int_st(&mut self) -> TIMER1_STOP_INT_ST_W<'_>

Bit 1

pub fn timer0_stop_int_st(&mut self) -> TIMER0_STOP_INT_ST_W<'_>

Bit 0

impl W<u32, Reg<u32, _MCMCPWM_INT_CLR_MCPWM>>

pub fn cap2_int_clr(&mut self) -> CAP2_INT_CLR_W<'_>

Bit 29

pub fn cap1_int_clr(&mut self) -> CAP1_INT_CLR_W<'_>

Bit 28

pub fn cap0_int_clr(&mut self) -> CAP0_INT_CLR_W<'_>

Bit 27

pub fn fh2_ost_int_clr(&mut self) -> FH2_OST_INT_CLR_W<'_>

Bit 26

pub fn fh1_ost_int_clr(&mut self) -> FH1_OST_INT_CLR_W<'_>

Bit 25

pub fn fh0_ost_int_clr(&mut self) -> FH0_OST_INT_CLR_W<'_>

Bit 24

pub fn fh2_cbc_int_clr(&mut self) -> FH2_CBC_INT_CLR_W<'_>

Bit 23

pub fn fh1_cbc_int_clr(&mut self) -> FH1_CBC_INT_CLR_W<'_>

Bit 22

pub fn fh0_cbc_int_clr(&mut self) -> FH0_CBC_INT_CLR_W<'_>

Bit 21

pub fn op2_teb_int_clr(&mut self) -> OP2_TEB_INT_CLR_W<'_>

Bit 20

pub fn op1_teb_int_clr(&mut self) -> OP1_TEB_INT_CLR_W<'_>

Bit 19

pub fn op0_teb_int_clr(&mut self) -> OP0_TEB_INT_CLR_W<'_>

Bit 18

pub fn op2_tea_int_clr(&mut self) -> OP2_TEA_INT_CLR_W<'_>

Bit 17

pub fn op1_tea_int_clr(&mut self) -> OP1_TEA_INT_CLR_W<'_>

Bit 16

pub fn op0_tea_int_clr(&mut self) -> OP0_TEA_INT_CLR_W<'_>

Bit 15

pub fn fault2_clr_int_clr(&mut self) -> FAULT2_CLR_INT_CLR_W<'_>

Bit 14

pub fn fault1_clr_int_clr(&mut self) -> FAULT1_CLR_INT_CLR_W<'_>

Bit 13

pub fn fault0_clr_int_clr(&mut self) -> FAULT0_CLR_INT_CLR_W<'_>

Bit 12

pub fn fault2_int_clr(&mut self) -> FAULT2_INT_CLR_W<'_>

Bit 11

pub fn fault1_int_clr(&mut self) -> FAULT1_INT_CLR_W<'_>

Bit 10

pub fn fault0_int_clr(&mut self) -> FAULT0_INT_CLR_W<'_>

Bit 9

pub fn timer2_tep_int_clr(&mut self) -> TIMER2_TEP_INT_CLR_W<'_>

Bit 8

pub fn timer1_tep_int_clr(&mut self) -> TIMER1_TEP_INT_CLR_W<'_>

Bit 7

pub fn timer0_tep_int_clr(&mut self) -> TIMER0_TEP_INT_CLR_W<'_>

Bit 6

pub fn timer2_tez_int_clr(&mut self) -> TIMER2_TEZ_INT_CLR_W<'_>

Bit 5

pub fn timer1_tez_int_clr(&mut self) -> TIMER1_TEZ_INT_CLR_W<'_>

Bit 4

pub fn timer0_tez_int_clr(&mut self) -> TIMER0_TEZ_INT_CLR_W<'_>

Bit 3

pub fn timer2_stop_int_clr(&mut self) -> TIMER2_STOP_INT_CLR_W<'_>

Bit 2

pub fn timer1_stop_int_clr(&mut self) -> TIMER1_STOP_INT_CLR_W<'_>

Bit 1

pub fn timer0_stop_int_clr(&mut self) -> TIMER0_STOP_INT_CLR_W<'_>

Bit 0

impl W<u32, Reg<u32, _CLK>>

pub fn clk_en(&mut self) -> CLK_EN_W<'_>

Bit 0

impl W<u32, Reg<u32, _VERSION>>

pub fn date(&mut self) -> DATE_W<'_>

Bits 0:27