[−][src]Struct esp32::generic::R

pub struct R<U, T> { /* fields omitted */ }

Register/field reader.

Result of the read methods of registers. Also used as a closure argument in the modify method.

Implementations

`impl<U, T> R<U, T> where U: Copy,` [src]

`pub fn bits(&self) -> U`[src]

Reads raw bits from register/field.

`impl<FI> R<bool, FI>`[src]

`pub fn bit(&self) -> bool`[src]

Value of the field as raw bits.

`pub fn bit_is_clear(&self) -> bool`[src]

Returns true if the bit is clear (0).

`pub fn bit_is_set(&self) -> bool`[src]

Returns true if the bit is set (1).

`impl R<u32, Reg<u32, _IDLE>>`[src]

`pub fn idle(&self) -> IDLE_R`[src]

Bit 0 - 0 when AES is busy, 1 otherwise

`impl R<u8, MODE_A>`[src]

`pub fn variant(&self) -> Variant<u8, MODE_A>`[src]

Get enumerated values variant

`pub fn is_aes128_encrypt(&self) -> bool`[src]

Checks if the value of the field is AES128_ENCRYPT

`pub fn is_aes192_encrypt(&self) -> bool`[src]

Checks if the value of the field is AES192_ENCRYPT

`pub fn is_aes256_encrypt(&self) -> bool`[src]

Checks if the value of the field is AES256_ENCRYPT

`pub fn is_aes128_decrypt(&self) -> bool`[src]

Checks if the value of the field is AES128_DECRYPT

`pub fn is_aes192_decrypt(&self) -> bool`[src]

Checks if the value of the field is AES192_DECRYPT

`pub fn is_aes256_decrypt(&self) -> bool`[src]

Checks if the value of the field is AES256_DECRYPT

`impl R<u32, Reg<u32, _MODE>>`[src]

`pub fn mode(&self) -> MODE_R`[src]

Bits 0:2 - Selects AES accelerator mode

`impl R<u32, Reg<u32, _ENDIAN>>`[src]

`pub fn mode(&self) -> MODE_R`[src]

Bits 0:5 - Select AES endian mode

`impl R<u32, Reg<u32, _CFG_DATA0>>`[src]

`pub fn device_id_fn1(&self) -> DEVICE_ID_FN1_R`[src]

Bits 16:31

`pub fn user_id_fn1(&self) -> USER_ID_FN1_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _CFG_DATA1>>`[src]

`pub fn sdio20_conf1(&self) -> SDIO20_CONF1_R`[src]

Bits 29:31

`pub fn func2_eps(&self) -> FUNC2_EPS_R`[src]

Bit 28

`pub fn sdio_ver(&self) -> SDIO_VER_R`[src]

Bits 16:27

`pub fn sdio20_conf0(&self) -> SDIO20_CONF0_R`[src]

Bits 12:15

`pub fn ioenable1(&self) -> IOENABLE1_R`[src]

Bit 11

`pub fn emp(&self) -> EMP_R`[src]

Bit 10

`pub fn func1_eps(&self) -> FUNC1_EPS_R`[src]

Bit 9

`pub fn cd_disable(&self) -> CD_DISABLE_R`[src]

Bit 8

`pub fn ioenable2(&self) -> IOENABLE2_R`[src]

Bit 7

`pub fn sdio_int_mask(&self) -> SDIO_INT_MASK_R`[src]

Bit 6

`pub fn sdio_ioready2(&self) -> SDIO_IOREADY2_R`[src]

Bit 5

`pub fn sdio_cd_enable(&self) -> SDIO_CD_ENABLE_R`[src]

Bit 4

`pub fn highspeed_mode(&self) -> HIGHSPEED_MODE_R`[src]

Bit 3

`pub fn highspeed_enable(&self) -> HIGHSPEED_ENABLE_R`[src]

Bit 2

`pub fn sdio_ioready1(&self) -> SDIO_IOREADY1_R`[src]

Bit 1

`pub fn sdio_enable(&self) -> SDIO_ENABLE_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CFG_DATA7>>`[src]

`pub fn sdio_ioready0(&self) -> SDIO_IOREADY0_R`[src]

Bit 17

`pub fn sdio_rst(&self) -> SDIO_RST_R`[src]

Bit 16

`pub fn chip_state(&self) -> CHIP_STATE_R`[src]

`pub fn user_id_fn2(&self) -> USER_ID_FN2_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _DATE>>`[src]

`pub fn sdio_date(&self) -> SDIO_DATE_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _CMD>>`[src]

`pub fn flash_read(&self) -> FLASH_READ_R`[src]

Bit 31

`pub fn flash_wren(&self) -> FLASH_WREN_R`[src]

Bit 30

`pub fn flash_wrdi(&self) -> FLASH_WRDI_R`[src]

Bit 29

`pub fn flash_rdid(&self) -> FLASH_RDID_R`[src]

Bit 28

`pub fn flash_rdsr(&self) -> FLASH_RDSR_R`[src]

Bit 27

`pub fn flash_wrsr(&self) -> FLASH_WRSR_R`[src]

Bit 26

`pub fn flash_pp(&self) -> FLASH_PP_R`[src]

Bit 25

`pub fn flash_se(&self) -> FLASH_SE_R`[src]

Bit 24

`pub fn flash_be(&self) -> FLASH_BE_R`[src]

Bit 23

`pub fn flash_ce(&self) -> FLASH_CE_R`[src]

Bit 22

`pub fn flash_dp(&self) -> FLASH_DP_R`[src]

Bit 21

`pub fn flash_res(&self) -> FLASH_RES_R`[src]

Bit 20

`pub fn flash_hpm(&self) -> FLASH_HPM_R`[src]

Bit 19

`pub fn usr(&self) -> USR_R`[src]

Bit 18

`pub fn flash_pes(&self) -> FLASH_PES_R`[src]

Bit 17

`pub fn flash_per(&self) -> FLASH_PER_R`[src]

Bit 16

`impl R<u32, Reg<u32, _CTRL>>`[src]

`pub fn wr_bit_order(&self) -> WR_BIT_ORDER_R`[src]

Bit 26

`pub fn rd_bit_order(&self) -> RD_BIT_ORDER_R`[src]

Bit 25

`pub fn fread_qio(&self) -> FREAD_QIO_R`[src]

Bit 24

`pub fn fread_dio(&self) -> FREAD_DIO_R`[src]

Bit 23

`pub fn wrsr_2b(&self) -> WRSR_2B_R`[src]

Bit 22

`pub fn wp_reg(&self) -> WP_REG_R`[src]

Bit 21

`pub fn fread_quad(&self) -> FREAD_QUAD_R`[src]

Bit 20

`pub fn resandres(&self) -> RESANDRES_R`[src]

Bit 15

`pub fn fread_dual(&self) -> FREAD_DUAL_R`[src]

Bit 14

`pub fn fastrd_mode(&self) -> FASTRD_MODE_R`[src]

Bit 13

`pub fn wait_flash_idle_en(&self) -> WAIT_FLASH_IDLE_EN_R`[src]

Bit 12

`pub fn tx_crc_en(&self) -> TX_CRC_EN_R`[src]

Bit 11

`pub fn fcs_crc_en(&self) -> FCS_CRC_EN_R`[src]

Bit 10

`impl R<u32, Reg<u32, _CTRL1>>`[src]

`pub fn cs_hold_delay(&self) -> CS_HOLD_DELAY_R`[src]

Bits 28:31

`pub fn cs_hold_delay_res(&self) -> CS_HOLD_DELAY_RES_R`[src]

Bits 16:27

`impl R<u32, Reg<u32, _RD_STATUS>>`[src]

`pub fn status_ext(&self) -> STATUS_EXT_R`[src]

Bits 24:31

`pub fn wb_mode(&self) -> WB_MODE_R`[src]

Bits 16:23

`pub fn status(&self) -> STATUS_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _CTRL2>>`[src]

`pub fn cs_delay_num(&self) -> CS_DELAY_NUM_R`[src]

Bits 28:31

`pub fn cs_delay_mode(&self) -> CS_DELAY_MODE_R`[src]

Bits 26:27

`pub fn mosi_delay_num(&self) -> MOSI_DELAY_NUM_R`[src]

Bits 23:25

`pub fn mosi_delay_mode(&self) -> MOSI_DELAY_MODE_R`[src]

Bits 21:22

`pub fn miso_delay_num(&self) -> MISO_DELAY_NUM_R`[src]

Bits 18:20

`pub fn miso_delay_mode(&self) -> MISO_DELAY_MODE_R`[src]

Bits 16:17

`pub fn ck_out_high_mode(&self) -> CK_OUT_HIGH_MODE_R`[src]

Bits 12:15

`pub fn ck_out_low_mode(&self) -> CK_OUT_LOW_MODE_R`[src]

Bits 8:11

`pub fn hold_time(&self) -> HOLD_TIME_R`[src]

Bits 4:7

`pub fn setup_time(&self) -> SETUP_TIME_R`[src]

Bits 0:3

`impl R<u32, Reg<u32, _CLOCK>>`[src]

`pub fn clk_equ_sysclk(&self) -> CLK_EQU_SYSCLK_R`[src]

Bit 31

`pub fn clkdiv_pre(&self) -> CLKDIV_PRE_R`[src]

Bits 18:30

`pub fn clkcnt_n(&self) -> CLKCNT_N_R`[src]

Bits 12:17

`pub fn clkcnt_h(&self) -> CLKCNT_H_R`[src]

Bits 6:11

`pub fn clkcnt_l(&self) -> CLKCNT_L_R`[src]

Bits 0:5

`impl R<u32, Reg<u32, _USER>>`[src]

`pub fn usr_command(&self) -> USR_COMMAND_R`[src]

Bit 31

`pub fn usr_addr(&self) -> USR_ADDR_R`[src]

Bit 30

`pub fn usr_dummy(&self) -> USR_DUMMY_R`[src]

Bit 29

`pub fn usr_miso(&self) -> USR_MISO_R`[src]

Bit 28

`pub fn usr_mosi(&self) -> USR_MOSI_R`[src]

Bit 27

`pub fn usr_dummy_idle(&self) -> USR_DUMMY_IDLE_R`[src]

Bit 26

`pub fn usr_mosi_highpart(&self) -> USR_MOSI_HIGHPART_R`[src]

Bit 25

`pub fn usr_miso_highpart(&self) -> USR_MISO_HIGHPART_R`[src]

Bit 24

`pub fn usr_prep_hold(&self) -> USR_PREP_HOLD_R`[src]

Bit 23

`pub fn usr_cmd_hold(&self) -> USR_CMD_HOLD_R`[src]

Bit 22

`pub fn usr_addr_hold(&self) -> USR_ADDR_HOLD_R`[src]

Bit 21

`pub fn usr_dummy_hold(&self) -> USR_DUMMY_HOLD_R`[src]

Bit 20

`pub fn usr_din_hold(&self) -> USR_DIN_HOLD_R`[src]

Bit 19

`pub fn usr_dout_hold(&self) -> USR_DOUT_HOLD_R`[src]

Bit 18

`pub fn usr_hold_pol(&self) -> USR_HOLD_POL_R`[src]

Bit 17

`pub fn sio(&self) -> SIO_R`[src]

Bit 16

`pub fn fwrite_qio(&self) -> FWRITE_QIO_R`[src]

Bit 15

`pub fn fwrite_dio(&self) -> FWRITE_DIO_R`[src]

Bit 14

`pub fn fwrite_quad(&self) -> FWRITE_QUAD_R`[src]

Bit 13

`pub fn fwrite_dual(&self) -> FWRITE_DUAL_R`[src]

Bit 12

`pub fn wr_byte_order(&self) -> WR_BYTE_ORDER_R`[src]

Bit 11

`pub fn rd_byte_order(&self) -> RD_BYTE_ORDER_R`[src]

Bit 10

`pub fn ck_out_edge(&self) -> CK_OUT_EDGE_R`[src]

Bit 7

`pub fn ck_i_edge(&self) -> CK_I_EDGE_R`[src]

Bit 6

`pub fn cs_setup(&self) -> CS_SETUP_R`[src]

Bit 5

`pub fn cs_hold(&self) -> CS_HOLD_R`[src]

Bit 4

`pub fn doutdin(&self) -> DOUTDIN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _USER1>>`[src]

`pub fn usr_addr_bitlen(&self) -> USR_ADDR_BITLEN_R`[src]

Bits 26:31

`pub fn usr_dummy_cyclelen(&self) -> USR_DUMMY_CYCLELEN_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _USER2>>`[src]

`pub fn usr_command_bitlen(&self) -> USR_COMMAND_BITLEN_R`[src]

Bits 28:31

`pub fn usr_command_value(&self) -> USR_COMMAND_VALUE_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _MOSI_DLEN>>`[src]

`pub fn usr_mosi_dbitlen(&self) -> USR_MOSI_DBITLEN_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _MISO_DLEN>>`[src]

`pub fn usr_miso_dbitlen(&self) -> USR_MISO_DBITLEN_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _SLV_WR_STATUS>>`[src]

`pub fn slv_wr_st(&self) -> SLV_WR_ST_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _PIN>>`[src]

`pub fn cs_keep_active(&self) -> CS_KEEP_ACTIVE_R`[src]

Bit 30

`pub fn ck_idle_edge(&self) -> CK_IDLE_EDGE_R`[src]

Bit 29

`pub fn master_ck_sel(&self) -> MASTER_CK_SEL_R`[src]

Bits 11:13

`pub fn master_cs_pol(&self) -> MASTER_CS_POL_R`[src]

Bits 6:8

`pub fn ck_dis(&self) -> CK_DIS_R`[src]

Bit 5

`pub fn cs2_dis(&self) -> CS2_DIS_R`[src]

Bit 2

`pub fn cs1_dis(&self) -> CS1_DIS_R`[src]

Bit 1

`pub fn cs0_dis(&self) -> CS0_DIS_R`[src]

Bit 0

`impl R<u32, Reg<u32, _SLAVE>>`[src]

`pub fn sync_reset(&self) -> SYNC_RESET_R`[src]

Bit 31

`pub fn slave_mode(&self) -> SLAVE_MODE_R`[src]

Bit 30

`pub fn slv_wr_rd_buf_en(&self) -> SLV_WR_RD_BUF_EN_R`[src]

Bit 29

`pub fn slv_wr_rd_sta_en(&self) -> SLV_WR_RD_STA_EN_R`[src]

Bit 28

`pub fn slv_cmd_define(&self) -> SLV_CMD_DEFINE_R`[src]

Bit 27

`pub fn trans_cnt(&self) -> TRANS_CNT_R`[src]

Bits 23:26

`pub fn slv_last_state(&self) -> SLV_LAST_STATE_R`[src]

Bits 20:22

`pub fn slv_last_command(&self) -> SLV_LAST_COMMAND_R`[src]

Bits 17:19

`pub fn cs_i_mode(&self) -> CS_I_MODE_R`[src]

Bits 10:11

`pub fn int_en(&self) -> INT_EN_R`[src]

Bits 5:9

`pub fn trans_done(&self) -> TRANS_DONE_R`[src]

Bit 4

`pub fn slv_wr_sta_done(&self) -> SLV_WR_STA_DONE_R`[src]

Bit 3

`pub fn slv_rd_sta_done(&self) -> SLV_RD_STA_DONE_R`[src]

Bit 2

`pub fn slv_wr_buf_done(&self) -> SLV_WR_BUF_DONE_R`[src]

Bit 1

`pub fn slv_rd_buf_done(&self) -> SLV_RD_BUF_DONE_R`[src]

Bit 0

`impl R<u32, Reg<u32, _SLAVE1>>`[src]

`pub fn slv_status_bitlen(&self) -> SLV_STATUS_BITLEN_R`[src]

Bits 27:31

`pub fn slv_status_fast_en(&self) -> SLV_STATUS_FAST_EN_R`[src]

Bit 26

`pub fn slv_status_readback(&self) -> SLV_STATUS_READBACK_R`[src]

Bit 25

`pub fn slv_rd_addr_bitlen(&self) -> SLV_RD_ADDR_BITLEN_R`[src]

Bits 10:15

`pub fn slv_wr_addr_bitlen(&self) -> SLV_WR_ADDR_BITLEN_R`[src]

Bits 4:9

`pub fn slv_wrsta_dummy_en(&self) -> SLV_WRSTA_DUMMY_EN_R`[src]

Bit 3

`pub fn slv_rdsta_dummy_en(&self) -> SLV_RDSTA_DUMMY_EN_R`[src]

Bit 2

`pub fn slv_wrbuf_dummy_en(&self) -> SLV_WRBUF_DUMMY_EN_R`[src]

Bit 1

`pub fn slv_rdbuf_dummy_en(&self) -> SLV_RDBUF_DUMMY_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _SLAVE2>>`[src]

`pub fn slv_wrbuf_dummy_cyclelen(&self) -> SLV_WRBUF_DUMMY_CYCLELEN_R`[src]

Bits 24:31

`pub fn slv_rdbuf_dummy_cyclelen(&self) -> SLV_RDBUF_DUMMY_CYCLELEN_R`[src]

Bits 16:23

`pub fn slv_wrsta_dummy_cyclelen(&self) -> SLV_WRSTA_DUMMY_CYCLELEN_R`[src]

Bits 8:15

`pub fn slv_rdsta_dummy_cyclelen(&self) -> SLV_RDSTA_DUMMY_CYCLELEN_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _SLAVE3>>`[src]

`pub fn slv_wrsta_cmd_value(&self) -> SLV_WRSTA_CMD_VALUE_R`[src]

Bits 24:31

`pub fn slv_rdsta_cmd_value(&self) -> SLV_RDSTA_CMD_VALUE_R`[src]

Bits 16:23

`pub fn slv_wrbuf_cmd_value(&self) -> SLV_WRBUF_CMD_VALUE_R`[src]

Bits 8:15

`pub fn slv_rdbuf_cmd_value(&self) -> SLV_RDBUF_CMD_VALUE_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _SLV_WRBUF_DLEN>>`[src]

`pub fn slv_wrbuf_dbitlen(&self) -> SLV_WRBUF_DBITLEN_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _SLV_RDBUF_DLEN>>`[src]

`pub fn slv_rdbuf_dbitlen(&self) -> SLV_RDBUF_DBITLEN_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _CACHE_FCTRL>>`[src]

`pub fn cache_flash_pes_en(&self) -> CACHE_FLASH_PES_EN_R`[src]

Bit 3

`pub fn cache_flash_usr_cmd(&self) -> CACHE_FLASH_USR_CMD_R`[src]

Bit 2

`pub fn cache_usr_cmd_4byte(&self) -> CACHE_USR_CMD_4BYTE_R`[src]

Bit 1

`pub fn cache_req_en(&self) -> CACHE_REQ_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CACHE_SCTRL>>`[src]

`pub fn cache_sram_usr_wcmd(&self) -> CACHE_SRAM_USR_WCMD_R`[src]

Bit 28

`pub fn sram_addr_bitlen(&self) -> SRAM_ADDR_BITLEN_R`[src]

Bits 22:27

`pub fn sram_dummy_cyclelen(&self) -> SRAM_DUMMY_CYCLELEN_R`[src]

Bits 14:21

`pub fn sram_bytes_len(&self) -> SRAM_BYTES_LEN_R`[src]

Bits 6:13

`pub fn cache_sram_usr_rcmd(&self) -> CACHE_SRAM_USR_RCMD_R`[src]

Bit 5

`pub fn usr_rd_sram_dummy(&self) -> USR_RD_SRAM_DUMMY_R`[src]

Bit 4

`pub fn usr_wr_sram_dummy(&self) -> USR_WR_SRAM_DUMMY_R`[src]

Bit 3

`pub fn usr_sram_qio(&self) -> USR_SRAM_QIO_R`[src]

Bit 2

`pub fn usr_sram_dio(&self) -> USR_SRAM_DIO_R`[src]

Bit 1

`impl R<u32, Reg<u32, _SRAM_CMD>>`[src]

`pub fn sram_rstio(&self) -> SRAM_RSTIO_R`[src]

Bit 4

`pub fn sram_qio(&self) -> SRAM_QIO_R`[src]

Bit 1

`pub fn sram_dio(&self) -> SRAM_DIO_R`[src]

Bit 0

`impl R<u32, Reg<u32, _SRAM_DRD_CMD>>`[src]

`pub fn cache_sram_usr_rd_cmd_bitlen(&self) -> CACHE_SRAM_USR_RD_CMD_BITLEN_R`[src]

Bits 28:31

`pub fn cache_sram_usr_rd_cmd_value(&self) -> CACHE_SRAM_USR_RD_CMD_VALUE_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _SRAM_DWR_CMD>>`[src]

`pub fn cache_sram_usr_wr_cmd_bitlen(&self) -> CACHE_SRAM_USR_WR_CMD_BITLEN_R`[src]

Bits 28:31

`pub fn cache_sram_usr_wr_cmd_value(&self) -> CACHE_SRAM_USR_WR_CMD_VALUE_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _SLV_RD_BIT>>`[src]

`pub fn slv_rdata_bit(&self) -> SLV_RDATA_BIT_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _W>>`[src]

`pub fn buf(&self) -> BUF_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _TX_CRC>>`[src]

`pub fn tx_crc_data(&self) -> TX_CRC_DATA_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _EXT0>>`[src]

`pub fn t_pp_ena(&self) -> T_PP_ENA_R`[src]

Bit 31

`pub fn t_pp_shift(&self) -> T_PP_SHIFT_R`[src]

Bits 16:19

`pub fn t_pp_time(&self) -> T_PP_TIME_R`[src]

Bits 0:11

`impl R<u32, Reg<u32, _EXT1>>`[src]

`pub fn t_erase_ena(&self) -> T_ERASE_ENA_R`[src]

Bit 31

`pub fn t_erase_shift(&self) -> T_ERASE_SHIFT_R`[src]

Bits 16:19

`pub fn t_erase_time(&self) -> T_ERASE_TIME_R`[src]

Bits 0:11

`impl R<u32, Reg<u32, _EXT2>>`[src]

`pub fn st(&self) -> ST_R`[src]

Bits 0:2

`impl R<u32, Reg<u32, _EXT3>>`[src]

`pub fn int_hold_ena(&self) -> INT_HOLD_ENA_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _DMA_CONF>>`[src]

`pub fn dma_continue(&self) -> DMA_CONTINUE_R`[src]

Bit 16

`pub fn dma_tx_stop(&self) -> DMA_TX_STOP_R`[src]

Bit 15

`pub fn dma_rx_stop(&self) -> DMA_RX_STOP_R`[src]

Bit 14

`pub fn out_data_burst_en(&self) -> OUT_DATA_BURST_EN_R`[src]

Bit 12

`pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R`[src]

Bit 11

`pub fn outdscr_burst_en(&self) -> OUTDSCR_BURST_EN_R`[src]

Bit 10

`pub fn out_eof_mode(&self) -> OUT_EOF_MODE_R`[src]

Bit 9

`pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R`[src]

Bit 8

`pub fn out_loop_test(&self) -> OUT_LOOP_TEST_R`[src]

Bit 7

`pub fn in_loop_test(&self) -> IN_LOOP_TEST_R`[src]

Bit 6

`pub fn ahbm_rst(&self) -> AHBM_RST_R`[src]

Bit 5

`pub fn ahbm_fifo_rst(&self) -> AHBM_FIFO_RST_R`[src]

Bit 4

`pub fn out_rst(&self) -> OUT_RST_R`[src]

Bit 3

`pub fn in_rst(&self) -> IN_RST_R`[src]

Bit 2

`impl R<u32, Reg<u32, _DMA_OUT_LINK>>`[src]

`pub fn outlink_restart(&self) -> OUTLINK_RESTART_R`[src]

Bit 30

`pub fn outlink_start(&self) -> OUTLINK_START_R`[src]

Bit 29

`pub fn outlink_stop(&self) -> OUTLINK_STOP_R`[src]

Bit 28

`pub fn outlink_addr(&self) -> OUTLINK_ADDR_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _DMA_IN_LINK>>`[src]

`pub fn inlink_restart(&self) -> INLINK_RESTART_R`[src]

Bit 30

`pub fn inlink_start(&self) -> INLINK_START_R`[src]

Bit 29

`pub fn inlink_stop(&self) -> INLINK_STOP_R`[src]

Bit 28

`pub fn inlink_auto_ret(&self) -> INLINK_AUTO_RET_R`[src]

Bit 20

`pub fn inlink_addr(&self) -> INLINK_ADDR_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _DMA_STATUS>>`[src]

`pub fn dma_tx_en(&self) -> DMA_TX_EN_R`[src]

Bit 1

`pub fn dma_rx_en(&self) -> DMA_RX_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DMA_INT_ENA>>`[src]

`pub fn out_total_eof_int_ena(&self) -> OUT_TOTAL_EOF_INT_ENA_R`[src]

Bit 8

`pub fn out_eof_int_ena(&self) -> OUT_EOF_INT_ENA_R`[src]

Bit 7

`pub fn out_done_int_ena(&self) -> OUT_DONE_INT_ENA_R`[src]

Bit 6

`pub fn in_suc_eof_int_ena(&self) -> IN_SUC_EOF_INT_ENA_R`[src]

Bit 5

`pub fn in_err_eof_int_ena(&self) -> IN_ERR_EOF_INT_ENA_R`[src]

Bit 4

`pub fn in_done_int_ena(&self) -> IN_DONE_INT_ENA_R`[src]

Bit 3

`pub fn inlink_dscr_error_int_ena(&self) -> INLINK_DSCR_ERROR_INT_ENA_R`[src]

Bit 2

`pub fn outlink_dscr_error_int_ena(&self) -> OUTLINK_DSCR_ERROR_INT_ENA_R`[src]

Bit 1

`pub fn inlink_dscr_empty_int_ena(&self) -> INLINK_DSCR_EMPTY_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DMA_INT_RAW>>`[src]

`pub fn out_total_eof_int_raw(&self) -> OUT_TOTAL_EOF_INT_RAW_R`[src]

Bit 8

`pub fn out_eof_int_raw(&self) -> OUT_EOF_INT_RAW_R`[src]

Bit 7

`pub fn out_done_int_raw(&self) -> OUT_DONE_INT_RAW_R`[src]

Bit 6

`pub fn in_suc_eof_int_raw(&self) -> IN_SUC_EOF_INT_RAW_R`[src]

Bit 5

`pub fn in_err_eof_int_raw(&self) -> IN_ERR_EOF_INT_RAW_R`[src]

Bit 4

`pub fn in_done_int_raw(&self) -> IN_DONE_INT_RAW_R`[src]

Bit 3

`pub fn inlink_dscr_error_int_raw(&self) -> INLINK_DSCR_ERROR_INT_RAW_R`[src]

Bit 2

`pub fn outlink_dscr_error_int_raw(&self) -> OUTLINK_DSCR_ERROR_INT_RAW_R`[src]

Bit 1

`pub fn inlink_dscr_empty_int_raw(&self) -> INLINK_DSCR_EMPTY_INT_RAW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DMA_INT_ST>>`[src]

`pub fn out_total_eof_int_st(&self) -> OUT_TOTAL_EOF_INT_ST_R`[src]

Bit 8

`pub fn out_eof_int_st(&self) -> OUT_EOF_INT_ST_R`[src]

Bit 7

`pub fn out_done_int_st(&self) -> OUT_DONE_INT_ST_R`[src]

Bit 6

`pub fn in_suc_eof_int_st(&self) -> IN_SUC_EOF_INT_ST_R`[src]

Bit 5

`pub fn in_err_eof_int_st(&self) -> IN_ERR_EOF_INT_ST_R`[src]

Bit 4

`pub fn in_done_int_st(&self) -> IN_DONE_INT_ST_R`[src]

Bit 3

`pub fn inlink_dscr_error_int_st(&self) -> INLINK_DSCR_ERROR_INT_ST_R`[src]

Bit 2

`pub fn outlink_dscr_error_int_st(&self) -> OUTLINK_DSCR_ERROR_INT_ST_R`[src]

Bit 1

`pub fn inlink_dscr_empty_int_st(&self) -> INLINK_DSCR_EMPTY_INT_ST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DMA_INT_CLR>>`[src]

`pub fn out_total_eof_int_clr(&self) -> OUT_TOTAL_EOF_INT_CLR_R`[src]

Bit 8

`pub fn out_eof_int_clr(&self) -> OUT_EOF_INT_CLR_R`[src]

Bit 7

`pub fn out_done_int_clr(&self) -> OUT_DONE_INT_CLR_R`[src]

Bit 6

`pub fn in_suc_eof_int_clr(&self) -> IN_SUC_EOF_INT_CLR_R`[src]

Bit 5

`pub fn in_err_eof_int_clr(&self) -> IN_ERR_EOF_INT_CLR_R`[src]

Bit 4

`pub fn in_done_int_clr(&self) -> IN_DONE_INT_CLR_R`[src]

Bit 3

`pub fn inlink_dscr_error_int_clr(&self) -> INLINK_DSCR_ERROR_INT_CLR_R`[src]

Bit 2

`pub fn outlink_dscr_error_int_clr(&self) -> OUTLINK_DSCR_ERROR_INT_CLR_R`[src]

Bit 1

`pub fn inlink_dscr_empty_int_clr(&self) -> INLINK_DSCR_EMPTY_INT_CLR_R`[src]

`pub fn tx_lsb_first(&self) -> TX_LSB_FIRST_R`[src]

Bit 6

`pub fn trans_start(&self) -> TRANS_START_R`[src]

Bit 5

`pub fn ms_mode(&self) -> MS_MODE_R`[src]

Bit 4

`pub fn sample_scl_level(&self) -> SAMPLE_SCL_LEVEL_R`[src]

Bit 2

`pub fn scl_force_out(&self) -> SCL_FORCE_OUT_R`[src]

Bit 1

`pub fn sda_force_out(&self) -> SDA_FORCE_OUT_R`[src]

Bit 0

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn scl_state_last(&self) -> SCL_STATE_LAST_R`[src]

Bits 28:30

`pub fn scl_main_state_last(&self) -> SCL_MAIN_STATE_LAST_R`[src]

Bits 24:26

`pub fn txfifo_cnt(&self) -> TXFIFO_CNT_R`[src]

Bits 18:23

`pub fn rxfifo_cnt(&self) -> RXFIFO_CNT_R`[src]

Bits 8:13

`pub fn byte_trans(&self) -> BYTE_TRANS_R`[src]

Bit 6

`pub fn slave_addressed(&self) -> SLAVE_ADDRESSED_R`[src]

Bit 5

`pub fn bus_busy(&self) -> BUS_BUSY_R`[src]

Bit 4

`pub fn arb_lost(&self) -> ARB_LOST_R`[src]

Bit 3

`pub fn time_out(&self) -> TIME_OUT_R`[src]

Bit 2

`pub fn slave_rw(&self) -> SLAVE_RW_R`[src]

Bit 1

`pub fn ack_rec(&self) -> ACK_REC_R`[src]

Bit 0

`impl R<u32, Reg<u32, _TO>>`[src]

`pub fn time_out_reg(&self) -> TIME_OUT_REG_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _SLAVE_ADDR>>`[src]

`pub fn addr_10bit_en(&self) -> ADDR_10BIT_EN_R`[src]

Bit 31

`pub fn slave_addr(&self) -> SLAVE_ADDR_R`[src]

Bits 0:14

`impl R<u32, Reg<u32, _RXFIFO_ST>>`[src]

`pub fn txfifo_end_addr(&self) -> TXFIFO_END_ADDR_R`[src]

Bits 15:19

`pub fn txfifo_start_addr(&self) -> TXFIFO_START_ADDR_R`[src]

Bits 10:14

`pub fn rxfifo_end_addr(&self) -> RXFIFO_END_ADDR_R`[src]

Bits 5:9

`pub fn rxfifo_start_addr(&self) -> RXFIFO_START_ADDR_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _FIFO_CONF>>`[src]

`pub fn nonfifo_tx_thres(&self) -> NONFIFO_TX_THRES_R`[src]

Bits 20:25

`pub fn nonfifo_rx_thres(&self) -> NONFIFO_RX_THRES_R`[src]

Bits 14:19

`pub fn tx_fifo_rst(&self) -> TX_FIFO_RST_R`[src]

Bit 13

`pub fn rx_fifo_rst(&self) -> RX_FIFO_RST_R`[src]

Bit 12

`pub fn fifo_addr_cfg_en(&self) -> FIFO_ADDR_CFG_EN_R`[src]

Bit 11

`pub fn nonfifo_en(&self) -> NONFIFO_EN_R`[src]

Bit 10

`pub fn txfifo_empty_thrhd(&self) -> TXFIFO_EMPTY_THRHD_R`[src]

Bits 5:9

`pub fn rxfifo_full_thrhd(&self) -> RXFIFO_FULL_THRHD_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _DATA>>`[src]

`pub fn fifo_rdata(&self) -> FIFO_RDATA_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _INT_RAW>>`[src]

`pub fn tx_send_empty_int_raw(&self) -> TX_SEND_EMPTY_INT_RAW_R`[src]

Bit 12

`pub fn rx_rec_full_int_raw(&self) -> RX_REC_FULL_INT_RAW_R`[src]

Bit 11

`pub fn ack_err_int_raw(&self) -> ACK_ERR_INT_RAW_R`[src]

Bit 10

`pub fn trans_start_int_raw(&self) -> TRANS_START_INT_RAW_R`[src]

Bit 9

`pub fn time_out_int_raw(&self) -> TIME_OUT_INT_RAW_R`[src]

Bit 8

`pub fn trans_complete_int_raw(&self) -> TRANS_COMPLETE_INT_RAW_R`[src]

Bit 7

`pub fn master_tran_comp_int_raw(&self) -> MASTER_TRAN_COMP_INT_RAW_R`[src]

Bit 6

`pub fn arbitration_lost_int_raw(&self) -> ARBITRATION_LOST_INT_RAW_R`[src]

Bit 5

`pub fn slave_tran_comp_int_raw(&self) -> SLAVE_TRAN_COMP_INT_RAW_R`[src]

Bit 4

`pub fn end_detect_int_raw(&self) -> END_DETECT_INT_RAW_R`[src]

Bit 3

`pub fn rxfifo_ovf_int_raw(&self) -> RXFIFO_OVF_INT_RAW_R`[src]

Bit 2

`pub fn txfifo_empty_int_raw(&self) -> TXFIFO_EMPTY_INT_RAW_R`[src]

Bit 1

`pub fn rxfifo_full_int_raw(&self) -> RXFIFO_FULL_INT_RAW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_CLR>>`[src]

`pub fn tx_send_empty_int_clr(&self) -> TX_SEND_EMPTY_INT_CLR_R`[src]

Bit 12

`pub fn rx_rec_full_int_clr(&self) -> RX_REC_FULL_INT_CLR_R`[src]

Bit 11

`pub fn ack_err_int_clr(&self) -> ACK_ERR_INT_CLR_R`[src]

Bit 10

`pub fn trans_start_int_clr(&self) -> TRANS_START_INT_CLR_R`[src]

Bit 9

`pub fn time_out_int_clr(&self) -> TIME_OUT_INT_CLR_R`[src]

Bit 8

`pub fn trans_complete_int_clr(&self) -> TRANS_COMPLETE_INT_CLR_R`[src]

Bit 7

`pub fn master_tran_comp_int_clr(&self) -> MASTER_TRAN_COMP_INT_CLR_R`[src]

Bit 6

`pub fn arbitration_lost_int_clr(&self) -> ARBITRATION_LOST_INT_CLR_R`[src]

Bit 5

`pub fn slave_tran_comp_int_clr(&self) -> SLAVE_TRAN_COMP_INT_CLR_R`[src]

Bit 4

`pub fn end_detect_int_clr(&self) -> END_DETECT_INT_CLR_R`[src]

Bit 3

`pub fn rxfifo_ovf_int_clr(&self) -> RXFIFO_OVF_INT_CLR_R`[src]

Bit 2

`pub fn txfifo_empty_int_clr(&self) -> TXFIFO_EMPTY_INT_CLR_R`[src]

Bit 1

`pub fn rxfifo_full_int_clr(&self) -> RXFIFO_FULL_INT_CLR_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_ENA>>`[src]

`pub fn tx_send_empty_int_ena(&self) -> TX_SEND_EMPTY_INT_ENA_R`[src]

Bit 12

`pub fn rx_rec_full_int_ena(&self) -> RX_REC_FULL_INT_ENA_R`[src]

Bit 11

`pub fn ack_err_int_ena(&self) -> ACK_ERR_INT_ENA_R`[src]

Bit 10

`pub fn trans_start_int_ena(&self) -> TRANS_START_INT_ENA_R`[src]

Bit 9

`pub fn time_out_int_ena(&self) -> TIME_OUT_INT_ENA_R`[src]

Bit 8

`pub fn trans_complete_int_ena(&self) -> TRANS_COMPLETE_INT_ENA_R`[src]

Bit 7

`pub fn master_tran_comp_int_ena(&self) -> MASTER_TRAN_COMP_INT_ENA_R`[src]

Bit 6

`pub fn arbitration_lost_int_ena(&self) -> ARBITRATION_LOST_INT_ENA_R`[src]

Bit 5

`pub fn slave_tran_comp_int_ena(&self) -> SLAVE_TRAN_COMP_INT_ENA_R`[src]

Bit 4

`pub fn end_detect_int_ena(&self) -> END_DETECT_INT_ENA_R`[src]

Bit 3

`pub fn rxfifo_ovf_int_ena(&self) -> RXFIFO_OVF_INT_ENA_R`[src]

Bit 2

`pub fn txfifo_empty_int_ena(&self) -> TXFIFO_EMPTY_INT_ENA_R`[src]

Bit 1

`pub fn rxfifo_full_int_ena(&self) -> RXFIFO_FULL_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_STATUS>>`[src]

`pub fn tx_send_empty_int_st(&self) -> TX_SEND_EMPTY_INT_ST_R`[src]

Bit 12

`pub fn rx_rec_full_int_st(&self) -> RX_REC_FULL_INT_ST_R`[src]

Bit 11

`pub fn ack_err_int_st(&self) -> ACK_ERR_INT_ST_R`[src]

Bit 10

`pub fn trans_start_int_st(&self) -> TRANS_START_INT_ST_R`[src]

Bit 9

`pub fn time_out_int_st(&self) -> TIME_OUT_INT_ST_R`[src]

Bit 8

`pub fn trans_complete_int_st(&self) -> TRANS_COMPLETE_INT_ST_R`[src]

Bit 7

`pub fn master_tran_comp_int_st(&self) -> MASTER_TRAN_COMP_INT_ST_R`[src]

Bit 6

`pub fn arbitration_lost_int_st(&self) -> ARBITRATION_LOST_INT_ST_R`[src]

Bit 5

`pub fn slave_tran_comp_int_st(&self) -> SLAVE_TRAN_COMP_INT_ST_R`[src]

Bit 4

`pub fn end_detect_int_st(&self) -> END_DETECT_INT_ST_R`[src]

Bit 3

`pub fn rxfifo_ovf_int_st(&self) -> RXFIFO_OVF_INT_ST_R`[src]

Bit 2

`pub fn txfifo_empty_int_st(&self) -> TXFIFO_EMPTY_INT_ST_R`[src]

Bit 31

`pub fn command15(&self) -> COMMAND15_R`[src]

Bits 0:13

`impl R<u32, Reg<u32, _DATE>>`[src]

`pub fn date(&self) -> DATE_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _BLK0_RDATA0>>`[src]

`pub fn rd_flash_crypt_cnt(&self) -> RD_FLASH_CRYPT_CNT_R`[src]

Bits 20:26

`pub fn rd_efuse_rd_dis(&self) -> RD_EFUSE_RD_DIS_R`[src]

Bits 16:19

`impl R<u32, Reg<u32, _BLK0_RDATA1>>`[src]

`pub fn rd_wifi_mac_crc_low(&self) -> RD_WIFI_MAC_CRC_LOW_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _BLK0_RDATA2>>`[src]

`pub fn rd_wifi_mac_crc_high(&self) -> RD_WIFI_MAC_CRC_HIGH_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _BLK0_RDATA3>>`[src]

`pub fn rd_chip_ver_rev1(&self) -> RD_CHIP_VER_REV1_R`[src]

Bit 15

`pub fn rd_chip_cpu_freq_rated(&self) -> RD_CHIP_CPU_FREQ_RATED_R`[src]

Bit 13

`pub fn rd_chip_cpu_freq_low(&self) -> RD_CHIP_CPU_FREQ_LOW_R`[src]

Bit 12

`pub fn rd_chip_ver_pkg(&self) -> RD_CHIP_VER_PKG_R`[src]

Bits 9:11

`pub fn rd_spi_pad_config_hd(&self) -> RD_SPI_PAD_CONFIG_HD_R`[src]

Bits 4:8

`pub fn rd_chip_ver_dis_cache(&self) -> RD_CHIP_VER_DIS_CACHE_R`[src]

Bit 3

`pub fn rd_chip_ver_32pad(&self) -> RD_CHIP_VER_32PAD_R`[src]

Bit 2

`pub fn rd_chip_ver_dis_bt(&self) -> RD_CHIP_VER_DIS_BT_R`[src]

Bit 1

`pub fn rd_chip_ver_dis_app_cpu(&self) -> RD_CHIP_VER_DIS_APP_CPU_R`[src]

Bit 0

`impl R<u32, Reg<u32, _BLK0_RDATA4>>`[src]

`pub fn rd_sdio_force(&self) -> RD_SDIO_FORCE_R`[src]

Bit 16

`pub fn rd_sdio_tieh(&self) -> RD_SDIO_TIEH_R`[src]

Bit 15

`pub fn rd_xpd_sdio_reg(&self) -> RD_XPD_SDIO_REG_R`[src]

Bit 14

`pub fn rd_adc_vref(&self) -> RD_ADC_VREF_R`[src]

Bits 8:12

`pub fn rd_sdio_drefl(&self) -> RD_SDIO_DREFL_R`[src]

Bits 12:13

`pub fn rd_sdio_drefm(&self) -> RD_SDIO_DREFM_R`[src]

Bits 10:11

`pub fn rd_sdio_drefh(&self) -> RD_SDIO_DREFH_R`[src]

Bits 8:9

`pub fn rd_ck8m_freq(&self) -> RD_CK8M_FREQ_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _BLK0_RDATA5>>`[src]

`pub fn rd_flash_crypt_config(&self) -> RD_FLASH_CRYPT_CONFIG_R`[src]

Bits 28:31

`pub fn rd_inst_config(&self) -> RD_INST_CONFIG_R`[src]

Bits 20:27

`pub fn rd_spi_pad_config_d(&self) -> RD_SPI_PAD_CONFIG_D_R`[src]

Bits 10:14

`pub fn rd_spi_pad_config_q(&self) -> RD_SPI_PAD_CONFIG_Q_R`[src]

Bits 5:9

`pub fn rd_spi_pad_config_clk(&self) -> RD_SPI_PAD_CONFIG_CLK_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _BLK0_RDATA6>>`[src]

`pub fn rd_key_status(&self) -> RD_KEY_STATUS_R`[src]

Bit 10

`pub fn rd_disable_dl_cache(&self) -> RD_DISABLE_DL_CACHE_R`[src]

Bit 9

`pub fn rd_disable_dl_decrypt(&self) -> RD_DISABLE_DL_DECRYPT_R`[src]

Bit 8

`pub fn rd_disable_dl_encrypt(&self) -> RD_DISABLE_DL_ENCRYPT_R`[src]

Bit 7

`pub fn rd_disable_jtag(&self) -> RD_DISABLE_JTAG_R`[src]

Bit 6

`pub fn rd_abs_done_1(&self) -> RD_ABS_DONE_1_R`[src]

Bit 5

`pub fn rd_abs_done_0(&self) -> RD_ABS_DONE_0_R`[src]

Bit 4

`pub fn rd_disable_sdio_host(&self) -> RD_DISABLE_SDIO_HOST_R`[src]

Bit 3

`pub fn rd_console_debug_disable(&self) -> RD_CONSOLE_DEBUG_DISABLE_R`[src]

Bit 2

`pub fn rd_coding_scheme(&self) -> RD_CODING_SCHEME_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _BLK0_WDATA0>>`[src]

`pub fn flash_crypt_cnt(&self) -> FLASH_CRYPT_CNT_R`[src]

Bits 20:26

`pub fn rd_dis(&self) -> RD_DIS_R`[src]

Bits 16:19

`pub fn wr_dis(&self) -> WR_DIS_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _BLK0_WDATA1>>`[src]

`pub fn wifi_mac_crc_low(&self) -> WIFI_MAC_CRC_LOW_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _BLK0_WDATA2>>`[src]

`pub fn wifi_mac_crc_high(&self) -> WIFI_MAC_CRC_HIGH_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _BLK0_WDATA3>>`[src]

`pub fn chip_ver_rev1(&self) -> CHIP_VER_REV1_R`[src]

Bit 15

`pub fn chip_cpu_freq_rated(&self) -> CHIP_CPU_FREQ_RATED_R`[src]

Bit 13

`pub fn chip_cpu_freq_low(&self) -> CHIP_CPU_FREQ_LOW_R`[src]

Bit 12

`pub fn chip_ver_pkg(&self) -> CHIP_VER_PKG_R`[src]

Bits 9:11

`pub fn spi_pad_config_hd(&self) -> SPI_PAD_CONFIG_HD_R`[src]

Bits 4:8

`pub fn chip_ver_dis_cache(&self) -> CHIP_VER_DIS_CACHE_R`[src]

Bit 3

`pub fn chip_ver_32pad(&self) -> CHIP_VER_32PAD_R`[src]

Bit 2

`pub fn chip_ver_dis_bt(&self) -> CHIP_VER_DIS_BT_R`[src]

Bit 1

`pub fn chip_ver_dis_app_cpu(&self) -> CHIP_VER_DIS_APP_CPU_R`[src]

Bit 0

`impl R<u32, Reg<u32, _BLK0_WDATA4>>`[src]

`pub fn sdio_force(&self) -> SDIO_FORCE_R`[src]

Bit 16

`pub fn sdio_tieh(&self) -> SDIO_TIEH_R`[src]

Bit 15

`pub fn xpd_sdio_reg(&self) -> XPD_SDIO_REG_R`[src]

Bit 14

`pub fn adc_vref(&self) -> ADC_VREF_R`[src]

Bits 8:12

`pub fn sdio_drefl(&self) -> SDIO_DREFL_R`[src]

Bits 12:13

`pub fn sdio_drefm(&self) -> SDIO_DREFM_R`[src]

Bits 10:11

`pub fn sdio_drefh(&self) -> SDIO_DREFH_R`[src]

Bits 8:9

`pub fn ck8m_freq(&self) -> CK8M_FREQ_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _BLK0_WDATA5>>`[src]

`pub fn flash_crypt_config(&self) -> FLASH_CRYPT_CONFIG_R`[src]

Bits 28:31

`pub fn inst_config(&self) -> INST_CONFIG_R`[src]

Bits 20:27

`pub fn spi_pad_config_d(&self) -> SPI_PAD_CONFIG_D_R`[src]

Bits 10:14

`pub fn spi_pad_config_q(&self) -> SPI_PAD_CONFIG_Q_R`[src]

Bits 5:9

`pub fn spi_pad_config_clk(&self) -> SPI_PAD_CONFIG_CLK_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _BLK0_WDATA6>>`[src]

`pub fn key_status(&self) -> KEY_STATUS_R`[src]

Bit 10

`pub fn disable_dl_cache(&self) -> DISABLE_DL_CACHE_R`[src]

Bit 9

`pub fn disable_dl_decrypt(&self) -> DISABLE_DL_DECRYPT_R`[src]

Bit 8

`pub fn disable_dl_encrypt(&self) -> DISABLE_DL_ENCRYPT_R`[src]

Bit 7

`pub fn disable_jtag(&self) -> DISABLE_JTAG_R`[src]

Bit 6

`pub fn abs_done_1(&self) -> ABS_DONE_1_R`[src]

Bit 5

`pub fn abs_done_0(&self) -> ABS_DONE_0_R`[src]

Bit 4

`pub fn disable_sdio_host(&self) -> DISABLE_SDIO_HOST_R`[src]

Bit 3

`pub fn console_debug_disable(&self) -> CONSOLE_DEBUG_DISABLE_R`[src]

`impl R<u32, Reg<u32, _BLK3_RDATA3>>`[src]

`pub fn blk3_dout3(&self) -> BLK3_DOUT3_R`[src]

Bits 0:31

`pub fn rd_adc2_tp_high(&self) -> RD_ADC2_TP_HIGH_R`[src]

Bits 23:31

`pub fn rd_adc2_tp_low(&self) -> RD_ADC2_TP_LOW_R`[src]

Bits 16:22

`pub fn rd_adc1_tp_high(&self) -> RD_ADC1_TP_HIGH_R`[src]

`impl R<u32, Reg<u32, _BLK3_WDATA3>>`[src]

`pub fn blk3_din3(&self) -> BLK3_DIN3_R`[src]

Bits 0:31

`pub fn adc2_tp_high(&self) -> ADC2_TP_HIGH_R`[src]

Bits 23:31

`pub fn adc2_tp_low(&self) -> ADC2_TP_LOW_R`[src]

Bits 16:22

`pub fn adc1_tp_high(&self) -> ADC1_TP_HIGH_R`[src]

`pub fn clk_sel1(&self) -> CLK_SEL1_R`[src]

Bits 8:15

`pub fn clk_sel0(&self) -> CLK_SEL0_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _CONF>>`[src]

`pub fn force_no_wr_rd_dis(&self) -> FORCE_NO_WR_RD_DIS_R`[src]

Bit 16

`pub fn op_code(&self) -> OP_CODE_R`[src]

Bits 0:15

Bit 8

`pub fn dac_clk_div(&self) -> DAC_CLK_DIV_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _DEC_STATUS>>`[src]

`pub fn dec_warnings(&self) -> DEC_WARNINGS_R`[src]

Bits 0:11

`impl R<u32, Reg<u32, _DATE>>`[src]

`pub fn date(&self) -> DATE_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _U0_CONF0>>`[src]

`pub fn ch1_lctrl_mode_u0(&self) -> CH1_LCTRL_MODE_U0_R`[src]

Bits 30:31

`pub fn ch1_hctrl_mode_u0(&self) -> CH1_HCTRL_MODE_U0_R`[src]

Bits 28:29

`pub fn ch1_pos_mode_u0(&self) -> CH1_POS_MODE_U0_R`[src]

Bits 26:27

`pub fn ch1_neg_mode_u0(&self) -> CH1_NEG_MODE_U0_R`[src]

Bits 24:25

`pub fn ch0_lctrl_mode_u0(&self) -> CH0_LCTRL_MODE_U0_R`[src]

Bits 22:23

`pub fn ch0_hctrl_mode_u0(&self) -> CH0_HCTRL_MODE_U0_R`[src]

Bits 20:21

`pub fn ch0_pos_mode_u0(&self) -> CH0_POS_MODE_U0_R`[src]

Bits 18:19

`pub fn ch0_neg_mode_u0(&self) -> CH0_NEG_MODE_U0_R`[src]

Bits 16:17

`pub fn thr_thres1_en_u0(&self) -> THR_THRES1_EN_U0_R`[src]

Bit 15

`pub fn thr_thres0_en_u0(&self) -> THR_THRES0_EN_U0_R`[src]

Bit 14

`pub fn thr_l_lim_en_u0(&self) -> THR_L_LIM_EN_U0_R`[src]

Bit 13

`pub fn thr_h_lim_en_u0(&self) -> THR_H_LIM_EN_U0_R`[src]

Bit 12

`pub fn thr_zero_en_u0(&self) -> THR_ZERO_EN_U0_R`[src]

Bit 11

`pub fn filter_en_u0(&self) -> FILTER_EN_U0_R`[src]

Bit 10

`pub fn filter_thres_u0(&self) -> FILTER_THRES_U0_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _U0_CONF1>>`[src]

`pub fn cnt_thres1_u0(&self) -> CNT_THRES1_U0_R`[src]

Bits 16:31

`pub fn cnt_thres0_u0(&self) -> CNT_THRES0_U0_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _U0_CONF2>>`[src]

`pub fn cnt_l_lim_u0(&self) -> CNT_L_LIM_U0_R`[src]

Bits 16:31

`pub fn cnt_h_lim_u0(&self) -> CNT_H_LIM_U0_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _U1_CONF0>>`[src]

`pub fn ch1_lctrl_mode_u1(&self) -> CH1_LCTRL_MODE_U1_R`[src]

Bits 30:31

`pub fn ch1_hctrl_mode_u1(&self) -> CH1_HCTRL_MODE_U1_R`[src]

Bits 28:29

`pub fn ch1_pos_mode_u1(&self) -> CH1_POS_MODE_U1_R`[src]

Bits 26:27

`pub fn ch1_neg_mode_u1(&self) -> CH1_NEG_MODE_U1_R`[src]

Bits 24:25

`pub fn ch0_lctrl_mode_u1(&self) -> CH0_LCTRL_MODE_U1_R`[src]

Bits 22:23

`pub fn ch0_hctrl_mode_u1(&self) -> CH0_HCTRL_MODE_U1_R`[src]

Bits 20:21

`pub fn ch0_pos_mode_u1(&self) -> CH0_POS_MODE_U1_R`[src]

Bits 18:19

`pub fn ch0_neg_mode_u1(&self) -> CH0_NEG_MODE_U1_R`[src]

Bits 16:17

`pub fn thr_thres1_en_u1(&self) -> THR_THRES1_EN_U1_R`[src]

Bit 15

`pub fn thr_thres0_en_u1(&self) -> THR_THRES0_EN_U1_R`[src]

Bit 14

`pub fn thr_l_lim_en_u1(&self) -> THR_L_LIM_EN_U1_R`[src]

Bit 13

`pub fn thr_h_lim_en_u1(&self) -> THR_H_LIM_EN_U1_R`[src]

Bit 12

`pub fn thr_zero_en_u1(&self) -> THR_ZERO_EN_U1_R`[src]

Bit 11

`pub fn filter_en_u1(&self) -> FILTER_EN_U1_R`[src]

Bit 10

`pub fn filter_thres_u1(&self) -> FILTER_THRES_U1_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _U1_CONF1>>`[src]

`pub fn cnt_thres1_u1(&self) -> CNT_THRES1_U1_R`[src]

Bits 16:31

`pub fn cnt_thres0_u1(&self) -> CNT_THRES0_U1_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _U1_CONF2>>`[src]

`pub fn cnt_l_lim_u1(&self) -> CNT_L_LIM_U1_R`[src]

Bits 16:31

`pub fn cnt_h_lim_u1(&self) -> CNT_H_LIM_U1_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _U2_CONF0>>`[src]

`pub fn ch1_lctrl_mode_u2(&self) -> CH1_LCTRL_MODE_U2_R`[src]

Bits 30:31

`pub fn ch1_hctrl_mode_u2(&self) -> CH1_HCTRL_MODE_U2_R`[src]

Bits 28:29

`pub fn ch1_pos_mode_u2(&self) -> CH1_POS_MODE_U2_R`[src]

Bits 26:27

`pub fn ch1_neg_mode_u2(&self) -> CH1_NEG_MODE_U2_R`[src]

Bits 24:25

`pub fn ch0_lctrl_mode_u2(&self) -> CH0_LCTRL_MODE_U2_R`[src]

Bits 22:23

`pub fn ch0_hctrl_mode_u2(&self) -> CH0_HCTRL_MODE_U2_R`[src]

Bits 20:21

`pub fn ch0_pos_mode_u2(&self) -> CH0_POS_MODE_U2_R`[src]

Bits 18:19

`pub fn ch0_neg_mode_u2(&self) -> CH0_NEG_MODE_U2_R`[src]

Bits 16:17

`pub fn thr_thres1_en_u2(&self) -> THR_THRES1_EN_U2_R`[src]

Bit 15

`pub fn thr_thres0_en_u2(&self) -> THR_THRES0_EN_U2_R`[src]

Bit 14

`pub fn thr_l_lim_en_u2(&self) -> THR_L_LIM_EN_U2_R`[src]

Bit 13

`pub fn thr_h_lim_en_u2(&self) -> THR_H_LIM_EN_U2_R`[src]

Bit 12

`pub fn thr_zero_en_u2(&self) -> THR_ZERO_EN_U2_R`[src]

Bit 11

`pub fn filter_en_u2(&self) -> FILTER_EN_U2_R`[src]

Bit 10

`pub fn filter_thres_u2(&self) -> FILTER_THRES_U2_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _U2_CONF1>>`[src]

`pub fn cnt_thres1_u2(&self) -> CNT_THRES1_U2_R`[src]

Bits 16:31

`pub fn cnt_thres0_u2(&self) -> CNT_THRES0_U2_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _U2_CONF2>>`[src]

`pub fn cnt_l_lim_u2(&self) -> CNT_L_LIM_U2_R`[src]

Bits 16:31

`pub fn cnt_h_lim_u2(&self) -> CNT_H_LIM_U2_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _U3_CONF0>>`[src]

`pub fn ch1_lctrl_mode_u3(&self) -> CH1_LCTRL_MODE_U3_R`[src]

Bits 30:31

`pub fn ch1_hctrl_mode_u3(&self) -> CH1_HCTRL_MODE_U3_R`[src]

Bits 28:29

`pub fn ch1_pos_mode_u3(&self) -> CH1_POS_MODE_U3_R`[src]

Bits 26:27

`pub fn ch1_neg_mode_u3(&self) -> CH1_NEG_MODE_U3_R`[src]

Bits 24:25

`pub fn ch0_lctrl_mode_u3(&self) -> CH0_LCTRL_MODE_U3_R`[src]

Bits 22:23

`pub fn ch0_hctrl_mode_u3(&self) -> CH0_HCTRL_MODE_U3_R`[src]

Bits 20:21

`pub fn ch0_pos_mode_u3(&self) -> CH0_POS_MODE_U3_R`[src]

Bits 18:19

`pub fn ch0_neg_mode_u3(&self) -> CH0_NEG_MODE_U3_R`[src]

Bits 16:17

`pub fn thr_thres1_en_u3(&self) -> THR_THRES1_EN_U3_R`[src]

Bit 15

`pub fn thr_thres0_en_u3(&self) -> THR_THRES0_EN_U3_R`[src]

Bit 14

`pub fn thr_l_lim_en_u3(&self) -> THR_L_LIM_EN_U3_R`[src]

Bit 13

`pub fn thr_h_lim_en_u3(&self) -> THR_H_LIM_EN_U3_R`[src]

Bit 12

`pub fn thr_zero_en_u3(&self) -> THR_ZERO_EN_U3_R`[src]

Bit 11

`pub fn filter_en_u3(&self) -> FILTER_EN_U3_R`[src]

Bit 10

`pub fn filter_thres_u3(&self) -> FILTER_THRES_U3_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _U3_CONF1>>`[src]

`pub fn cnt_thres1_u3(&self) -> CNT_THRES1_U3_R`[src]

Bits 16:31

`pub fn cnt_thres0_u3(&self) -> CNT_THRES0_U3_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _U3_CONF2>>`[src]

`pub fn cnt_l_lim_u3(&self) -> CNT_L_LIM_U3_R`[src]

Bits 16:31

`pub fn cnt_h_lim_u3(&self) -> CNT_H_LIM_U3_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _U4_CONF0>>`[src]

`pub fn ch1_lctrl_mode_u4(&self) -> CH1_LCTRL_MODE_U4_R`[src]

Bits 30:31

`pub fn ch1_hctrl_mode_u4(&self) -> CH1_HCTRL_MODE_U4_R`[src]

Bits 28:29

`pub fn ch1_pos_mode_u4(&self) -> CH1_POS_MODE_U4_R`[src]

Bits 26:27

`pub fn ch1_neg_mode_u4(&self) -> CH1_NEG_MODE_U4_R`[src]

Bits 24:25

`pub fn ch0_lctrl_mode_u4(&self) -> CH0_LCTRL_MODE_U4_R`[src]

Bits 22:23

`pub fn ch0_hctrl_mode_u4(&self) -> CH0_HCTRL_MODE_U4_R`[src]

Bits 20:21

`pub fn ch0_pos_mode_u4(&self) -> CH0_POS_MODE_U4_R`[src]

Bits 18:19

`pub fn ch0_neg_mode_u4(&self) -> CH0_NEG_MODE_U4_R`[src]

Bits 16:17

`pub fn thr_thres1_en_u4(&self) -> THR_THRES1_EN_U4_R`[src]

Bit 15

`pub fn thr_thres0_en_u4(&self) -> THR_THRES0_EN_U4_R`[src]

Bit 14

`pub fn thr_l_lim_en_u4(&self) -> THR_L_LIM_EN_U4_R`[src]

Bit 13

`pub fn thr_h_lim_en_u4(&self) -> THR_H_LIM_EN_U4_R`[src]

Bit 12

`pub fn thr_zero_en_u4(&self) -> THR_ZERO_EN_U4_R`[src]

Bit 11

`pub fn filter_en_u4(&self) -> FILTER_EN_U4_R`[src]

Bit 10

`pub fn filter_thres_u4(&self) -> FILTER_THRES_U4_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _U4_CONF1>>`[src]

`pub fn cnt_thres1_u4(&self) -> CNT_THRES1_U4_R`[src]

Bits 16:31

`pub fn cnt_thres0_u4(&self) -> CNT_THRES0_U4_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _U4_CONF2>>`[src]

`pub fn cnt_l_lim_u4(&self) -> CNT_L_LIM_U4_R`[src]

Bits 16:31

`pub fn cnt_h_lim_u4(&self) -> CNT_H_LIM_U4_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _U5_CONF0>>`[src]

`pub fn ch1_lctrl_mode_u5(&self) -> CH1_LCTRL_MODE_U5_R`[src]

Bits 30:31

`pub fn ch1_hctrl_mode_u5(&self) -> CH1_HCTRL_MODE_U5_R`[src]

Bits 28:29

`pub fn ch1_pos_mode_u5(&self) -> CH1_POS_MODE_U5_R`[src]

Bits 26:27

`pub fn ch1_neg_mode_u5(&self) -> CH1_NEG_MODE_U5_R`[src]

Bits 24:25

`pub fn ch0_lctrl_mode_u5(&self) -> CH0_LCTRL_MODE_U5_R`[src]

Bits 22:23

`pub fn ch0_hctrl_mode_u5(&self) -> CH0_HCTRL_MODE_U5_R`[src]

Bits 20:21

`pub fn ch0_pos_mode_u5(&self) -> CH0_POS_MODE_U5_R`[src]

Bits 18:19

`pub fn ch0_neg_mode_u5(&self) -> CH0_NEG_MODE_U5_R`[src]

Bits 16:17

`pub fn thr_thres1_en_u5(&self) -> THR_THRES1_EN_U5_R`[src]

Bit 15

`pub fn thr_thres0_en_u5(&self) -> THR_THRES0_EN_U5_R`[src]

Bit 14

`pub fn thr_l_lim_en_u5(&self) -> THR_L_LIM_EN_U5_R`[src]

Bit 13

`pub fn thr_h_lim_en_u5(&self) -> THR_H_LIM_EN_U5_R`[src]

Bit 12

`pub fn thr_zero_en_u5(&self) -> THR_ZERO_EN_U5_R`[src]

Bit 11

`pub fn filter_en_u5(&self) -> FILTER_EN_U5_R`[src]

Bit 10

`pub fn filter_thres_u5(&self) -> FILTER_THRES_U5_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _U5_CONF1>>`[src]

`pub fn cnt_thres1_u5(&self) -> CNT_THRES1_U5_R`[src]

Bits 16:31

`pub fn cnt_thres0_u5(&self) -> CNT_THRES0_U5_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _U5_CONF2>>`[src]

`pub fn cnt_l_lim_u5(&self) -> CNT_L_LIM_U5_R`[src]

Bits 16:31

`pub fn cnt_h_lim_u5(&self) -> CNT_H_LIM_U5_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _U6_CONF0>>`[src]

`pub fn ch1_lctrl_mode_u6(&self) -> CH1_LCTRL_MODE_U6_R`[src]

Bits 30:31

`pub fn ch1_hctrl_mode_u6(&self) -> CH1_HCTRL_MODE_U6_R`[src]

Bits 28:29

`pub fn ch1_pos_mode_u6(&self) -> CH1_POS_MODE_U6_R`[src]

Bits 26:27

`pub fn ch1_neg_mode_u6(&self) -> CH1_NEG_MODE_U6_R`[src]

Bits 24:25

`pub fn ch0_lctrl_mode_u6(&self) -> CH0_LCTRL_MODE_U6_R`[src]

Bits 22:23

`pub fn ch0_hctrl_mode_u6(&self) -> CH0_HCTRL_MODE_U6_R`[src]

Bits 20:21

`pub fn ch0_pos_mode_u6(&self) -> CH0_POS_MODE_U6_R`[src]

Bits 18:19

`pub fn ch0_neg_mode_u6(&self) -> CH0_NEG_MODE_U6_R`[src]

Bits 16:17

`pub fn thr_thres1_en_u6(&self) -> THR_THRES1_EN_U6_R`[src]

Bit 15

`pub fn thr_thres0_en_u6(&self) -> THR_THRES0_EN_U6_R`[src]

Bit 14

`pub fn thr_l_lim_en_u6(&self) -> THR_L_LIM_EN_U6_R`[src]

Bit 13

`pub fn thr_h_lim_en_u6(&self) -> THR_H_LIM_EN_U6_R`[src]

Bit 12

`pub fn thr_zero_en_u6(&self) -> THR_ZERO_EN_U6_R`[src]

Bit 11

`pub fn filter_en_u6(&self) -> FILTER_EN_U6_R`[src]

Bit 10

`pub fn filter_thres_u6(&self) -> FILTER_THRES_U6_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _U6_CONF1>>`[src]

`pub fn cnt_thres1_u6(&self) -> CNT_THRES1_U6_R`[src]

Bits 16:31

`pub fn cnt_thres0_u6(&self) -> CNT_THRES0_U6_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _U6_CONF2>>`[src]

`pub fn cnt_l_lim_u6(&self) -> CNT_L_LIM_U6_R`[src]

Bits 16:31

`pub fn cnt_h_lim_u6(&self) -> CNT_H_LIM_U6_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _U7_CONF0>>`[src]

`pub fn ch1_lctrl_mode_u7(&self) -> CH1_LCTRL_MODE_U7_R`[src]

Bits 30:31

`pub fn ch1_hctrl_mode_u7(&self) -> CH1_HCTRL_MODE_U7_R`[src]

Bits 28:29

`pub fn ch1_pos_mode_u7(&self) -> CH1_POS_MODE_U7_R`[src]

Bits 26:27

`pub fn ch1_neg_mode_u7(&self) -> CH1_NEG_MODE_U7_R`[src]

Bits 24:25

`pub fn ch0_lctrl_mode_u7(&self) -> CH0_LCTRL_MODE_U7_R`[src]

Bits 22:23

`pub fn ch0_hctrl_mode_u7(&self) -> CH0_HCTRL_MODE_U7_R`[src]

Bits 20:21

`pub fn ch0_pos_mode_u7(&self) -> CH0_POS_MODE_U7_R`[src]

Bits 18:19

`pub fn ch0_neg_mode_u7(&self) -> CH0_NEG_MODE_U7_R`[src]

Bits 16:17

`pub fn thr_thres1_en_u7(&self) -> THR_THRES1_EN_U7_R`[src]

Bit 15

`pub fn thr_thres0_en_u7(&self) -> THR_THRES0_EN_U7_R`[src]

Bit 14

`pub fn thr_l_lim_en_u7(&self) -> THR_L_LIM_EN_U7_R`[src]

Bit 13

`pub fn thr_h_lim_en_u7(&self) -> THR_H_LIM_EN_U7_R`[src]

Bit 12

`pub fn thr_zero_en_u7(&self) -> THR_ZERO_EN_U7_R`[src]

Bit 11

`pub fn filter_en_u7(&self) -> FILTER_EN_U7_R`[src]

Bit 10

`pub fn filter_thres_u7(&self) -> FILTER_THRES_U7_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _U7_CONF1>>`[src]

`pub fn cnt_thres1_u7(&self) -> CNT_THRES1_U7_R`[src]

Bits 16:31

`pub fn cnt_thres0_u7(&self) -> CNT_THRES0_U7_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _U7_CONF2>>`[src]

`pub fn cnt_l_lim_u7(&self) -> CNT_L_LIM_U7_R`[src]

`pub fn cnt_thr_event_u6_int_raw(&self) -> CNT_THR_EVENT_U6_INT_RAW_R`[src]

Bit 6

`pub fn cnt_thr_event_u5_int_raw(&self) -> CNT_THR_EVENT_U5_INT_RAW_R`[src]

Bit 5

`pub fn cnt_thr_event_u4_int_raw(&self) -> CNT_THR_EVENT_U4_INT_RAW_R`[src]

Bit 4

`pub fn cnt_thr_event_u3_int_raw(&self) -> CNT_THR_EVENT_U3_INT_RAW_R`[src]

Bit 3

`pub fn cnt_thr_event_u2_int_raw(&self) -> CNT_THR_EVENT_U2_INT_RAW_R`[src]

Bit 2

`pub fn cnt_thr_event_u1_int_raw(&self) -> CNT_THR_EVENT_U1_INT_RAW_R`[src]

Bit 1

`pub fn cnt_thr_event_u0_int_raw(&self) -> CNT_THR_EVENT_U0_INT_RAW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_ST>>`[src]

`pub fn cnt_thr_event_u7_int_st(&self) -> CNT_THR_EVENT_U7_INT_ST_R`[src]

Bit 7

`pub fn cnt_thr_event_u6_int_st(&self) -> CNT_THR_EVENT_U6_INT_ST_R`[src]

Bit 6

`pub fn cnt_thr_event_u5_int_st(&self) -> CNT_THR_EVENT_U5_INT_ST_R`[src]

Bit 5

`pub fn cnt_thr_event_u4_int_st(&self) -> CNT_THR_EVENT_U4_INT_ST_R`[src]

Bit 4

`pub fn cnt_thr_event_u3_int_st(&self) -> CNT_THR_EVENT_U3_INT_ST_R`[src]

Bit 3

`pub fn cnt_thr_event_u2_int_st(&self) -> CNT_THR_EVENT_U2_INT_ST_R`[src]

Bit 2

`pub fn cnt_thr_event_u1_int_st(&self) -> CNT_THR_EVENT_U1_INT_ST_R`[src]

Bit 1

`pub fn cnt_thr_event_u0_int_st(&self) -> CNT_THR_EVENT_U0_INT_ST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_ENA>>`[src]

`pub fn cnt_thr_event_u7_int_ena(&self) -> CNT_THR_EVENT_U7_INT_ENA_R`[src]

Bit 7

`pub fn cnt_thr_event_u6_int_ena(&self) -> CNT_THR_EVENT_U6_INT_ENA_R`[src]

Bit 6

`pub fn cnt_thr_event_u5_int_ena(&self) -> CNT_THR_EVENT_U5_INT_ENA_R`[src]

Bit 5

`pub fn cnt_thr_event_u4_int_ena(&self) -> CNT_THR_EVENT_U4_INT_ENA_R`[src]

Bit 4

`pub fn cnt_thr_event_u3_int_ena(&self) -> CNT_THR_EVENT_U3_INT_ENA_R`[src]

Bit 3

`pub fn cnt_thr_event_u2_int_ena(&self) -> CNT_THR_EVENT_U2_INT_ENA_R`[src]

Bit 2

`pub fn cnt_thr_event_u1_int_ena(&self) -> CNT_THR_EVENT_U1_INT_ENA_R`[src]

Bit 1

`pub fn cnt_thr_event_u0_int_ena(&self) -> CNT_THR_EVENT_U0_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_CLR>>`[src]

`pub fn cnt_thr_event_u7_int_clr(&self) -> CNT_THR_EVENT_U7_INT_CLR_R`[src]

Bit 7

`pub fn cnt_thr_event_u6_int_clr(&self) -> CNT_THR_EVENT_U6_INT_CLR_R`[src]

Bit 6

`pub fn cnt_thr_event_u5_int_clr(&self) -> CNT_THR_EVENT_U5_INT_CLR_R`[src]

Bit 5

`pub fn cnt_thr_event_u4_int_clr(&self) -> CNT_THR_EVENT_U4_INT_CLR_R`[src]

Bit 4

`pub fn cnt_thr_event_u3_int_clr(&self) -> CNT_THR_EVENT_U3_INT_CLR_R`[src]

Bit 3

`pub fn cnt_thr_event_u2_int_clr(&self) -> CNT_THR_EVENT_U2_INT_CLR_R`[src]

Bit 2

`pub fn cnt_thr_event_u1_int_clr(&self) -> CNT_THR_EVENT_U1_INT_CLR_R`[src]

`pub fn cnt_pause_u7(&self) -> CNT_PAUSE_U7_R`[src]

Bit 15

`pub fn plus_cnt_rst_u7(&self) -> PLUS_CNT_RST_U7_R`[src]

Bit 14

`pub fn cnt_pause_u6(&self) -> CNT_PAUSE_U6_R`[src]

Bit 13

`pub fn plus_cnt_rst_u6(&self) -> PLUS_CNT_RST_U6_R`[src]

Bit 12

`pub fn cnt_pause_u5(&self) -> CNT_PAUSE_U5_R`[src]

Bit 11

`pub fn plus_cnt_rst_u5(&self) -> PLUS_CNT_RST_U5_R`[src]

Bit 10

`pub fn cnt_pause_u4(&self) -> CNT_PAUSE_U4_R`[src]

Bit 9

`pub fn plus_cnt_rst_u4(&self) -> PLUS_CNT_RST_U4_R`[src]

Bit 8

`pub fn cnt_pause_u3(&self) -> CNT_PAUSE_U3_R`[src]

Bit 7

`pub fn plus_cnt_rst_u3(&self) -> PLUS_CNT_RST_U3_R`[src]

Bit 6

`pub fn cnt_pause_u2(&self) -> CNT_PAUSE_U2_R`[src]

Bit 5

`pub fn plus_cnt_rst_u2(&self) -> PLUS_CNT_RST_U2_R`[src]

Bit 4

`pub fn cnt_pause_u1(&self) -> CNT_PAUSE_U1_R`[src]

Bit 3

`pub fn plus_cnt_rst_u1(&self) -> PLUS_CNT_RST_U1_R`[src]

Bit 2

`pub fn cnt_pause_u0(&self) -> CNT_PAUSE_U0_R`[src]

Bit 1

`pub fn plus_cnt_rst_u0(&self) -> PLUS_CNT_RST_U0_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DATE>>`[src]

`pub fn date(&self) -> DATE_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _CH0CONF0>>`[src]

`pub fn clk_en(&self) -> CLK_EN_R`[src]

Bit 31

`pub fn mem_pd(&self) -> MEM_PD_R`[src]

Bit 30

`pub fn carrier_out_lv_ch0(&self) -> CARRIER_OUT_LV_CH0_R`[src]

Bit 29

`pub fn carrier_en_ch0(&self) -> CARRIER_EN_CH0_R`[src]

Bit 28

`pub fn mem_size_ch0(&self) -> MEM_SIZE_CH0_R`[src]

Bits 24:27

`pub fn idle_thres_ch0(&self) -> IDLE_THRES_CH0_R`[src]

Bits 8:23

`pub fn div_cnt_ch0(&self) -> DIV_CNT_CH0_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _CH0CONF1>>`[src]

`pub fn idle_out_en_ch0(&self) -> IDLE_OUT_EN_CH0_R`[src]

Bit 19

`pub fn idle_out_lv_ch0(&self) -> IDLE_OUT_LV_CH0_R`[src]

Bit 18

`pub fn ref_always_on_ch0(&self) -> REF_ALWAYS_ON_CH0_R`[src]

Bit 17

`pub fn ref_cnt_rst_ch0(&self) -> REF_CNT_RST_CH0_R`[src]

Bit 16

`pub fn rx_filter_thres_ch0(&self) -> RX_FILTER_THRES_CH0_R`[src]

Bits 8:15

`pub fn rx_filter_en_ch0(&self) -> RX_FILTER_EN_CH0_R`[src]

Bit 7

`pub fn tx_conti_mode_ch0(&self) -> TX_CONTI_MODE_CH0_R`[src]

Bit 6

`pub fn mem_owner_ch0(&self) -> MEM_OWNER_CH0_R`[src]

Bit 5

`pub fn apb_mem_rst_ch0(&self) -> APB_MEM_RST_CH0_R`[src]

Bit 4

`pub fn mem_rd_rst_ch0(&self) -> MEM_RD_RST_CH0_R`[src]

Bit 3

`pub fn mem_wr_rst_ch0(&self) -> MEM_WR_RST_CH0_R`[src]

Bit 2

`pub fn rx_en_ch0(&self) -> RX_EN_CH0_R`[src]

Bit 1

`pub fn tx_start_ch0(&self) -> TX_START_CH0_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CH1CONF0>>`[src]

`pub fn carrier_out_lv_ch1(&self) -> CARRIER_OUT_LV_CH1_R`[src]

Bit 29

`pub fn carrier_en_ch1(&self) -> CARRIER_EN_CH1_R`[src]

Bit 28

`pub fn mem_size_ch1(&self) -> MEM_SIZE_CH1_R`[src]

Bits 24:27

`pub fn idle_thres_ch1(&self) -> IDLE_THRES_CH1_R`[src]

Bits 8:23

`pub fn div_cnt_ch1(&self) -> DIV_CNT_CH1_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _CH1CONF1>>`[src]

`pub fn idle_out_en_ch1(&self) -> IDLE_OUT_EN_CH1_R`[src]

Bit 19

`pub fn idle_out_lv_ch1(&self) -> IDLE_OUT_LV_CH1_R`[src]

Bit 18

`pub fn ref_always_on_ch1(&self) -> REF_ALWAYS_ON_CH1_R`[src]

Bit 17

`pub fn ref_cnt_rst_ch1(&self) -> REF_CNT_RST_CH1_R`[src]

Bit 16

`pub fn rx_filter_thres_ch1(&self) -> RX_FILTER_THRES_CH1_R`[src]

Bits 8:15

`pub fn rx_filter_en_ch1(&self) -> RX_FILTER_EN_CH1_R`[src]

Bit 7

`pub fn tx_conti_mode_ch1(&self) -> TX_CONTI_MODE_CH1_R`[src]

Bit 6

`pub fn mem_owner_ch1(&self) -> MEM_OWNER_CH1_R`[src]

Bit 5

`pub fn apb_mem_rst_ch1(&self) -> APB_MEM_RST_CH1_R`[src]

Bit 4

`pub fn mem_rd_rst_ch1(&self) -> MEM_RD_RST_CH1_R`[src]

Bit 3

`pub fn mem_wr_rst_ch1(&self) -> MEM_WR_RST_CH1_R`[src]

Bit 2

`pub fn rx_en_ch1(&self) -> RX_EN_CH1_R`[src]

Bit 1

`pub fn tx_start_ch1(&self) -> TX_START_CH1_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CH2CONF0>>`[src]

`pub fn carrier_out_lv_ch2(&self) -> CARRIER_OUT_LV_CH2_R`[src]

Bit 29

`pub fn carrier_en_ch2(&self) -> CARRIER_EN_CH2_R`[src]

Bit 28

`pub fn mem_size_ch2(&self) -> MEM_SIZE_CH2_R`[src]

Bits 24:27

`pub fn idle_thres_ch2(&self) -> IDLE_THRES_CH2_R`[src]

Bits 8:23

`pub fn div_cnt_ch2(&self) -> DIV_CNT_CH2_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _CH2CONF1>>`[src]

`pub fn idle_out_en_ch2(&self) -> IDLE_OUT_EN_CH2_R`[src]

Bit 19

`pub fn idle_out_lv_ch2(&self) -> IDLE_OUT_LV_CH2_R`[src]

Bit 18

`pub fn ref_always_on_ch2(&self) -> REF_ALWAYS_ON_CH2_R`[src]

Bit 17

`pub fn ref_cnt_rst_ch2(&self) -> REF_CNT_RST_CH2_R`[src]

Bit 16

`pub fn rx_filter_thres_ch2(&self) -> RX_FILTER_THRES_CH2_R`[src]

Bits 8:15

`pub fn rx_filter_en_ch2(&self) -> RX_FILTER_EN_CH2_R`[src]

Bit 7

`pub fn tx_conti_mode_ch2(&self) -> TX_CONTI_MODE_CH2_R`[src]

Bit 6

`pub fn mem_owner_ch2(&self) -> MEM_OWNER_CH2_R`[src]

Bit 5

`pub fn apb_mem_rst_ch2(&self) -> APB_MEM_RST_CH2_R`[src]

Bit 4

`pub fn mem_rd_rst_ch2(&self) -> MEM_RD_RST_CH2_R`[src]

Bit 3

`pub fn mem_wr_rst_ch2(&self) -> MEM_WR_RST_CH2_R`[src]

Bit 2

`pub fn rx_en_ch2(&self) -> RX_EN_CH2_R`[src]

Bit 1

`pub fn tx_start_ch2(&self) -> TX_START_CH2_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CH3CONF0>>`[src]

`pub fn carrier_out_lv_ch3(&self) -> CARRIER_OUT_LV_CH3_R`[src]

Bit 29

`pub fn carrier_en_ch3(&self) -> CARRIER_EN_CH3_R`[src]

Bit 28

`pub fn mem_size_ch3(&self) -> MEM_SIZE_CH3_R`[src]

Bits 24:27

`pub fn idle_thres_ch3(&self) -> IDLE_THRES_CH3_R`[src]

Bits 8:23

`pub fn div_cnt_ch3(&self) -> DIV_CNT_CH3_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _CH3CONF1>>`[src]

`pub fn idle_out_en_ch3(&self) -> IDLE_OUT_EN_CH3_R`[src]

Bit 19

`pub fn idle_out_lv_ch3(&self) -> IDLE_OUT_LV_CH3_R`[src]

Bit 18

`pub fn ref_always_on_ch3(&self) -> REF_ALWAYS_ON_CH3_R`[src]

Bit 17

`pub fn ref_cnt_rst_ch3(&self) -> REF_CNT_RST_CH3_R`[src]

Bit 16

`pub fn rx_filter_thres_ch3(&self) -> RX_FILTER_THRES_CH3_R`[src]

Bits 8:15

`pub fn rx_filter_en_ch3(&self) -> RX_FILTER_EN_CH3_R`[src]

Bit 7

`pub fn tx_conti_mode_ch3(&self) -> TX_CONTI_MODE_CH3_R`[src]

Bit 6

`pub fn mem_owner_ch3(&self) -> MEM_OWNER_CH3_R`[src]

Bit 5

`pub fn apb_mem_rst_ch3(&self) -> APB_MEM_RST_CH3_R`[src]

Bit 4

`pub fn mem_rd_rst_ch3(&self) -> MEM_RD_RST_CH3_R`[src]

Bit 3

`pub fn mem_wr_rst_ch3(&self) -> MEM_WR_RST_CH3_R`[src]

Bit 2

`pub fn rx_en_ch3(&self) -> RX_EN_CH3_R`[src]

Bit 1

`pub fn tx_start_ch3(&self) -> TX_START_CH3_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CH4CONF0>>`[src]

`pub fn carrier_out_lv_ch4(&self) -> CARRIER_OUT_LV_CH4_R`[src]

Bit 29

`pub fn carrier_en_ch4(&self) -> CARRIER_EN_CH4_R`[src]

Bit 28

`pub fn mem_size_ch4(&self) -> MEM_SIZE_CH4_R`[src]

Bits 24:27

`pub fn idle_thres_ch4(&self) -> IDLE_THRES_CH4_R`[src]

Bits 8:23

`pub fn div_cnt_ch4(&self) -> DIV_CNT_CH4_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _CH4CONF1>>`[src]

`pub fn idle_out_en_ch4(&self) -> IDLE_OUT_EN_CH4_R`[src]

Bit 19

`pub fn idle_out_lv_ch4(&self) -> IDLE_OUT_LV_CH4_R`[src]

Bit 18

`pub fn ref_always_on_ch4(&self) -> REF_ALWAYS_ON_CH4_R`[src]

Bit 17

`pub fn ref_cnt_rst_ch4(&self) -> REF_CNT_RST_CH4_R`[src]

Bit 16

`pub fn rx_filter_thres_ch4(&self) -> RX_FILTER_THRES_CH4_R`[src]

Bits 8:15

`pub fn rx_filter_en_ch4(&self) -> RX_FILTER_EN_CH4_R`[src]

Bit 7

`pub fn tx_conti_mode_ch4(&self) -> TX_CONTI_MODE_CH4_R`[src]

Bit 6

`pub fn mem_owner_ch4(&self) -> MEM_OWNER_CH4_R`[src]

Bit 5

`pub fn apb_mem_rst_ch4(&self) -> APB_MEM_RST_CH4_R`[src]

Bit 4

`pub fn mem_rd_rst_ch4(&self) -> MEM_RD_RST_CH4_R`[src]

Bit 3

`pub fn mem_wr_rst_ch4(&self) -> MEM_WR_RST_CH4_R`[src]

Bit 2

`pub fn rx_en_ch4(&self) -> RX_EN_CH4_R`[src]

Bit 1

`pub fn tx_start_ch4(&self) -> TX_START_CH4_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CH5CONF0>>`[src]

`pub fn carrier_out_lv_ch5(&self) -> CARRIER_OUT_LV_CH5_R`[src]

Bit 29

`pub fn carrier_en_ch5(&self) -> CARRIER_EN_CH5_R`[src]

Bit 28

`pub fn mem_size_ch5(&self) -> MEM_SIZE_CH5_R`[src]

Bits 24:27

`pub fn idle_thres_ch5(&self) -> IDLE_THRES_CH5_R`[src]

Bits 8:23

`pub fn div_cnt_ch5(&self) -> DIV_CNT_CH5_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _CH5CONF1>>`[src]

`pub fn idle_out_en_ch5(&self) -> IDLE_OUT_EN_CH5_R`[src]

Bit 19

`pub fn idle_out_lv_ch5(&self) -> IDLE_OUT_LV_CH5_R`[src]

Bit 18

`pub fn ref_always_on_ch5(&self) -> REF_ALWAYS_ON_CH5_R`[src]

Bit 17

`pub fn ref_cnt_rst_ch5(&self) -> REF_CNT_RST_CH5_R`[src]

Bit 16

`pub fn rx_filter_thres_ch5(&self) -> RX_FILTER_THRES_CH5_R`[src]

Bits 8:15

`pub fn rx_filter_en_ch5(&self) -> RX_FILTER_EN_CH5_R`[src]

Bit 7

`pub fn tx_conti_mode_ch5(&self) -> TX_CONTI_MODE_CH5_R`[src]

Bit 6

`pub fn mem_owner_ch5(&self) -> MEM_OWNER_CH5_R`[src]

Bit 5

`pub fn apb_mem_rst_ch5(&self) -> APB_MEM_RST_CH5_R`[src]

Bit 4

`pub fn mem_rd_rst_ch5(&self) -> MEM_RD_RST_CH5_R`[src]

Bit 3

`pub fn mem_wr_rst_ch5(&self) -> MEM_WR_RST_CH5_R`[src]

Bit 2

`pub fn rx_en_ch5(&self) -> RX_EN_CH5_R`[src]

Bit 1

`pub fn tx_start_ch5(&self) -> TX_START_CH5_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CH6CONF0>>`[src]

`pub fn carrier_out_lv_ch6(&self) -> CARRIER_OUT_LV_CH6_R`[src]

Bit 29

`pub fn carrier_en_ch6(&self) -> CARRIER_EN_CH6_R`[src]

Bit 28

`pub fn mem_size_ch6(&self) -> MEM_SIZE_CH6_R`[src]

Bits 24:27

`pub fn idle_thres_ch6(&self) -> IDLE_THRES_CH6_R`[src]

Bits 8:23

`pub fn div_cnt_ch6(&self) -> DIV_CNT_CH6_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _CH6CONF1>>`[src]

`pub fn idle_out_en_ch6(&self) -> IDLE_OUT_EN_CH6_R`[src]

Bit 19

`pub fn idle_out_lv_ch6(&self) -> IDLE_OUT_LV_CH6_R`[src]

Bit 18

`pub fn ref_always_on_ch6(&self) -> REF_ALWAYS_ON_CH6_R`[src]

Bit 17

`pub fn ref_cnt_rst_ch6(&self) -> REF_CNT_RST_CH6_R`[src]

Bit 16

`pub fn rx_filter_thres_ch6(&self) -> RX_FILTER_THRES_CH6_R`[src]

Bits 8:15

`pub fn rx_filter_en_ch6(&self) -> RX_FILTER_EN_CH6_R`[src]

Bit 7

`pub fn tx_conti_mode_ch6(&self) -> TX_CONTI_MODE_CH6_R`[src]

Bit 6

`pub fn mem_owner_ch6(&self) -> MEM_OWNER_CH6_R`[src]

Bit 5

`pub fn apb_mem_rst_ch6(&self) -> APB_MEM_RST_CH6_R`[src]

Bit 4

`pub fn mem_rd_rst_ch6(&self) -> MEM_RD_RST_CH6_R`[src]

Bit 3

`pub fn mem_wr_rst_ch6(&self) -> MEM_WR_RST_CH6_R`[src]

Bit 2

`pub fn rx_en_ch6(&self) -> RX_EN_CH6_R`[src]

Bit 1

`pub fn tx_start_ch6(&self) -> TX_START_CH6_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CH7CONF0>>`[src]

`pub fn carrier_out_lv_ch7(&self) -> CARRIER_OUT_LV_CH7_R`[src]

Bit 29

`pub fn carrier_en_ch7(&self) -> CARRIER_EN_CH7_R`[src]

Bit 28

`pub fn mem_size_ch7(&self) -> MEM_SIZE_CH7_R`[src]

Bits 24:27

`pub fn idle_thres_ch7(&self) -> IDLE_THRES_CH7_R`[src]

Bits 8:23

`pub fn div_cnt_ch7(&self) -> DIV_CNT_CH7_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _CH7CONF1>>`[src]

`pub fn idle_out_en_ch7(&self) -> IDLE_OUT_EN_CH7_R`[src]

Bit 19

`pub fn idle_out_lv_ch7(&self) -> IDLE_OUT_LV_CH7_R`[src]

Bit 18

`pub fn ref_always_on_ch7(&self) -> REF_ALWAYS_ON_CH7_R`[src]

Bit 17

`pub fn ref_cnt_rst_ch7(&self) -> REF_CNT_RST_CH7_R`[src]

Bit 16

`pub fn rx_filter_thres_ch7(&self) -> RX_FILTER_THRES_CH7_R`[src]

Bits 8:15

`pub fn rx_filter_en_ch7(&self) -> RX_FILTER_EN_CH7_R`[src]

Bit 7

`pub fn tx_conti_mode_ch7(&self) -> TX_CONTI_MODE_CH7_R`[src]

Bit 6

`pub fn mem_owner_ch7(&self) -> MEM_OWNER_CH7_R`[src]

Bit 5

`pub fn apb_mem_rst_ch7(&self) -> APB_MEM_RST_CH7_R`[src]

Bit 4

`pub fn mem_rd_rst_ch7(&self) -> MEM_RD_RST_CH7_R`[src]

Bit 3

`pub fn mem_wr_rst_ch7(&self) -> MEM_WR_RST_CH7_R`[src]

Bit 2

`pub fn rx_en_ch7(&self) -> RX_EN_CH7_R`[src]

Bit 1

`pub fn tx_start_ch7(&self) -> TX_START_CH7_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CH0STATUS>>`[src]

`pub fn status_ch0(&self) -> STATUS_CH0_R`[src]

Bits 0:31

`pub fn apb_mem_rd_err_ch0(&self) -> APB_MEM_RD_ERR_CH0_R`[src]

Bit 31

`pub fn apb_mem_wr_err_ch0(&self) -> APB_MEM_WR_ERR_CH0_R`[src]

Bit 30

`pub fn mem_empty_ch0(&self) -> MEM_EMPTY_CH0_R`[src]

Bit 29

`pub fn mem_full_ch0(&self) -> MEM_FULL_CH0_R`[src]

Bit 28

`pub fn mem_owner_err_ch0(&self) -> MEM_OWNER_ERR_CH0_R`[src]

Bit 27

`pub fn state_ch0(&self) -> STATE_CH0_R`[src]

Bits 24:26

`pub fn mem_raddr_ex_ch0(&self) -> MEM_RADDR_EX_CH0_R`[src]

Bits 12:21

`pub fn mem_waddr_ex_ch0(&self) -> MEM_WADDR_EX_CH0_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _CH1STATUS>>`[src]

`pub fn status_ch1(&self) -> STATUS_CH1_R`[src]

Bits 0:31

`pub fn apb_mem_rd_err_ch1(&self) -> APB_MEM_RD_ERR_CH1_R`[src]

Bit 31

`pub fn apb_mem_wr_err_ch1(&self) -> APB_MEM_WR_ERR_CH1_R`[src]

Bit 30

`pub fn mem_empty_ch1(&self) -> MEM_EMPTY_CH1_R`[src]

Bit 29

`pub fn mem_full_ch1(&self) -> MEM_FULL_CH1_R`[src]

Bit 28

`pub fn mem_owner_err_ch1(&self) -> MEM_OWNER_ERR_CH1_R`[src]

Bit 27

`pub fn state_ch1(&self) -> STATE_CH1_R`[src]

Bits 24:26

`pub fn mem_raddr_ex_ch1(&self) -> MEM_RADDR_EX_CH1_R`[src]

Bits 12:21

`pub fn mem_waddr_ex_ch1(&self) -> MEM_WADDR_EX_CH1_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _CH2STATUS>>`[src]

`pub fn status_ch2(&self) -> STATUS_CH2_R`[src]

Bits 0:31

`pub fn apb_mem_rd_err_ch2(&self) -> APB_MEM_RD_ERR_CH2_R`[src]

Bit 31

`pub fn apb_mem_wr_err_ch2(&self) -> APB_MEM_WR_ERR_CH2_R`[src]

Bit 30

`pub fn mem_empty_ch2(&self) -> MEM_EMPTY_CH2_R`[src]

Bit 29

`pub fn mem_full_ch2(&self) -> MEM_FULL_CH2_R`[src]

Bit 28

`pub fn mem_owner_err_ch2(&self) -> MEM_OWNER_ERR_CH2_R`[src]

Bit 27

`pub fn state_ch2(&self) -> STATE_CH2_R`[src]

Bits 24:26

`pub fn mem_raddr_ex_ch2(&self) -> MEM_RADDR_EX_CH2_R`[src]

Bits 12:21

`pub fn mem_waddr_ex_ch2(&self) -> MEM_WADDR_EX_CH2_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _CH3STATUS>>`[src]

`pub fn status_ch3(&self) -> STATUS_CH3_R`[src]

Bits 0:31

`pub fn apb_mem_rd_err_ch3(&self) -> APB_MEM_RD_ERR_CH3_R`[src]

Bit 31

`pub fn apb_mem_wr_err_ch3(&self) -> APB_MEM_WR_ERR_CH3_R`[src]

Bit 30

`pub fn mem_empty_ch3(&self) -> MEM_EMPTY_CH3_R`[src]

Bit 29

`pub fn mem_full_ch3(&self) -> MEM_FULL_CH3_R`[src]

Bit 28

`pub fn mem_owner_err_ch3(&self) -> MEM_OWNER_ERR_CH3_R`[src]

Bit 27

`pub fn state_ch3(&self) -> STATE_CH3_R`[src]

Bits 24:26

`pub fn mem_raddr_ex_ch3(&self) -> MEM_RADDR_EX_CH3_R`[src]

Bits 12:21

`pub fn mem_waddr_ex_ch3(&self) -> MEM_WADDR_EX_CH3_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _CH4STATUS>>`[src]

`pub fn status_ch4(&self) -> STATUS_CH4_R`[src]

Bits 0:31

`pub fn apb_mem_rd_err_ch4(&self) -> APB_MEM_RD_ERR_CH4_R`[src]

Bit 31

`pub fn apb_mem_wr_err_ch4(&self) -> APB_MEM_WR_ERR_CH4_R`[src]

Bit 30

`pub fn mem_empty_ch4(&self) -> MEM_EMPTY_CH4_R`[src]

Bit 29

`pub fn mem_full_ch4(&self) -> MEM_FULL_CH4_R`[src]

Bit 28

`pub fn mem_owner_err_ch4(&self) -> MEM_OWNER_ERR_CH4_R`[src]

Bit 27

`pub fn state_ch4(&self) -> STATE_CH4_R`[src]

Bits 24:26

`pub fn mem_raddr_ex_ch4(&self) -> MEM_RADDR_EX_CH4_R`[src]

Bits 12:21

`pub fn mem_waddr_ex_ch4(&self) -> MEM_WADDR_EX_CH4_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _CH5STATUS>>`[src]

`pub fn status_ch5(&self) -> STATUS_CH5_R`[src]

Bits 0:31

`pub fn apb_mem_rd_err_ch5(&self) -> APB_MEM_RD_ERR_CH5_R`[src]

Bit 31

`pub fn apb_mem_wr_err_ch5(&self) -> APB_MEM_WR_ERR_CH5_R`[src]

Bit 30

`pub fn mem_empty_ch5(&self) -> MEM_EMPTY_CH5_R`[src]

Bit 29

`pub fn mem_full_ch5(&self) -> MEM_FULL_CH5_R`[src]

Bit 28

`pub fn mem_owner_err_ch5(&self) -> MEM_OWNER_ERR_CH5_R`[src]

Bit 27

`pub fn state_ch5(&self) -> STATE_CH5_R`[src]

Bits 24:26

`pub fn mem_raddr_ex_ch5(&self) -> MEM_RADDR_EX_CH5_R`[src]

Bits 12:21

`pub fn mem_waddr_ex_ch5(&self) -> MEM_WADDR_EX_CH5_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _CH6STATUS>>`[src]

`pub fn status_ch6(&self) -> STATUS_CH6_R`[src]

Bits 0:31

`pub fn apb_mem_rd_err_ch6(&self) -> APB_MEM_RD_ERR_CH6_R`[src]

Bit 31

`pub fn apb_mem_wr_err_ch6(&self) -> APB_MEM_WR_ERR_CH6_R`[src]

Bit 30

`pub fn mem_empty_ch6(&self) -> MEM_EMPTY_CH6_R`[src]

Bit 29

`pub fn mem_full_ch6(&self) -> MEM_FULL_CH6_R`[src]

Bit 28

`pub fn mem_owner_err_ch6(&self) -> MEM_OWNER_ERR_CH6_R`[src]

Bit 27

`pub fn state_ch6(&self) -> STATE_CH6_R`[src]

Bits 24:26

`pub fn mem_raddr_ex_ch6(&self) -> MEM_RADDR_EX_CH6_R`[src]

Bits 12:21

`pub fn mem_waddr_ex_ch6(&self) -> MEM_WADDR_EX_CH6_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _CH7STATUS>>`[src]

`pub fn status_ch7(&self) -> STATUS_CH7_R`[src]

Bits 0:31

`pub fn apb_mem_rd_err_ch7(&self) -> APB_MEM_RD_ERR_CH7_R`[src]

Bit 31

`pub fn apb_mem_wr_err_ch7(&self) -> APB_MEM_WR_ERR_CH7_R`[src]

Bit 30

`pub fn mem_empty_ch7(&self) -> MEM_EMPTY_CH7_R`[src]

Bit 29

`pub fn mem_full_ch7(&self) -> MEM_FULL_CH7_R`[src]

Bit 28

`pub fn mem_owner_err_ch7(&self) -> MEM_OWNER_ERR_CH7_R`[src]

Bit 27

`pub fn state_ch7(&self) -> STATE_CH7_R`[src]

Bits 24:26

`pub fn mem_raddr_ex_ch7(&self) -> MEM_RADDR_EX_CH7_R`[src]

Bits 12:21

`pub fn mem_waddr_ex_ch7(&self) -> MEM_WADDR_EX_CH7_R`[src]

`pub fn ch5_tx_thr_event_int_raw(&self) -> CH5_TX_THR_EVENT_INT_RAW_R`[src]

Bit 29

`pub fn ch4_tx_thr_event_int_raw(&self) -> CH4_TX_THR_EVENT_INT_RAW_R`[src]

Bit 28

`pub fn ch3_tx_thr_event_int_raw(&self) -> CH3_TX_THR_EVENT_INT_RAW_R`[src]

Bit 27

`pub fn ch2_tx_thr_event_int_raw(&self) -> CH2_TX_THR_EVENT_INT_RAW_R`[src]

Bit 26

`pub fn ch1_tx_thr_event_int_raw(&self) -> CH1_TX_THR_EVENT_INT_RAW_R`[src]

Bit 25

`pub fn ch0_tx_thr_event_int_raw(&self) -> CH0_TX_THR_EVENT_INT_RAW_R`[src]

Bit 24

`pub fn ch7_err_int_raw(&self) -> CH7_ERR_INT_RAW_R`[src]

Bit 23

`pub fn ch7_rx_end_int_raw(&self) -> CH7_RX_END_INT_RAW_R`[src]

Bit 22

`pub fn ch7_tx_end_int_raw(&self) -> CH7_TX_END_INT_RAW_R`[src]

Bit 21

`pub fn ch6_err_int_raw(&self) -> CH6_ERR_INT_RAW_R`[src]

Bit 20

`pub fn ch6_rx_end_int_raw(&self) -> CH6_RX_END_INT_RAW_R`[src]

Bit 19

`pub fn ch6_tx_end_int_raw(&self) -> CH6_TX_END_INT_RAW_R`[src]

Bit 18

`pub fn ch5_err_int_raw(&self) -> CH5_ERR_INT_RAW_R`[src]

Bit 17

`pub fn ch5_rx_end_int_raw(&self) -> CH5_RX_END_INT_RAW_R`[src]

Bit 16

`pub fn ch5_tx_end_int_raw(&self) -> CH5_TX_END_INT_RAW_R`[src]

Bit 15

`pub fn ch4_err_int_raw(&self) -> CH4_ERR_INT_RAW_R`[src]

Bit 14

`pub fn ch4_rx_end_int_raw(&self) -> CH4_RX_END_INT_RAW_R`[src]

Bit 13

`pub fn ch4_tx_end_int_raw(&self) -> CH4_TX_END_INT_RAW_R`[src]

Bit 12

`pub fn ch3_err_int_raw(&self) -> CH3_ERR_INT_RAW_R`[src]

Bit 11

`pub fn ch3_rx_end_int_raw(&self) -> CH3_RX_END_INT_RAW_R`[src]

Bit 10

`pub fn ch3_tx_end_int_raw(&self) -> CH3_TX_END_INT_RAW_R`[src]

Bit 9

`pub fn ch2_err_int_raw(&self) -> CH2_ERR_INT_RAW_R`[src]

Bit 8

`pub fn ch2_rx_end_int_raw(&self) -> CH2_RX_END_INT_RAW_R`[src]

Bit 7

`pub fn ch2_tx_end_int_raw(&self) -> CH2_TX_END_INT_RAW_R`[src]

Bit 6

`pub fn ch1_err_int_raw(&self) -> CH1_ERR_INT_RAW_R`[src]

Bit 5

`pub fn ch1_rx_end_int_raw(&self) -> CH1_RX_END_INT_RAW_R`[src]

Bit 4

`pub fn ch1_tx_end_int_raw(&self) -> CH1_TX_END_INT_RAW_R`[src]

Bit 3

`pub fn ch0_err_int_raw(&self) -> CH0_ERR_INT_RAW_R`[src]

Bit 2

`pub fn ch0_rx_end_int_raw(&self) -> CH0_RX_END_INT_RAW_R`[src]

Bit 1

`pub fn ch0_tx_end_int_raw(&self) -> CH0_TX_END_INT_RAW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_ST>>`[src]

`pub fn ch7_tx_thr_event_int_st(&self) -> CH7_TX_THR_EVENT_INT_ST_R`[src]

Bit 31

`pub fn ch6_tx_thr_event_int_st(&self) -> CH6_TX_THR_EVENT_INT_ST_R`[src]

Bit 30

`pub fn ch5_tx_thr_event_int_st(&self) -> CH5_TX_THR_EVENT_INT_ST_R`[src]

Bit 29

`pub fn ch4_tx_thr_event_int_st(&self) -> CH4_TX_THR_EVENT_INT_ST_R`[src]

Bit 28

`pub fn ch3_tx_thr_event_int_st(&self) -> CH3_TX_THR_EVENT_INT_ST_R`[src]

Bit 27

`pub fn ch2_tx_thr_event_int_st(&self) -> CH2_TX_THR_EVENT_INT_ST_R`[src]

Bit 26

`pub fn ch1_tx_thr_event_int_st(&self) -> CH1_TX_THR_EVENT_INT_ST_R`[src]

Bit 25

`pub fn ch0_tx_thr_event_int_st(&self) -> CH0_TX_THR_EVENT_INT_ST_R`[src]

Bit 24

`pub fn ch7_err_int_st(&self) -> CH7_ERR_INT_ST_R`[src]

Bit 23

`pub fn ch7_rx_end_int_st(&self) -> CH7_RX_END_INT_ST_R`[src]

Bit 22

`pub fn ch7_tx_end_int_st(&self) -> CH7_TX_END_INT_ST_R`[src]

Bit 21

`pub fn ch6_err_int_st(&self) -> CH6_ERR_INT_ST_R`[src]

Bit 20

`pub fn ch6_rx_end_int_st(&self) -> CH6_RX_END_INT_ST_R`[src]

Bit 19

`pub fn ch6_tx_end_int_st(&self) -> CH6_TX_END_INT_ST_R`[src]

Bit 18

`pub fn ch5_err_int_st(&self) -> CH5_ERR_INT_ST_R`[src]

Bit 17

`pub fn ch5_rx_end_int_st(&self) -> CH5_RX_END_INT_ST_R`[src]

Bit 16

`pub fn ch5_tx_end_int_st(&self) -> CH5_TX_END_INT_ST_R`[src]

Bit 15

`pub fn ch4_err_int_st(&self) -> CH4_ERR_INT_ST_R`[src]

Bit 14

`pub fn ch4_rx_end_int_st(&self) -> CH4_RX_END_INT_ST_R`[src]

Bit 13

`pub fn ch4_tx_end_int_st(&self) -> CH4_TX_END_INT_ST_R`[src]

Bit 12

`pub fn ch3_err_int_st(&self) -> CH3_ERR_INT_ST_R`[src]

Bit 11

`pub fn ch3_rx_end_int_st(&self) -> CH3_RX_END_INT_ST_R`[src]

Bit 10

`pub fn ch3_tx_end_int_st(&self) -> CH3_TX_END_INT_ST_R`[src]

Bit 9

`pub fn ch2_err_int_st(&self) -> CH2_ERR_INT_ST_R`[src]

Bit 8

`pub fn ch2_rx_end_int_st(&self) -> CH2_RX_END_INT_ST_R`[src]

Bit 7

`pub fn ch2_tx_end_int_st(&self) -> CH2_TX_END_INT_ST_R`[src]

Bit 6

`pub fn ch1_err_int_st(&self) -> CH1_ERR_INT_ST_R`[src]

Bit 5

`pub fn ch1_rx_end_int_st(&self) -> CH1_RX_END_INT_ST_R`[src]

Bit 4

`pub fn ch1_tx_end_int_st(&self) -> CH1_TX_END_INT_ST_R`[src]

Bit 3

`pub fn ch0_err_int_st(&self) -> CH0_ERR_INT_ST_R`[src]

Bit 2

`pub fn ch0_rx_end_int_st(&self) -> CH0_RX_END_INT_ST_R`[src]

Bit 1

`pub fn ch0_tx_end_int_st(&self) -> CH0_TX_END_INT_ST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_ENA>>`[src]

`pub fn ch7_tx_thr_event_int_ena(&self) -> CH7_TX_THR_EVENT_INT_ENA_R`[src]

Bit 31

`pub fn ch6_tx_thr_event_int_ena(&self) -> CH6_TX_THR_EVENT_INT_ENA_R`[src]

Bit 30

`pub fn ch5_tx_thr_event_int_ena(&self) -> CH5_TX_THR_EVENT_INT_ENA_R`[src]

Bit 29

`pub fn ch4_tx_thr_event_int_ena(&self) -> CH4_TX_THR_EVENT_INT_ENA_R`[src]

Bit 28

`pub fn ch3_tx_thr_event_int_ena(&self) -> CH3_TX_THR_EVENT_INT_ENA_R`[src]

Bit 27

`pub fn ch2_tx_thr_event_int_ena(&self) -> CH2_TX_THR_EVENT_INT_ENA_R`[src]

Bit 26

`pub fn ch1_tx_thr_event_int_ena(&self) -> CH1_TX_THR_EVENT_INT_ENA_R`[src]

Bit 25

`pub fn ch0_tx_thr_event_int_ena(&self) -> CH0_TX_THR_EVENT_INT_ENA_R`[src]

Bit 24

`pub fn ch7_err_int_ena(&self) -> CH7_ERR_INT_ENA_R`[src]

Bit 23

`pub fn ch7_rx_end_int_ena(&self) -> CH7_RX_END_INT_ENA_R`[src]

Bit 22

`pub fn ch7_tx_end_int_ena(&self) -> CH7_TX_END_INT_ENA_R`[src]

Bit 21

`pub fn ch6_err_int_ena(&self) -> CH6_ERR_INT_ENA_R`[src]

Bit 20

`pub fn ch6_rx_end_int_ena(&self) -> CH6_RX_END_INT_ENA_R`[src]

Bit 19

`pub fn ch6_tx_end_int_ena(&self) -> CH6_TX_END_INT_ENA_R`[src]

Bit 18

`pub fn ch5_err_int_ena(&self) -> CH5_ERR_INT_ENA_R`[src]

Bit 17

`pub fn ch5_rx_end_int_ena(&self) -> CH5_RX_END_INT_ENA_R`[src]

Bit 16

`pub fn ch5_tx_end_int_ena(&self) -> CH5_TX_END_INT_ENA_R`[src]

Bit 15

`pub fn ch4_err_int_ena(&self) -> CH4_ERR_INT_ENA_R`[src]

Bit 14

`pub fn ch4_rx_end_int_ena(&self) -> CH4_RX_END_INT_ENA_R`[src]

Bit 13

`pub fn ch4_tx_end_int_ena(&self) -> CH4_TX_END_INT_ENA_R`[src]

Bit 12

`pub fn ch3_err_int_ena(&self) -> CH3_ERR_INT_ENA_R`[src]

Bit 11

`pub fn ch3_rx_end_int_ena(&self) -> CH3_RX_END_INT_ENA_R`[src]

Bit 10

`pub fn ch3_tx_end_int_ena(&self) -> CH3_TX_END_INT_ENA_R`[src]

Bit 9

`pub fn ch2_err_int_ena(&self) -> CH2_ERR_INT_ENA_R`[src]

Bit 8

`pub fn ch2_rx_end_int_ena(&self) -> CH2_RX_END_INT_ENA_R`[src]

Bit 7

`pub fn ch2_tx_end_int_ena(&self) -> CH2_TX_END_INT_ENA_R`[src]

Bit 6

`pub fn ch1_err_int_ena(&self) -> CH1_ERR_INT_ENA_R`[src]

Bit 5

`pub fn ch1_rx_end_int_ena(&self) -> CH1_RX_END_INT_ENA_R`[src]

Bit 4

`pub fn ch1_tx_end_int_ena(&self) -> CH1_TX_END_INT_ENA_R`[src]

Bit 3

`pub fn ch0_err_int_ena(&self) -> CH0_ERR_INT_ENA_R`[src]

Bit 2

`pub fn ch0_rx_end_int_ena(&self) -> CH0_RX_END_INT_ENA_R`[src]

Bit 1

`pub fn ch0_tx_end_int_ena(&self) -> CH0_TX_END_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_CLR>>`[src]

`pub fn ch7_tx_thr_event_int_clr(&self) -> CH7_TX_THR_EVENT_INT_CLR_R`[src]

Bit 31

`pub fn ch6_tx_thr_event_int_clr(&self) -> CH6_TX_THR_EVENT_INT_CLR_R`[src]

Bit 30

`pub fn ch5_tx_thr_event_int_clr(&self) -> CH5_TX_THR_EVENT_INT_CLR_R`[src]

Bit 29

`pub fn ch4_tx_thr_event_int_clr(&self) -> CH4_TX_THR_EVENT_INT_CLR_R`[src]

Bit 28

`pub fn ch3_tx_thr_event_int_clr(&self) -> CH3_TX_THR_EVENT_INT_CLR_R`[src]

Bit 27

`pub fn ch2_tx_thr_event_int_clr(&self) -> CH2_TX_THR_EVENT_INT_CLR_R`[src]

Bit 26

`pub fn ch1_tx_thr_event_int_clr(&self) -> CH1_TX_THR_EVENT_INT_CLR_R`[src]

Bit 25

`pub fn ch0_tx_thr_event_int_clr(&self) -> CH0_TX_THR_EVENT_INT_CLR_R`[src]

Bit 24

`pub fn ch7_err_int_clr(&self) -> CH7_ERR_INT_CLR_R`[src]

Bit 23

`pub fn ch7_rx_end_int_clr(&self) -> CH7_RX_END_INT_CLR_R`[src]

Bit 22

`pub fn ch7_tx_end_int_clr(&self) -> CH7_TX_END_INT_CLR_R`[src]

Bit 21

`pub fn ch6_err_int_clr(&self) -> CH6_ERR_INT_CLR_R`[src]

Bit 20

`pub fn ch6_rx_end_int_clr(&self) -> CH6_RX_END_INT_CLR_R`[src]

Bit 19

`pub fn ch6_tx_end_int_clr(&self) -> CH6_TX_END_INT_CLR_R`[src]

Bit 18

`pub fn ch5_err_int_clr(&self) -> CH5_ERR_INT_CLR_R`[src]

Bit 17

`pub fn ch5_rx_end_int_clr(&self) -> CH5_RX_END_INT_CLR_R`[src]

Bit 16

`pub fn ch5_tx_end_int_clr(&self) -> CH5_TX_END_INT_CLR_R`[src]

Bit 15

`pub fn ch4_err_int_clr(&self) -> CH4_ERR_INT_CLR_R`[src]

Bit 14

`pub fn ch4_rx_end_int_clr(&self) -> CH4_RX_END_INT_CLR_R`[src]

Bit 13

`pub fn ch4_tx_end_int_clr(&self) -> CH4_TX_END_INT_CLR_R`[src]

Bit 12

`pub fn ch3_err_int_clr(&self) -> CH3_ERR_INT_CLR_R`[src]

Bit 11

`pub fn ch3_rx_end_int_clr(&self) -> CH3_RX_END_INT_CLR_R`[src]

Bit 10

`pub fn ch3_tx_end_int_clr(&self) -> CH3_TX_END_INT_CLR_R`[src]

Bit 9

`pub fn ch2_err_int_clr(&self) -> CH2_ERR_INT_CLR_R`[src]

Bit 8

`pub fn ch2_rx_end_int_clr(&self) -> CH2_RX_END_INT_CLR_R`[src]

Bit 7

`pub fn ch2_tx_end_int_clr(&self) -> CH2_TX_END_INT_CLR_R`[src]

Bit 6

`pub fn ch1_err_int_clr(&self) -> CH1_ERR_INT_CLR_R`[src]

Bit 5

`pub fn ch1_rx_end_int_clr(&self) -> CH1_RX_END_INT_CLR_R`[src]

Bit 4

`pub fn ch1_tx_end_int_clr(&self) -> CH1_TX_END_INT_CLR_R`[src]

Bit 3

`pub fn ch0_err_int_clr(&self) -> CH0_ERR_INT_CLR_R`[src]

`impl R<u32, Reg<u32, _CH7CARRIER_DUTY>>`[src]

`pub fn carrier_high_ch7(&self) -> CARRIER_HIGH_CH7_R`[src]

`pub fn config(&self) -> CONFIG_R`[src]

Bits 11:12

`pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R`[src]

Bit 10

`pub fn int_type(&self) -> INT_TYPE_R`[src]

Bits 7:9

`pub fn pad_driver(&self) -> PAD_DRIVER_R`[src]

Bit 2

`impl R<u32, Reg<u32, _CALI_CONF>>`[src]

`pub fn cali_start(&self) -> CALI_START_R`[src]

Bit 31

`pub fn cali_rtc_max(&self) -> CALI_RTC_MAX_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _CALI_DATA>>`[src]

`pub fn cali_rdy_sync2(&self) -> CALI_RDY_SYNC2_R`[src]

Bit 31

`pub fn cali_rdy_real(&self) -> CALI_RDY_REAL_R`[src]

Bit 30

`pub fn cali_value_sync2(&self) -> CALI_VALUE_SYNC2_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _FUNC_IN_SEL_CFG>>`[src]

`pub fn sel(&self) -> SEL_R`[src]

Bit 7

`pub fn in_inv_sel(&self) -> IN_INV_SEL_R`[src]

Bit 6

`pub fn in_sel(&self) -> IN_SEL_R`[src]

Bits 0:5

`impl R<u32, Reg<u32, _FUNC_OUT_SEL_CFG>>`[src]

`pub fn oen_inv_sel(&self) -> OEN_INV_SEL_R`[src]

Bit 11

`pub fn oen_sel(&self) -> OEN_SEL_R`[src]

Bit 10

`pub fn out_inv_sel(&self) -> OUT_INV_SEL_R`[src]

Bit 9

`pub fn out_sel(&self) -> OUT_SEL_R`[src]

Bits 0:8

`impl R<u32, Reg<u32, _CONF0>>`[src]

`pub fn uart_rx_brk_eof_en(&self) -> UART_RX_BRK_EOF_EN_R`[src]

Bit 23

`pub fn clk_en(&self) -> CLK_EN_R`[src]

Bit 22

`pub fn encode_crc_en(&self) -> ENCODE_CRC_EN_R`[src]

Bit 21

`pub fn len_eof_en(&self) -> LEN_EOF_EN_R`[src]

Bit 20

`pub fn uart_idle_eof_en(&self) -> UART_IDLE_EOF_EN_R`[src]

Bit 19

`pub fn crc_rec_en(&self) -> CRC_REC_EN_R`[src]

Bit 18

`pub fn head_en(&self) -> HEAD_EN_R`[src]

Bit 17

`pub fn seper_en(&self) -> SEPER_EN_R`[src]

Bit 16

`pub fn mem_trans_en(&self) -> MEM_TRANS_EN_R`[src]

Bit 15

`pub fn out_data_burst_en(&self) -> OUT_DATA_BURST_EN_R`[src]

Bit 14

`pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R`[src]

Bit 13

`pub fn outdscr_burst_en(&self) -> OUTDSCR_BURST_EN_R`[src]

Bit 12

`pub fn uart2_ce(&self) -> UART2_CE_R`[src]

Bit 11

`pub fn uart1_ce(&self) -> UART1_CE_R`[src]

Bit 10

`pub fn uart0_ce(&self) -> UART0_CE_R`[src]

Bit 9

`pub fn out_eof_mode(&self) -> OUT_EOF_MODE_R`[src]

Bit 8

`pub fn out_no_restart_clr(&self) -> OUT_NO_RESTART_CLR_R`[src]

Bit 7

`pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R`[src]

Bit 6

`pub fn out_loop_test(&self) -> OUT_LOOP_TEST_R`[src]

Bit 5

`pub fn in_loop_test(&self) -> IN_LOOP_TEST_R`[src]

Bit 4

`pub fn ahbm_rst(&self) -> AHBM_RST_R`[src]

Bit 3

`pub fn ahbm_fifo_rst(&self) -> AHBM_FIFO_RST_R`[src]

Bit 2

`pub fn out_rst(&self) -> OUT_RST_R`[src]

Bit 1

`pub fn in_rst(&self) -> IN_RST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_RAW>>`[src]

`pub fn dma_infifo_full_wm_int_raw(&self) -> DMA_INFIFO_FULL_WM_INT_RAW_R`[src]

Bit 16

`pub fn send_a_q_int_raw(&self) -> SEND_A_Q_INT_RAW_R`[src]

Bit 15

`pub fn send_s_q_int_raw(&self) -> SEND_S_Q_INT_RAW_R`[src]

Bit 14

`pub fn out_total_eof_int_raw(&self) -> OUT_TOTAL_EOF_INT_RAW_R`[src]

Bit 13

`pub fn outlink_eof_err_int_raw(&self) -> OUTLINK_EOF_ERR_INT_RAW_R`[src]

Bit 12

`pub fn in_dscr_empty_int_raw(&self) -> IN_DSCR_EMPTY_INT_RAW_R`[src]

Bit 11

`pub fn out_dscr_err_int_raw(&self) -> OUT_DSCR_ERR_INT_RAW_R`[src]

Bit 10

`pub fn in_dscr_err_int_raw(&self) -> IN_DSCR_ERR_INT_RAW_R`[src]

Bit 9

`pub fn out_eof_int_raw(&self) -> OUT_EOF_INT_RAW_R`[src]

Bit 8

`pub fn out_done_int_raw(&self) -> OUT_DONE_INT_RAW_R`[src]

Bit 7

`pub fn in_err_eof_int_raw(&self) -> IN_ERR_EOF_INT_RAW_R`[src]

Bit 6

`pub fn in_suc_eof_int_raw(&self) -> IN_SUC_EOF_INT_RAW_R`[src]

Bit 5

`pub fn in_done_int_raw(&self) -> IN_DONE_INT_RAW_R`[src]

Bit 4

`pub fn tx_hung_int_raw(&self) -> TX_HUNG_INT_RAW_R`[src]

Bit 3

`pub fn rx_hung_int_raw(&self) -> RX_HUNG_INT_RAW_R`[src]

Bit 2

`pub fn tx_start_int_raw(&self) -> TX_START_INT_RAW_R`[src]

Bit 1

`pub fn rx_start_int_raw(&self) -> RX_START_INT_RAW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_ST>>`[src]

`pub fn dma_infifo_full_wm_int_st(&self) -> DMA_INFIFO_FULL_WM_INT_ST_R`[src]

Bit 16

`pub fn send_a_q_int_st(&self) -> SEND_A_Q_INT_ST_R`[src]

Bit 15

`pub fn send_s_q_int_st(&self) -> SEND_S_Q_INT_ST_R`[src]

Bit 14

`pub fn out_total_eof_int_st(&self) -> OUT_TOTAL_EOF_INT_ST_R`[src]

Bit 13

`pub fn outlink_eof_err_int_st(&self) -> OUTLINK_EOF_ERR_INT_ST_R`[src]

Bit 12

`pub fn in_dscr_empty_int_st(&self) -> IN_DSCR_EMPTY_INT_ST_R`[src]

Bit 11

`pub fn out_dscr_err_int_st(&self) -> OUT_DSCR_ERR_INT_ST_R`[src]

Bit 10

`pub fn in_dscr_err_int_st(&self) -> IN_DSCR_ERR_INT_ST_R`[src]

Bit 9

`pub fn out_eof_int_st(&self) -> OUT_EOF_INT_ST_R`[src]

Bit 8

`pub fn out_done_int_st(&self) -> OUT_DONE_INT_ST_R`[src]

Bit 7

`pub fn in_err_eof_int_st(&self) -> IN_ERR_EOF_INT_ST_R`[src]

Bit 6

`pub fn in_suc_eof_int_st(&self) -> IN_SUC_EOF_INT_ST_R`[src]

Bit 5

`pub fn in_done_int_st(&self) -> IN_DONE_INT_ST_R`[src]

Bit 4

`pub fn tx_hung_int_st(&self) -> TX_HUNG_INT_ST_R`[src]

Bit 3

`pub fn rx_hung_int_st(&self) -> RX_HUNG_INT_ST_R`[src]

Bit 2

`pub fn tx_start_int_st(&self) -> TX_START_INT_ST_R`[src]

Bit 1

`pub fn rx_start_int_st(&self) -> RX_START_INT_ST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_ENA>>`[src]

`pub fn dma_infifo_full_wm_int_ena(&self) -> DMA_INFIFO_FULL_WM_INT_ENA_R`[src]

Bit 16

`pub fn send_a_q_int_ena(&self) -> SEND_A_Q_INT_ENA_R`[src]

Bit 15

`pub fn send_s_q_int_ena(&self) -> SEND_S_Q_INT_ENA_R`[src]

Bit 14

`pub fn out_total_eof_int_ena(&self) -> OUT_TOTAL_EOF_INT_ENA_R`[src]

Bit 13

`pub fn outlink_eof_err_int_ena(&self) -> OUTLINK_EOF_ERR_INT_ENA_R`[src]

Bit 12

`pub fn in_dscr_empty_int_ena(&self) -> IN_DSCR_EMPTY_INT_ENA_R`[src]

Bit 11

`pub fn out_dscr_err_int_ena(&self) -> OUT_DSCR_ERR_INT_ENA_R`[src]

Bit 10

`pub fn in_dscr_err_int_ena(&self) -> IN_DSCR_ERR_INT_ENA_R`[src]

Bit 9

`pub fn out_eof_int_ena(&self) -> OUT_EOF_INT_ENA_R`[src]

Bit 8

`pub fn out_done_int_ena(&self) -> OUT_DONE_INT_ENA_R`[src]

Bit 7

`pub fn in_err_eof_int_ena(&self) -> IN_ERR_EOF_INT_ENA_R`[src]

Bit 6

`pub fn in_suc_eof_int_ena(&self) -> IN_SUC_EOF_INT_ENA_R`[src]

Bit 5

`pub fn in_done_int_ena(&self) -> IN_DONE_INT_ENA_R`[src]

Bit 4

`pub fn tx_hung_int_ena(&self) -> TX_HUNG_INT_ENA_R`[src]

Bit 3

`pub fn rx_hung_int_ena(&self) -> RX_HUNG_INT_ENA_R`[src]

Bit 2

`pub fn tx_start_int_ena(&self) -> TX_START_INT_ENA_R`[src]

Bit 1

`pub fn rx_start_int_ena(&self) -> RX_START_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_CLR>>`[src]

`pub fn dma_infifo_full_wm_int_clr(&self) -> DMA_INFIFO_FULL_WM_INT_CLR_R`[src]

Bit 16

`pub fn send_a_q_int_clr(&self) -> SEND_A_Q_INT_CLR_R`[src]

Bit 15

`pub fn send_s_q_int_clr(&self) -> SEND_S_Q_INT_CLR_R`[src]

Bit 14

`pub fn out_total_eof_int_clr(&self) -> OUT_TOTAL_EOF_INT_CLR_R`[src]

Bit 13

`pub fn outlink_eof_err_int_clr(&self) -> OUTLINK_EOF_ERR_INT_CLR_R`[src]

Bit 12

`pub fn in_dscr_empty_int_clr(&self) -> IN_DSCR_EMPTY_INT_CLR_R`[src]

Bit 11

`pub fn out_dscr_err_int_clr(&self) -> OUT_DSCR_ERR_INT_CLR_R`[src]

Bit 10

`pub fn in_dscr_err_int_clr(&self) -> IN_DSCR_ERR_INT_CLR_R`[src]

Bit 9

`pub fn out_eof_int_clr(&self) -> OUT_EOF_INT_CLR_R`[src]

Bit 8

`pub fn out_done_int_clr(&self) -> OUT_DONE_INT_CLR_R`[src]

Bit 7

`pub fn in_err_eof_int_clr(&self) -> IN_ERR_EOF_INT_CLR_R`[src]

Bit 6

`pub fn in_suc_eof_int_clr(&self) -> IN_SUC_EOF_INT_CLR_R`[src]

Bit 5

`pub fn in_done_int_clr(&self) -> IN_DONE_INT_CLR_R`[src]

Bit 4

`pub fn tx_hung_int_clr(&self) -> TX_HUNG_INT_CLR_R`[src]

Bit 3

`pub fn rx_hung_int_clr(&self) -> RX_HUNG_INT_CLR_R`[src]

Bit 2

`pub fn tx_start_int_clr(&self) -> TX_START_INT_CLR_R`[src]

Bit 1

`pub fn rx_start_int_clr(&self) -> RX_START_INT_CLR_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DMA_OUT_STATUS>>`[src]

`pub fn out_empty(&self) -> OUT_EMPTY_R`[src]

Bit 1

`pub fn out_full(&self) -> OUT_FULL_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DMA_OUT_PUSH>>`[src]

`pub fn outfifo_push(&self) -> OUTFIFO_PUSH_R`[src]

Bit 16

`pub fn outfifo_wdata(&self) -> OUTFIFO_WDATA_R`[src]

Bits 0:8

`impl R<u32, Reg<u32, _DMA_IN_STATUS>>`[src]

`pub fn rx_err_cause(&self) -> RX_ERR_CAUSE_R`[src]

Bits 4:6

`pub fn in_empty(&self) -> IN_EMPTY_R`[src]

Bit 1

`pub fn in_full(&self) -> IN_FULL_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DMA_IN_POP>>`[src]

`pub fn infifo_pop(&self) -> INFIFO_POP_R`[src]

Bit 16

`pub fn infifo_rdata(&self) -> INFIFO_RDATA_R`[src]

Bits 0:11

`impl R<u32, Reg<u32, _DMA_OUT_LINK>>`[src]

`pub fn outlink_park(&self) -> OUTLINK_PARK_R`[src]

Bit 31

`pub fn outlink_restart(&self) -> OUTLINK_RESTART_R`[src]

Bit 30

`pub fn outlink_start(&self) -> OUTLINK_START_R`[src]

Bit 29

`pub fn outlink_stop(&self) -> OUTLINK_STOP_R`[src]

Bit 28

`pub fn outlink_addr(&self) -> OUTLINK_ADDR_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _DMA_IN_LINK>>`[src]

`pub fn inlink_park(&self) -> INLINK_PARK_R`[src]

Bit 31

`pub fn inlink_restart(&self) -> INLINK_RESTART_R`[src]

Bit 30

`pub fn inlink_start(&self) -> INLINK_START_R`[src]

Bit 29

`pub fn inlink_stop(&self) -> INLINK_STOP_R`[src]

Bit 28

`pub fn inlink_auto_ret(&self) -> INLINK_AUTO_RET_R`[src]

Bit 20

`pub fn inlink_addr(&self) -> INLINK_ADDR_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _CONF1>>`[src]

`pub fn dma_infifo_full_thrs(&self) -> DMA_INFIFO_FULL_THRS_R`[src]

Bits 9:20

`pub fn sw_start(&self) -> SW_START_R`[src]

Bit 8

`pub fn wait_sw_start(&self) -> WAIT_SW_START_R`[src]

Bit 7

`pub fn check_owner(&self) -> CHECK_OWNER_R`[src]

Bit 6

`pub fn tx_ack_num_re(&self) -> TX_ACK_NUM_RE_R`[src]

Bit 5

`pub fn tx_check_sum_re(&self) -> TX_CHECK_SUM_RE_R`[src]

Bit 4

`pub fn save_head(&self) -> SAVE_HEAD_R`[src]

Bit 3

`pub fn crc_disable(&self) -> CRC_DISABLE_R`[src]

Bit 2

`pub fn check_seq_en(&self) -> CHECK_SEQ_EN_R`[src]

Bit 6

`pub fn rx_db_esc_en(&self) -> RX_DB_ESC_EN_R`[src]

Bit 5

`pub fn rx_c0_esc_en(&self) -> RX_C0_ESC_EN_R`[src]

Bit 4

`pub fn tx_13_esc_en(&self) -> TX_13_ESC_EN_R`[src]

Bit 3

`pub fn tx_11_esc_en(&self) -> TX_11_ESC_EN_R`[src]

Bit 2

`pub fn tx_db_esc_en(&self) -> TX_DB_ESC_EN_R`[src]

Bit 1

`pub fn tx_c0_esc_en(&self) -> TX_C0_ESC_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HUNG_CONF>>`[src]

`pub fn rxfifo_timeout_ena(&self) -> RXFIFO_TIMEOUT_ENA_R`[src]

Bit 23

`pub fn rxfifo_timeout_shift(&self) -> RXFIFO_TIMEOUT_SHIFT_R`[src]

Bits 20:22

`pub fn rxfifo_timeout(&self) -> RXFIFO_TIMEOUT_R`[src]

Bits 12:19

`pub fn txfifo_timeout_ena(&self) -> TXFIFO_TIMEOUT_ENA_R`[src]

Bit 11

`pub fn txfifo_timeout_shift(&self) -> TXFIFO_TIMEOUT_SHIFT_R`[src]

Bits 8:10

`pub fn txfifo_timeout(&self) -> TXFIFO_TIMEOUT_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _RX_HEAD>>`[src]

`pub fn rx_head(&self) -> RX_HEAD_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _QUICK_SENT>>`[src]

`pub fn always_send_en(&self) -> ALWAYS_SEND_EN_R`[src]

Bit 7

`pub fn always_send_num(&self) -> ALWAYS_SEND_NUM_R`[src]

Bits 4:6

`pub fn single_send_en(&self) -> SINGLE_SEND_EN_R`[src]

Bits 16:27

`pub fn host_slc0_rx_pf_valid(&self) -> HOST_SLC0_RX_PF_VALID_R`[src]

Bit 12

`pub fn host_slc0_token0(&self) -> HOST_SLC0_TOKEN0_R`[src]

Bits 0:11

`impl R<u32, Reg<u32, _HOST_SLC0_HOST_PF>>`[src]

`pub fn host_slc0_pf_data(&self) -> HOST_SLC0_PF_DATA_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _HOST_SLC1_HOST_PF>>`[src]

`pub fn host_slc1_pf_data(&self) -> HOST_SLC1_PF_DATA_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _HOST_SLC0HOST_INT_RAW>>`[src]

`pub fn host_gpio_sdio_int_raw(&self) -> HOST_GPIO_SDIO_INT_RAW_R`[src]

Bit 25

`pub fn host_slc0_host_rd_retry_int_raw( &self ) -> HOST_SLC0_HOST_RD_RETRY_INT_RAW_R`[src]

Bit 24

`pub fn host_slc0_rx_new_packet_int_raw( &self ) -> HOST_SLC0_RX_NEW_PACKET_INT_RAW_R`[src]

Bit 23

`pub fn host_slc0_ext_bit3_int_raw(&self) -> HOST_SLC0_EXT_BIT3_INT_RAW_R`[src]

Bit 22

`pub fn host_slc0_ext_bit2_int_raw(&self) -> HOST_SLC0_EXT_BIT2_INT_RAW_R`[src]

Bit 21

`pub fn host_slc0_ext_bit1_int_raw(&self) -> HOST_SLC0_EXT_BIT1_INT_RAW_R`[src]

Bit 20

`pub fn host_slc0_ext_bit0_int_raw(&self) -> HOST_SLC0_EXT_BIT0_INT_RAW_R`[src]

Bit 19

`pub fn host_slc0_rx_pf_valid_int_raw(&self) -> HOST_SLC0_RX_PF_VALID_INT_RAW_R`[src]

Bit 18

`pub fn host_slc0_tx_ovf_int_raw(&self) -> HOST_SLC0_TX_OVF_INT_RAW_R`[src]

Bit 17

`pub fn host_slc0_rx_udf_int_raw(&self) -> HOST_SLC0_RX_UDF_INT_RAW_R`[src]

Bit 16

`pub fn host_slc0host_tx_start_int_raw(&self) -> HOST_SLC0HOST_TX_START_INT_RAW_R`[src]

Bit 15

`pub fn host_slc0host_rx_start_int_raw(&self) -> HOST_SLC0HOST_RX_START_INT_RAW_R`[src]

Bit 14

`pub fn host_slc0host_rx_eof_int_raw(&self) -> HOST_SLC0HOST_RX_EOF_INT_RAW_R`[src]

Bit 13

`pub fn host_slc0host_rx_sof_int_raw(&self) -> HOST_SLC0HOST_RX_SOF_INT_RAW_R`[src]

Bit 12

`pub fn host_slc0_token1_0to1_int_raw(&self) -> HOST_SLC0_TOKEN1_0TO1_INT_RAW_R`[src]

Bit 11

`pub fn host_slc0_token0_0to1_int_raw(&self) -> HOST_SLC0_TOKEN0_0TO1_INT_RAW_R`[src]

Bit 10

`pub fn host_slc0_token1_1to0_int_raw(&self) -> HOST_SLC0_TOKEN1_1TO0_INT_RAW_R`[src]

Bit 9

`pub fn host_slc0_token0_1to0_int_raw(&self) -> HOST_SLC0_TOKEN0_1TO0_INT_RAW_R`[src]

Bit 8

`pub fn host_slc0_tohost_bit7_int_raw(&self) -> HOST_SLC0_TOHOST_BIT7_INT_RAW_R`[src]

Bit 7

`pub fn host_slc0_tohost_bit6_int_raw(&self) -> HOST_SLC0_TOHOST_BIT6_INT_RAW_R`[src]

Bit 6

`pub fn host_slc0_tohost_bit5_int_raw(&self) -> HOST_SLC0_TOHOST_BIT5_INT_RAW_R`[src]

Bit 5

`pub fn host_slc0_tohost_bit4_int_raw(&self) -> HOST_SLC0_TOHOST_BIT4_INT_RAW_R`[src]

Bit 4

`pub fn host_slc0_tohost_bit3_int_raw(&self) -> HOST_SLC0_TOHOST_BIT3_INT_RAW_R`[src]

Bit 3

`pub fn host_slc0_tohost_bit2_int_raw(&self) -> HOST_SLC0_TOHOST_BIT2_INT_RAW_R`[src]

Bit 2

`pub fn host_slc0_tohost_bit1_int_raw(&self) -> HOST_SLC0_TOHOST_BIT1_INT_RAW_R`[src]

Bit 1

`pub fn host_slc0_tohost_bit0_int_raw(&self) -> HOST_SLC0_TOHOST_BIT0_INT_RAW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HOST_SLC1HOST_INT_RAW>>`[src]

`pub fn host_slc1_bt_rx_new_packet_int_raw( &self ) -> HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_R`[src]

Bit 25

`pub fn host_slc1_host_rd_retry_int_raw( &self ) -> HOST_SLC1_HOST_RD_RETRY_INT_RAW_R`[src]

Bit 24

`pub fn host_slc1_wifi_rx_new_packet_int_raw( &self ) -> HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_R`[src]

Bit 23

`pub fn host_slc1_ext_bit3_int_raw(&self) -> HOST_SLC1_EXT_BIT3_INT_RAW_R`[src]

Bit 22

`pub fn host_slc1_ext_bit2_int_raw(&self) -> HOST_SLC1_EXT_BIT2_INT_RAW_R`[src]

Bit 21

`pub fn host_slc1_ext_bit1_int_raw(&self) -> HOST_SLC1_EXT_BIT1_INT_RAW_R`[src]

Bit 20

`pub fn host_slc1_ext_bit0_int_raw(&self) -> HOST_SLC1_EXT_BIT0_INT_RAW_R`[src]

Bit 19

`pub fn host_slc1_rx_pf_valid_int_raw(&self) -> HOST_SLC1_RX_PF_VALID_INT_RAW_R`[src]

Bit 18

`pub fn host_slc1_tx_ovf_int_raw(&self) -> HOST_SLC1_TX_OVF_INT_RAW_R`[src]

Bit 17

`pub fn host_slc1_rx_udf_int_raw(&self) -> HOST_SLC1_RX_UDF_INT_RAW_R`[src]

Bit 16

`pub fn host_slc1host_tx_start_int_raw(&self) -> HOST_SLC1HOST_TX_START_INT_RAW_R`[src]

Bit 15

`pub fn host_slc1host_rx_start_int_raw(&self) -> HOST_SLC1HOST_RX_START_INT_RAW_R`[src]

Bit 14

`pub fn host_slc1host_rx_eof_int_raw(&self) -> HOST_SLC1HOST_RX_EOF_INT_RAW_R`[src]

Bit 13

`pub fn host_slc1host_rx_sof_int_raw(&self) -> HOST_SLC1HOST_RX_SOF_INT_RAW_R`[src]

Bit 12

`pub fn host_slc1_token1_0to1_int_raw(&self) -> HOST_SLC1_TOKEN1_0TO1_INT_RAW_R`[src]

Bit 11

`pub fn host_slc1_token0_0to1_int_raw(&self) -> HOST_SLC1_TOKEN0_0TO1_INT_RAW_R`[src]

Bit 10

`pub fn host_slc1_token1_1to0_int_raw(&self) -> HOST_SLC1_TOKEN1_1TO0_INT_RAW_R`[src]

Bit 9

`pub fn host_slc1_token0_1to0_int_raw(&self) -> HOST_SLC1_TOKEN0_1TO0_INT_RAW_R`[src]

Bit 8

`pub fn host_slc1_tohost_bit7_int_raw(&self) -> HOST_SLC1_TOHOST_BIT7_INT_RAW_R`[src]

Bit 7

`pub fn host_slc1_tohost_bit6_int_raw(&self) -> HOST_SLC1_TOHOST_BIT6_INT_RAW_R`[src]

Bit 6

`pub fn host_slc1_tohost_bit5_int_raw(&self) -> HOST_SLC1_TOHOST_BIT5_INT_RAW_R`[src]

Bit 5

`pub fn host_slc1_tohost_bit4_int_raw(&self) -> HOST_SLC1_TOHOST_BIT4_INT_RAW_R`[src]

Bit 4

`pub fn host_slc1_tohost_bit3_int_raw(&self) -> HOST_SLC1_TOHOST_BIT3_INT_RAW_R`[src]

Bit 3

`pub fn host_slc1_tohost_bit2_int_raw(&self) -> HOST_SLC1_TOHOST_BIT2_INT_RAW_R`[src]

Bit 2

`pub fn host_slc1_tohost_bit1_int_raw(&self) -> HOST_SLC1_TOHOST_BIT1_INT_RAW_R`[src]

Bit 1

`pub fn host_slc1_tohost_bit0_int_raw(&self) -> HOST_SLC1_TOHOST_BIT0_INT_RAW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HOST_SLC0HOST_INT_ST>>`[src]

`pub fn host_gpio_sdio_int_st(&self) -> HOST_GPIO_SDIO_INT_ST_R`[src]

Bit 25

`pub fn host_slc0_host_rd_retry_int_st(&self) -> HOST_SLC0_HOST_RD_RETRY_INT_ST_R`[src]

Bit 24

`pub fn host_slc0_rx_new_packet_int_st(&self) -> HOST_SLC0_RX_NEW_PACKET_INT_ST_R`[src]

Bit 23

`pub fn host_slc0_ext_bit3_int_st(&self) -> HOST_SLC0_EXT_BIT3_INT_ST_R`[src]

Bit 22

`pub fn host_slc0_ext_bit2_int_st(&self) -> HOST_SLC0_EXT_BIT2_INT_ST_R`[src]

Bit 21

`pub fn host_slc0_ext_bit1_int_st(&self) -> HOST_SLC0_EXT_BIT1_INT_ST_R`[src]

Bit 20

`pub fn host_slc0_ext_bit0_int_st(&self) -> HOST_SLC0_EXT_BIT0_INT_ST_R`[src]

Bit 19

`pub fn host_slc0_rx_pf_valid_int_st(&self) -> HOST_SLC0_RX_PF_VALID_INT_ST_R`[src]

Bit 18

`pub fn host_slc0_tx_ovf_int_st(&self) -> HOST_SLC0_TX_OVF_INT_ST_R`[src]

Bit 17

`pub fn host_slc0_rx_udf_int_st(&self) -> HOST_SLC0_RX_UDF_INT_ST_R`[src]

Bit 16

`pub fn host_slc0host_tx_start_int_st(&self) -> HOST_SLC0HOST_TX_START_INT_ST_R`[src]

Bit 15

`pub fn host_slc0host_rx_start_int_st(&self) -> HOST_SLC0HOST_RX_START_INT_ST_R`[src]

Bit 14

`pub fn host_slc0host_rx_eof_int_st(&self) -> HOST_SLC0HOST_RX_EOF_INT_ST_R`[src]

Bit 13

`pub fn host_slc0host_rx_sof_int_st(&self) -> HOST_SLC0HOST_RX_SOF_INT_ST_R`[src]

Bit 12

`pub fn host_slc0_token1_0to1_int_st(&self) -> HOST_SLC0_TOKEN1_0TO1_INT_ST_R`[src]

Bit 11

`pub fn host_slc0_token0_0to1_int_st(&self) -> HOST_SLC0_TOKEN0_0TO1_INT_ST_R`[src]

Bit 10

`pub fn host_slc0_token1_1to0_int_st(&self) -> HOST_SLC0_TOKEN1_1TO0_INT_ST_R`[src]

Bit 9

`pub fn host_slc0_token0_1to0_int_st(&self) -> HOST_SLC0_TOKEN0_1TO0_INT_ST_R`[src]

Bit 8

`pub fn host_slc0_tohost_bit7_int_st(&self) -> HOST_SLC0_TOHOST_BIT7_INT_ST_R`[src]

Bit 7

`pub fn host_slc0_tohost_bit6_int_st(&self) -> HOST_SLC0_TOHOST_BIT6_INT_ST_R`[src]

Bit 6

`pub fn host_slc0_tohost_bit5_int_st(&self) -> HOST_SLC0_TOHOST_BIT5_INT_ST_R`[src]

Bit 5

`pub fn host_slc0_tohost_bit4_int_st(&self) -> HOST_SLC0_TOHOST_BIT4_INT_ST_R`[src]

Bit 4

`pub fn host_slc0_tohost_bit3_int_st(&self) -> HOST_SLC0_TOHOST_BIT3_INT_ST_R`[src]

Bit 3

`pub fn host_slc0_tohost_bit2_int_st(&self) -> HOST_SLC0_TOHOST_BIT2_INT_ST_R`[src]

Bit 2

`pub fn host_slc0_tohost_bit1_int_st(&self) -> HOST_SLC0_TOHOST_BIT1_INT_ST_R`[src]

Bit 1

`pub fn host_slc0_tohost_bit0_int_st(&self) -> HOST_SLC0_TOHOST_BIT0_INT_ST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HOST_SLC1HOST_INT_ST>>`[src]

`pub fn host_slc1_bt_rx_new_packet_int_st( &self ) -> HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_R`[src]

Bit 25

`pub fn host_slc1_host_rd_retry_int_st(&self) -> HOST_SLC1_HOST_RD_RETRY_INT_ST_R`[src]

Bit 24

`pub fn host_slc1_wifi_rx_new_packet_int_st( &self ) -> HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_R`[src]

Bit 23

`pub fn host_slc1_ext_bit3_int_st(&self) -> HOST_SLC1_EXT_BIT3_INT_ST_R`[src]

Bit 22

`pub fn host_slc1_ext_bit2_int_st(&self) -> HOST_SLC1_EXT_BIT2_INT_ST_R`[src]

Bit 21

`pub fn host_slc1_ext_bit1_int_st(&self) -> HOST_SLC1_EXT_BIT1_INT_ST_R`[src]

Bit 20

`pub fn host_slc1_ext_bit0_int_st(&self) -> HOST_SLC1_EXT_BIT0_INT_ST_R`[src]

Bit 19

`pub fn host_slc1_rx_pf_valid_int_st(&self) -> HOST_SLC1_RX_PF_VALID_INT_ST_R`[src]

Bit 18

`pub fn host_slc1_tx_ovf_int_st(&self) -> HOST_SLC1_TX_OVF_INT_ST_R`[src]

Bit 17

`pub fn host_slc1_rx_udf_int_st(&self) -> HOST_SLC1_RX_UDF_INT_ST_R`[src]

Bit 16

`pub fn host_slc1host_tx_start_int_st(&self) -> HOST_SLC1HOST_TX_START_INT_ST_R`[src]

Bit 15

`pub fn host_slc1host_rx_start_int_st(&self) -> HOST_SLC1HOST_RX_START_INT_ST_R`[src]

Bit 14

`pub fn host_slc1host_rx_eof_int_st(&self) -> HOST_SLC1HOST_RX_EOF_INT_ST_R`[src]

Bit 13

`pub fn host_slc1host_rx_sof_int_st(&self) -> HOST_SLC1HOST_RX_SOF_INT_ST_R`[src]

Bit 12

`pub fn host_slc1_token1_0to1_int_st(&self) -> HOST_SLC1_TOKEN1_0TO1_INT_ST_R`[src]

Bit 11

`pub fn host_slc1_token0_0to1_int_st(&self) -> HOST_SLC1_TOKEN0_0TO1_INT_ST_R`[src]

Bit 10

`pub fn host_slc1_token1_1to0_int_st(&self) -> HOST_SLC1_TOKEN1_1TO0_INT_ST_R`[src]

Bit 9

`pub fn host_slc1_token0_1to0_int_st(&self) -> HOST_SLC1_TOKEN0_1TO0_INT_ST_R`[src]

Bit 8

`pub fn host_slc1_tohost_bit7_int_st(&self) -> HOST_SLC1_TOHOST_BIT7_INT_ST_R`[src]

Bit 7

`pub fn host_slc1_tohost_bit6_int_st(&self) -> HOST_SLC1_TOHOST_BIT6_INT_ST_R`[src]

Bit 6

`pub fn host_slc1_tohost_bit5_int_st(&self) -> HOST_SLC1_TOHOST_BIT5_INT_ST_R`[src]

Bit 5

`pub fn host_slc1_tohost_bit4_int_st(&self) -> HOST_SLC1_TOHOST_BIT4_INT_ST_R`[src]

Bit 4

`pub fn host_slc1_tohost_bit3_int_st(&self) -> HOST_SLC1_TOHOST_BIT3_INT_ST_R`[src]

Bit 3

`pub fn host_slc1_tohost_bit2_int_st(&self) -> HOST_SLC1_TOHOST_BIT2_INT_ST_R`[src]

Bit 2

`pub fn host_slc1_tohost_bit1_int_st(&self) -> HOST_SLC1_TOHOST_BIT1_INT_ST_R`[src]

Bit 1

`pub fn host_slc1_tohost_bit0_int_st(&self) -> HOST_SLC1_TOHOST_BIT0_INT_ST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HOST_SLCHOST_PKT_LEN>>`[src]

`pub fn host_hostslc0_len_check(&self) -> HOST_HOSTSLC0_LEN_CHECK_R`[src]

Bits 20:31

`pub fn host_hostslc0_len(&self) -> HOST_HOSTSLC0_LEN_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HOST_SLCHOST_STATE_W0>>`[src]

`pub fn host_slchost_state3(&self) -> HOST_SLCHOST_STATE3_R`[src]

Bits 24:31

`pub fn host_slchost_state2(&self) -> HOST_SLCHOST_STATE2_R`[src]

Bits 16:23

`pub fn host_slchost_state1(&self) -> HOST_SLCHOST_STATE1_R`[src]

Bits 8:15

`pub fn host_slchost_state0(&self) -> HOST_SLCHOST_STATE0_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _HOST_SLCHOST_STATE_W1>>`[src]

`pub fn host_slchost_state7(&self) -> HOST_SLCHOST_STATE7_R`[src]

Bits 24:31

`pub fn host_slchost_state6(&self) -> HOST_SLCHOST_STATE6_R`[src]

Bits 16:23

`pub fn host_slchost_state5(&self) -> HOST_SLCHOST_STATE5_R`[src]

Bits 8:15

`pub fn host_slchost_state4(&self) -> HOST_SLCHOST_STATE4_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _HOST_SLCHOST_CONF_W0>>`[src]

`pub fn host_slchost_conf3(&self) -> HOST_SLCHOST_CONF3_R`[src]

Bits 24:31

`pub fn host_slchost_conf2(&self) -> HOST_SLCHOST_CONF2_R`[src]

Bits 16:23

`pub fn host_slchost_conf1(&self) -> HOST_SLCHOST_CONF1_R`[src]

Bits 8:15

`pub fn host_slchost_conf0(&self) -> HOST_SLCHOST_CONF0_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _HOST_SLCHOST_CONF_W1>>`[src]

`pub fn host_slchost_conf7(&self) -> HOST_SLCHOST_CONF7_R`[src]

Bits 24:31

`pub fn host_slchost_conf6(&self) -> HOST_SLCHOST_CONF6_R`[src]

Bits 16:23

`pub fn host_slchost_conf5(&self) -> HOST_SLCHOST_CONF5_R`[src]

Bits 8:15

`pub fn host_slchost_conf4(&self) -> HOST_SLCHOST_CONF4_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _HOST_SLCHOST_CONF_W2>>`[src]

`pub fn host_slchost_conf11(&self) -> HOST_SLCHOST_CONF11_R`[src]

Bits 24:31

`pub fn host_slchost_conf10(&self) -> HOST_SLCHOST_CONF10_R`[src]

Bits 16:23

`pub fn host_slchost_conf9(&self) -> HOST_SLCHOST_CONF9_R`[src]

Bits 8:15

`pub fn host_slchost_conf8(&self) -> HOST_SLCHOST_CONF8_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _HOST_SLCHOST_CONF_W3>>`[src]

`pub fn host_slchost_conf15(&self) -> HOST_SLCHOST_CONF15_R`[src]

Bits 24:31

`pub fn host_slchost_conf14(&self) -> HOST_SLCHOST_CONF14_R`[src]

Bits 16:23

`pub fn host_slchost_conf13(&self) -> HOST_SLCHOST_CONF13_R`[src]

Bits 8:15

`pub fn host_slchost_conf12(&self) -> HOST_SLCHOST_CONF12_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _HOST_SLCHOST_CONF_W4>>`[src]

`pub fn host_slchost_conf19(&self) -> HOST_SLCHOST_CONF19_R`[src]

Bits 24:31

`pub fn host_slchost_conf18(&self) -> HOST_SLCHOST_CONF18_R`[src]

Bits 16:23

`pub fn host_slchost_conf17(&self) -> HOST_SLCHOST_CONF17_R`[src]

Bits 8:15

`pub fn host_slchost_conf16(&self) -> HOST_SLCHOST_CONF16_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _HOST_SLCHOST_CONF_W5>>`[src]

`pub fn host_slchost_conf23(&self) -> HOST_SLCHOST_CONF23_R`[src]

Bits 24:31

`pub fn host_slchost_conf22(&self) -> HOST_SLCHOST_CONF22_R`[src]

Bits 16:23

`pub fn host_slchost_conf21(&self) -> HOST_SLCHOST_CONF21_R`[src]

Bits 8:15

`pub fn host_slchost_conf20(&self) -> HOST_SLCHOST_CONF20_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _HOST_SLCHOST_CONF_W6>>`[src]

`pub fn host_slchost_conf27(&self) -> HOST_SLCHOST_CONF27_R`[src]

Bits 24:31

`pub fn host_slchost_conf26(&self) -> HOST_SLCHOST_CONF26_R`[src]

Bits 16:23

`pub fn host_slchost_conf25(&self) -> HOST_SLCHOST_CONF25_R`[src]

Bits 8:15

`pub fn host_slchost_conf24(&self) -> HOST_SLCHOST_CONF24_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _HOST_SLCHOST_CONF_W7>>`[src]

`pub fn host_slchost_conf31(&self) -> HOST_SLCHOST_CONF31_R`[src]

Bits 24:31

`pub fn host_slchost_conf30(&self) -> HOST_SLCHOST_CONF30_R`[src]

Bits 16:23

`pub fn host_slchost_conf29(&self) -> HOST_SLCHOST_CONF29_R`[src]

Bits 8:15

`pub fn host_slchost_conf28(&self) -> HOST_SLCHOST_CONF28_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _HOST_SLCHOST_PKT_LEN0>>`[src]

`pub fn host_hostslc0_len0(&self) -> HOST_HOSTSLC0_LEN0_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HOST_SLCHOST_PKT_LEN1>>`[src]

`pub fn host_hostslc0_len1(&self) -> HOST_HOSTSLC0_LEN1_R`[src]

Bits 0:19

Bits 8:15

`pub fn host_slchost_conf60(&self) -> HOST_SLCHOST_CONF60_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _HOST_SLCHOST_CHECK_SUM0>>`[src]

`pub fn host_slchost_check_sum0(&self) -> HOST_SLCHOST_CHECK_SUM0_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _HOST_SLCHOST_CHECK_SUM1>>`[src]

`pub fn host_slchost_check_sum1(&self) -> HOST_SLCHOST_CHECK_SUM1_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _HOST_SLC1HOST_TOKEN_RDATA>>`[src]

`pub fn host_slc1_rx_pf_eof(&self) -> HOST_SLC1_RX_PF_EOF_R`[src]

Bits 28:31

`pub fn host_hostslc1_token1(&self) -> HOST_HOSTSLC1_TOKEN1_R`[src]

Bits 16:27

`pub fn host_slc1_rx_pf_valid(&self) -> HOST_SLC1_RX_PF_VALID_R`[src]

Bit 12

`pub fn host_slc1_token0(&self) -> HOST_SLC1_TOKEN0_R`[src]

Bits 0:11

`impl R<u32, Reg<u32, _HOST_SLC0HOST_TOKEN_WDATA>>`[src]

`pub fn host_slc0host_token1_wd(&self) -> HOST_SLC0HOST_TOKEN1_WD_R`[src]

Bits 16:27

`pub fn host_slc0host_token0_wd(&self) -> HOST_SLC0HOST_TOKEN0_WD_R`[src]

Bits 0:11

`impl R<u32, Reg<u32, _HOST_SLC1HOST_TOKEN_WDATA>>`[src]

`pub fn host_slc1host_token1_wd(&self) -> HOST_SLC1HOST_TOKEN1_WD_R`[src]

Bits 16:27

`pub fn host_slc1host_token0_wd(&self) -> HOST_SLC1HOST_TOKEN0_WD_R`[src]

Bits 0:11

`impl R<u32, Reg<u32, _HOST_SLCHOST_TOKEN_CON>>`[src]

`pub fn host_slc0host_len_wr(&self) -> HOST_SLC0HOST_LEN_WR_R`[src]

Bit 8

`pub fn host_slc1host_token1_wr(&self) -> HOST_SLC1HOST_TOKEN1_WR_R`[src]

Bit 7

`pub fn host_slc1host_token0_wr(&self) -> HOST_SLC1HOST_TOKEN0_WR_R`[src]

Bit 6

`pub fn host_slc1host_token1_dec(&self) -> HOST_SLC1HOST_TOKEN1_DEC_R`[src]

Bit 5

`pub fn host_slc1host_token0_dec(&self) -> HOST_SLC1HOST_TOKEN0_DEC_R`[src]

Bit 4

`pub fn host_slc0host_token1_wr(&self) -> HOST_SLC0HOST_TOKEN1_WR_R`[src]

Bit 3

`pub fn host_slc0host_token0_wr(&self) -> HOST_SLC0HOST_TOKEN0_WR_R`[src]

Bit 2

`pub fn host_slc0host_token1_dec(&self) -> HOST_SLC0HOST_TOKEN1_DEC_R`[src]

Bit 1

`pub fn host_slc0host_token0_dec(&self) -> HOST_SLC0HOST_TOKEN0_DEC_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HOST_SLC0HOST_INT_CLR>>`[src]

`pub fn host_gpio_sdio_int_clr(&self) -> HOST_GPIO_SDIO_INT_CLR_R`[src]

Bit 25

`pub fn host_slc0_host_rd_retry_int_clr( &self ) -> HOST_SLC0_HOST_RD_RETRY_INT_CLR_R`[src]

Bit 24

`pub fn host_slc0_rx_new_packet_int_clr( &self ) -> HOST_SLC0_RX_NEW_PACKET_INT_CLR_R`[src]

Bit 23

`pub fn host_slc0_ext_bit3_int_clr(&self) -> HOST_SLC0_EXT_BIT3_INT_CLR_R`[src]

Bit 22

`pub fn host_slc0_ext_bit2_int_clr(&self) -> HOST_SLC0_EXT_BIT2_INT_CLR_R`[src]

Bit 21

`pub fn host_slc0_ext_bit1_int_clr(&self) -> HOST_SLC0_EXT_BIT1_INT_CLR_R`[src]

Bit 20

`pub fn host_slc0_ext_bit0_int_clr(&self) -> HOST_SLC0_EXT_BIT0_INT_CLR_R`[src]

Bit 19

`pub fn host_slc0_rx_pf_valid_int_clr(&self) -> HOST_SLC0_RX_PF_VALID_INT_CLR_R`[src]

Bit 18

`pub fn host_slc0_tx_ovf_int_clr(&self) -> HOST_SLC0_TX_OVF_INT_CLR_R`[src]

Bit 17

`pub fn host_slc0_rx_udf_int_clr(&self) -> HOST_SLC0_RX_UDF_INT_CLR_R`[src]

Bit 16

`pub fn host_slc0host_tx_start_int_clr(&self) -> HOST_SLC0HOST_TX_START_INT_CLR_R`[src]

Bit 15

`pub fn host_slc0host_rx_start_int_clr(&self) -> HOST_SLC0HOST_RX_START_INT_CLR_R`[src]

Bit 14

`pub fn host_slc0host_rx_eof_int_clr(&self) -> HOST_SLC0HOST_RX_EOF_INT_CLR_R`[src]

Bit 13

`pub fn host_slc0host_rx_sof_int_clr(&self) -> HOST_SLC0HOST_RX_SOF_INT_CLR_R`[src]

Bit 12

`pub fn host_slc0_token1_0to1_int_clr(&self) -> HOST_SLC0_TOKEN1_0TO1_INT_CLR_R`[src]

Bit 11

`pub fn host_slc0_token0_0to1_int_clr(&self) -> HOST_SLC0_TOKEN0_0TO1_INT_CLR_R`[src]

Bit 10

`pub fn host_slc0_token1_1to0_int_clr(&self) -> HOST_SLC0_TOKEN1_1TO0_INT_CLR_R`[src]

Bit 9

`pub fn host_slc0_token0_1to0_int_clr(&self) -> HOST_SLC0_TOKEN0_1TO0_INT_CLR_R`[src]

Bit 8

`pub fn host_slc0_tohost_bit7_int_clr(&self) -> HOST_SLC0_TOHOST_BIT7_INT_CLR_R`[src]

Bit 7

`pub fn host_slc0_tohost_bit6_int_clr(&self) -> HOST_SLC0_TOHOST_BIT6_INT_CLR_R`[src]

Bit 6

`pub fn host_slc0_tohost_bit5_int_clr(&self) -> HOST_SLC0_TOHOST_BIT5_INT_CLR_R`[src]

Bit 5

`pub fn host_slc0_tohost_bit4_int_clr(&self) -> HOST_SLC0_TOHOST_BIT4_INT_CLR_R`[src]

Bit 4

`pub fn host_slc0_tohost_bit3_int_clr(&self) -> HOST_SLC0_TOHOST_BIT3_INT_CLR_R`[src]

Bit 3

`pub fn host_slc0_tohost_bit2_int_clr(&self) -> HOST_SLC0_TOHOST_BIT2_INT_CLR_R`[src]

Bit 2

`pub fn host_slc0_tohost_bit1_int_clr(&self) -> HOST_SLC0_TOHOST_BIT1_INT_CLR_R`[src]

Bit 1

`pub fn host_slc0_tohost_bit0_int_clr(&self) -> HOST_SLC0_TOHOST_BIT0_INT_CLR_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HOST_SLC1HOST_INT_CLR>>`[src]

`pub fn host_slc1_bt_rx_new_packet_int_clr( &self ) -> HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_R`[src]

Bit 25

`pub fn host_slc1_host_rd_retry_int_clr( &self ) -> HOST_SLC1_HOST_RD_RETRY_INT_CLR_R`[src]

Bit 24

`pub fn host_slc1_wifi_rx_new_packet_int_clr( &self ) -> HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_R`[src]

Bit 23

`pub fn host_slc1_ext_bit3_int_clr(&self) -> HOST_SLC1_EXT_BIT3_INT_CLR_R`[src]

Bit 22

`pub fn host_slc1_ext_bit2_int_clr(&self) -> HOST_SLC1_EXT_BIT2_INT_CLR_R`[src]

Bit 21

`pub fn host_slc1_ext_bit1_int_clr(&self) -> HOST_SLC1_EXT_BIT1_INT_CLR_R`[src]

Bit 20

`pub fn host_slc1_ext_bit0_int_clr(&self) -> HOST_SLC1_EXT_BIT0_INT_CLR_R`[src]

Bit 19

`pub fn host_slc1_rx_pf_valid_int_clr(&self) -> HOST_SLC1_RX_PF_VALID_INT_CLR_R`[src]

Bit 18

`pub fn host_slc1_tx_ovf_int_clr(&self) -> HOST_SLC1_TX_OVF_INT_CLR_R`[src]

Bit 17

`pub fn host_slc1_rx_udf_int_clr(&self) -> HOST_SLC1_RX_UDF_INT_CLR_R`[src]

Bit 16

`pub fn host_slc1host_tx_start_int_clr(&self) -> HOST_SLC1HOST_TX_START_INT_CLR_R`[src]

Bit 15

`pub fn host_slc1host_rx_start_int_clr(&self) -> HOST_SLC1HOST_RX_START_INT_CLR_R`[src]

Bit 14

`pub fn host_slc1host_rx_eof_int_clr(&self) -> HOST_SLC1HOST_RX_EOF_INT_CLR_R`[src]

Bit 13

`pub fn host_slc1host_rx_sof_int_clr(&self) -> HOST_SLC1HOST_RX_SOF_INT_CLR_R`[src]

Bit 12

`pub fn host_slc1_token1_0to1_int_clr(&self) -> HOST_SLC1_TOKEN1_0TO1_INT_CLR_R`[src]

Bit 11

`pub fn host_slc1_token0_0to1_int_clr(&self) -> HOST_SLC1_TOKEN0_0TO1_INT_CLR_R`[src]

Bit 10

`pub fn host_slc1_token1_1to0_int_clr(&self) -> HOST_SLC1_TOKEN1_1TO0_INT_CLR_R`[src]

Bit 9

`pub fn host_slc1_token0_1to0_int_clr(&self) -> HOST_SLC1_TOKEN0_1TO0_INT_CLR_R`[src]

Bit 8

`pub fn host_slc1_tohost_bit7_int_clr(&self) -> HOST_SLC1_TOHOST_BIT7_INT_CLR_R`[src]

Bit 7

`pub fn host_slc1_tohost_bit6_int_clr(&self) -> HOST_SLC1_TOHOST_BIT6_INT_CLR_R`[src]

Bit 6

`pub fn host_slc1_tohost_bit5_int_clr(&self) -> HOST_SLC1_TOHOST_BIT5_INT_CLR_R`[src]

Bit 5

`pub fn host_slc1_tohost_bit4_int_clr(&self) -> HOST_SLC1_TOHOST_BIT4_INT_CLR_R`[src]

Bit 4

`pub fn host_slc1_tohost_bit3_int_clr(&self) -> HOST_SLC1_TOHOST_BIT3_INT_CLR_R`[src]

Bit 3

`pub fn host_slc1_tohost_bit2_int_clr(&self) -> HOST_SLC1_TOHOST_BIT2_INT_CLR_R`[src]

Bit 2

`pub fn host_slc1_tohost_bit1_int_clr(&self) -> HOST_SLC1_TOHOST_BIT1_INT_CLR_R`[src]

Bit 1

`pub fn host_slc1_tohost_bit0_int_clr(&self) -> HOST_SLC1_TOHOST_BIT0_INT_CLR_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HOST_SLC0HOST_FUNC1_INT_ENA>>`[src]

`pub fn host_fn1_gpio_sdio_int_ena(&self) -> HOST_FN1_GPIO_SDIO_INT_ENA_R`[src]

Bit 25

`pub fn host_fn1_slc0_host_rd_retry_int_ena( &self ) -> HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_R`[src]

Bit 24

`pub fn host_fn1_slc0_rx_new_packet_int_ena( &self ) -> HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_R`[src]

Bit 23

`pub fn host_fn1_slc0_ext_bit3_int_ena(&self) -> HOST_FN1_SLC0_EXT_BIT3_INT_ENA_R`[src]

Bit 22

`pub fn host_fn1_slc0_ext_bit2_int_ena(&self) -> HOST_FN1_SLC0_EXT_BIT2_INT_ENA_R`[src]

Bit 21

`pub fn host_fn1_slc0_ext_bit1_int_ena(&self) -> HOST_FN1_SLC0_EXT_BIT1_INT_ENA_R`[src]

Bit 20

`pub fn host_fn1_slc0_ext_bit0_int_ena(&self) -> HOST_FN1_SLC0_EXT_BIT0_INT_ENA_R`[src]

Bit 19

`pub fn host_fn1_slc0_rx_pf_valid_int_ena( &self ) -> HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_R`[src]

Bit 18

`pub fn host_fn1_slc0_tx_ovf_int_ena(&self) -> HOST_FN1_SLC0_TX_OVF_INT_ENA_R`[src]

Bit 17

`pub fn host_fn1_slc0_rx_udf_int_ena(&self) -> HOST_FN1_SLC0_RX_UDF_INT_ENA_R`[src]

Bit 16

`pub fn host_fn1_slc0host_tx_start_int_ena( &self ) -> HOST_FN1_SLC0HOST_TX_START_INT_ENA_R`[src]

Bit 15

`pub fn host_fn1_slc0host_rx_start_int_ena( &self ) -> HOST_FN1_SLC0HOST_RX_START_INT_ENA_R`[src]

Bit 14

`pub fn host_fn1_slc0host_rx_eof_int_ena( &self ) -> HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_R`[src]

Bit 13

`pub fn host_fn1_slc0host_rx_sof_int_ena( &self ) -> HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_R`[src]

Bit 12

`pub fn host_fn1_slc0_token1_0to1_int_ena( &self ) -> HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_R`[src]

Bit 11

`pub fn host_fn1_slc0_token0_0to1_int_ena( &self ) -> HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_R`[src]

Bit 10

`pub fn host_fn1_slc0_token1_1to0_int_ena( &self ) -> HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_R`[src]

Bit 9

`pub fn host_fn1_slc0_token0_1to0_int_ena( &self ) -> HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_R`[src]

Bit 8

`pub fn host_fn1_slc0_tohost_bit7_int_ena( &self ) -> HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_R`[src]

Bit 7

`pub fn host_fn1_slc0_tohost_bit6_int_ena( &self ) -> HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_R`[src]

Bit 6

`pub fn host_fn1_slc0_tohost_bit5_int_ena( &self ) -> HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_R`[src]

Bit 5

`pub fn host_fn1_slc0_tohost_bit4_int_ena( &self ) -> HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_R`[src]

Bit 4

`pub fn host_fn1_slc0_tohost_bit3_int_ena( &self ) -> HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_R`[src]

Bit 3

`pub fn host_fn1_slc0_tohost_bit2_int_ena( &self ) -> HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_R`[src]

Bit 2

`pub fn host_fn1_slc0_tohost_bit1_int_ena( &self ) -> HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_R`[src]

Bit 1

`pub fn host_fn1_slc0_tohost_bit0_int_ena( &self ) -> HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HOST_SLC1HOST_FUNC1_INT_ENA>>`[src]

`pub fn host_fn1_slc1_bt_rx_new_packet_int_ena( &self ) -> HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_R`[src]

Bit 25

`pub fn host_fn1_slc1_host_rd_retry_int_ena( &self ) -> HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_R`[src]

Bit 24

`pub fn host_fn1_slc1_wifi_rx_new_packet_int_ena( &self ) -> HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_R`[src]

Bit 23

`pub fn host_fn1_slc1_ext_bit3_int_ena(&self) -> HOST_FN1_SLC1_EXT_BIT3_INT_ENA_R`[src]

Bit 22

`pub fn host_fn1_slc1_ext_bit2_int_ena(&self) -> HOST_FN1_SLC1_EXT_BIT2_INT_ENA_R`[src]

Bit 21

`pub fn host_fn1_slc1_ext_bit1_int_ena(&self) -> HOST_FN1_SLC1_EXT_BIT1_INT_ENA_R`[src]

Bit 20

`pub fn host_fn1_slc1_ext_bit0_int_ena(&self) -> HOST_FN1_SLC1_EXT_BIT0_INT_ENA_R`[src]

Bit 19

`pub fn host_fn1_slc1_rx_pf_valid_int_ena( &self ) -> HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_R`[src]

Bit 18

`pub fn host_fn1_slc1_tx_ovf_int_ena(&self) -> HOST_FN1_SLC1_TX_OVF_INT_ENA_R`[src]

Bit 17

`pub fn host_fn1_slc1_rx_udf_int_ena(&self) -> HOST_FN1_SLC1_RX_UDF_INT_ENA_R`[src]

Bit 16

`pub fn host_fn1_slc1host_tx_start_int_ena( &self ) -> HOST_FN1_SLC1HOST_TX_START_INT_ENA_R`[src]

Bit 15

`pub fn host_fn1_slc1host_rx_start_int_ena( &self ) -> HOST_FN1_SLC1HOST_RX_START_INT_ENA_R`[src]

Bit 14

`pub fn host_fn1_slc1host_rx_eof_int_ena( &self ) -> HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_R`[src]

Bit 13

`pub fn host_fn1_slc1host_rx_sof_int_ena( &self ) -> HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_R`[src]

Bit 12

`pub fn host_fn1_slc1_token1_0to1_int_ena( &self ) -> HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_R`[src]

Bit 11

`pub fn host_fn1_slc1_token0_0to1_int_ena( &self ) -> HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_R`[src]

Bit 10

`pub fn host_fn1_slc1_token1_1to0_int_ena( &self ) -> HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_R`[src]

Bit 9

`pub fn host_fn1_slc1_token0_1to0_int_ena( &self ) -> HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_R`[src]

Bit 8

`pub fn host_fn1_slc1_tohost_bit7_int_ena( &self ) -> HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_R`[src]

Bit 7

`pub fn host_fn1_slc1_tohost_bit6_int_ena( &self ) -> HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_R`[src]

Bit 6

`pub fn host_fn1_slc1_tohost_bit5_int_ena( &self ) -> HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_R`[src]

Bit 5

`pub fn host_fn1_slc1_tohost_bit4_int_ena( &self ) -> HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_R`[src]

Bit 4

`pub fn host_fn1_slc1_tohost_bit3_int_ena( &self ) -> HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_R`[src]

Bit 3

`pub fn host_fn1_slc1_tohost_bit2_int_ena( &self ) -> HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_R`[src]

Bit 2

`pub fn host_fn1_slc1_tohost_bit1_int_ena( &self ) -> HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_R`[src]

Bit 1

`pub fn host_fn1_slc1_tohost_bit0_int_ena( &self ) -> HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HOST_SLC0HOST_FUNC2_INT_ENA>>`[src]

`pub fn host_fn2_gpio_sdio_int_ena(&self) -> HOST_FN2_GPIO_SDIO_INT_ENA_R`[src]

Bit 25

`pub fn host_fn2_slc0_host_rd_retry_int_ena( &self ) -> HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_R`[src]

Bit 24

`pub fn host_fn2_slc0_rx_new_packet_int_ena( &self ) -> HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_R`[src]

Bit 23

`pub fn host_fn2_slc0_ext_bit3_int_ena(&self) -> HOST_FN2_SLC0_EXT_BIT3_INT_ENA_R`[src]

Bit 22

`pub fn host_fn2_slc0_ext_bit2_int_ena(&self) -> HOST_FN2_SLC0_EXT_BIT2_INT_ENA_R`[src]

Bit 21

`pub fn host_fn2_slc0_ext_bit1_int_ena(&self) -> HOST_FN2_SLC0_EXT_BIT1_INT_ENA_R`[src]

Bit 20

`pub fn host_fn2_slc0_ext_bit0_int_ena(&self) -> HOST_FN2_SLC0_EXT_BIT0_INT_ENA_R`[src]

Bit 19

`pub fn host_fn2_slc0_rx_pf_valid_int_ena( &self ) -> HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_R`[src]

Bit 18

`pub fn host_fn2_slc0_tx_ovf_int_ena(&self) -> HOST_FN2_SLC0_TX_OVF_INT_ENA_R`[src]

Bit 17

`pub fn host_fn2_slc0_rx_udf_int_ena(&self) -> HOST_FN2_SLC0_RX_UDF_INT_ENA_R`[src]

Bit 16

`pub fn host_fn2_slc0host_tx_start_int_ena( &self ) -> HOST_FN2_SLC0HOST_TX_START_INT_ENA_R`[src]

Bit 15

`pub fn host_fn2_slc0host_rx_start_int_ena( &self ) -> HOST_FN2_SLC0HOST_RX_START_INT_ENA_R`[src]

Bit 14

`pub fn host_fn2_slc0host_rx_eof_int_ena( &self ) -> HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_R`[src]

Bit 13

`pub fn host_fn2_slc0host_rx_sof_int_ena( &self ) -> HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_R`[src]

Bit 12

`pub fn host_fn2_slc0_token1_0to1_int_ena( &self ) -> HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_R`[src]

Bit 11

`pub fn host_fn2_slc0_token0_0to1_int_ena( &self ) -> HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_R`[src]

Bit 10

`pub fn host_fn2_slc0_token1_1to0_int_ena( &self ) -> HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_R`[src]

Bit 9

`pub fn host_fn2_slc0_token0_1to0_int_ena( &self ) -> HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_R`[src]

Bit 8

`pub fn host_fn2_slc0_tohost_bit7_int_ena( &self ) -> HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_R`[src]

Bit 7

`pub fn host_fn2_slc0_tohost_bit6_int_ena( &self ) -> HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_R`[src]

Bit 6

`pub fn host_fn2_slc0_tohost_bit5_int_ena( &self ) -> HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_R`[src]

Bit 5

`pub fn host_fn2_slc0_tohost_bit4_int_ena( &self ) -> HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_R`[src]

Bit 4

`pub fn host_fn2_slc0_tohost_bit3_int_ena( &self ) -> HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_R`[src]

Bit 3

`pub fn host_fn2_slc0_tohost_bit2_int_ena( &self ) -> HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_R`[src]

Bit 2

`pub fn host_fn2_slc0_tohost_bit1_int_ena( &self ) -> HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_R`[src]

Bit 1

`pub fn host_fn2_slc0_tohost_bit0_int_ena( &self ) -> HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HOST_SLC1HOST_FUNC2_INT_ENA>>`[src]

`pub fn host_fn2_slc1_bt_rx_new_packet_int_ena( &self ) -> HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_R`[src]

Bit 25

`pub fn host_fn2_slc1_host_rd_retry_int_ena( &self ) -> HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_R`[src]

Bit 24

`pub fn host_fn2_slc1_wifi_rx_new_packet_int_ena( &self ) -> HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_R`[src]

Bit 23

`pub fn host_fn2_slc1_ext_bit3_int_ena(&self) -> HOST_FN2_SLC1_EXT_BIT3_INT_ENA_R`[src]

Bit 22

`pub fn host_fn2_slc1_ext_bit2_int_ena(&self) -> HOST_FN2_SLC1_EXT_BIT2_INT_ENA_R`[src]

Bit 21

`pub fn host_fn2_slc1_ext_bit1_int_ena(&self) -> HOST_FN2_SLC1_EXT_BIT1_INT_ENA_R`[src]

Bit 20

`pub fn host_fn2_slc1_ext_bit0_int_ena(&self) -> HOST_FN2_SLC1_EXT_BIT0_INT_ENA_R`[src]

Bit 19

`pub fn host_fn2_slc1_rx_pf_valid_int_ena( &self ) -> HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_R`[src]

Bit 18

`pub fn host_fn2_slc1_tx_ovf_int_ena(&self) -> HOST_FN2_SLC1_TX_OVF_INT_ENA_R`[src]

Bit 17

`pub fn host_fn2_slc1_rx_udf_int_ena(&self) -> HOST_FN2_SLC1_RX_UDF_INT_ENA_R`[src]

Bit 16

`pub fn host_fn2_slc1host_tx_start_int_ena( &self ) -> HOST_FN2_SLC1HOST_TX_START_INT_ENA_R`[src]

Bit 15

`pub fn host_fn2_slc1host_rx_start_int_ena( &self ) -> HOST_FN2_SLC1HOST_RX_START_INT_ENA_R`[src]

Bit 14

`pub fn host_fn2_slc1host_rx_eof_int_ena( &self ) -> HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_R`[src]

Bit 13

`pub fn host_fn2_slc1host_rx_sof_int_ena( &self ) -> HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_R`[src]

Bit 12

`pub fn host_fn2_slc1_token1_0to1_int_ena( &self ) -> HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_R`[src]

Bit 11

`pub fn host_fn2_slc1_token0_0to1_int_ena( &self ) -> HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_R`[src]

Bit 10

`pub fn host_fn2_slc1_token1_1to0_int_ena( &self ) -> HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_R`[src]

Bit 9

`pub fn host_fn2_slc1_token0_1to0_int_ena( &self ) -> HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_R`[src]

Bit 8

`pub fn host_fn2_slc1_tohost_bit7_int_ena( &self ) -> HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_R`[src]

Bit 7

`pub fn host_fn2_slc1_tohost_bit6_int_ena( &self ) -> HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_R`[src]

Bit 6

`pub fn host_fn2_slc1_tohost_bit5_int_ena( &self ) -> HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_R`[src]

Bit 5

`pub fn host_fn2_slc1_tohost_bit4_int_ena( &self ) -> HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_R`[src]

Bit 4

`pub fn host_fn2_slc1_tohost_bit3_int_ena( &self ) -> HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_R`[src]

Bit 3

`pub fn host_fn2_slc1_tohost_bit2_int_ena( &self ) -> HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_R`[src]

Bit 2

`pub fn host_fn2_slc1_tohost_bit1_int_ena( &self ) -> HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_R`[src]

Bit 1

`pub fn host_fn2_slc1_tohost_bit0_int_ena( &self ) -> HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HOST_SLC0HOST_INT_ENA>>`[src]

`pub fn host_gpio_sdio_int_ena(&self) -> HOST_GPIO_SDIO_INT_ENA_R`[src]

Bit 25

`pub fn host_slc0_host_rd_retry_int_ena( &self ) -> HOST_SLC0_HOST_RD_RETRY_INT_ENA_R`[src]

Bit 24

`pub fn host_slc0_rx_new_packet_int_ena( &self ) -> HOST_SLC0_RX_NEW_PACKET_INT_ENA_R`[src]

Bit 23

`pub fn host_slc0_ext_bit3_int_ena(&self) -> HOST_SLC0_EXT_BIT3_INT_ENA_R`[src]

Bit 22

`pub fn host_slc0_ext_bit2_int_ena(&self) -> HOST_SLC0_EXT_BIT2_INT_ENA_R`[src]

Bit 21

`pub fn host_slc0_ext_bit1_int_ena(&self) -> HOST_SLC0_EXT_BIT1_INT_ENA_R`[src]

Bit 20

`pub fn host_slc0_ext_bit0_int_ena(&self) -> HOST_SLC0_EXT_BIT0_INT_ENA_R`[src]

Bit 19

`pub fn host_slc0_rx_pf_valid_int_ena(&self) -> HOST_SLC0_RX_PF_VALID_INT_ENA_R`[src]

Bit 18

`pub fn host_slc0_tx_ovf_int_ena(&self) -> HOST_SLC0_TX_OVF_INT_ENA_R`[src]

Bit 17

`pub fn host_slc0_rx_udf_int_ena(&self) -> HOST_SLC0_RX_UDF_INT_ENA_R`[src]

Bit 16

`pub fn host_slc0host_tx_start_int_ena(&self) -> HOST_SLC0HOST_TX_START_INT_ENA_R`[src]

Bit 15

`pub fn host_slc0host_rx_start_int_ena(&self) -> HOST_SLC0HOST_RX_START_INT_ENA_R`[src]

Bit 14

`pub fn host_slc0host_rx_eof_int_ena(&self) -> HOST_SLC0HOST_RX_EOF_INT_ENA_R`[src]

Bit 13

`pub fn host_slc0host_rx_sof_int_ena(&self) -> HOST_SLC0HOST_RX_SOF_INT_ENA_R`[src]

Bit 12

`pub fn host_slc0_token1_0to1_int_ena(&self) -> HOST_SLC0_TOKEN1_0TO1_INT_ENA_R`[src]

Bit 11

`pub fn host_slc0_token0_0to1_int_ena(&self) -> HOST_SLC0_TOKEN0_0TO1_INT_ENA_R`[src]

Bit 10

`pub fn host_slc0_token1_1to0_int_ena(&self) -> HOST_SLC0_TOKEN1_1TO0_INT_ENA_R`[src]

Bit 9

`pub fn host_slc0_token0_1to0_int_ena(&self) -> HOST_SLC0_TOKEN0_1TO0_INT_ENA_R`[src]

Bit 8

`pub fn host_slc0_tohost_bit7_int_ena(&self) -> HOST_SLC0_TOHOST_BIT7_INT_ENA_R`[src]

Bit 7

`pub fn host_slc0_tohost_bit6_int_ena(&self) -> HOST_SLC0_TOHOST_BIT6_INT_ENA_R`[src]

Bit 6

`pub fn host_slc0_tohost_bit5_int_ena(&self) -> HOST_SLC0_TOHOST_BIT5_INT_ENA_R`[src]

Bit 5

`pub fn host_slc0_tohost_bit4_int_ena(&self) -> HOST_SLC0_TOHOST_BIT4_INT_ENA_R`[src]

Bit 4

`pub fn host_slc0_tohost_bit3_int_ena(&self) -> HOST_SLC0_TOHOST_BIT3_INT_ENA_R`[src]

Bit 3

`pub fn host_slc0_tohost_bit2_int_ena(&self) -> HOST_SLC0_TOHOST_BIT2_INT_ENA_R`[src]

Bit 2

`pub fn host_slc0_tohost_bit1_int_ena(&self) -> HOST_SLC0_TOHOST_BIT1_INT_ENA_R`[src]

Bit 1

`pub fn host_slc0_tohost_bit0_int_ena(&self) -> HOST_SLC0_TOHOST_BIT0_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HOST_SLC1HOST_INT_ENA>>`[src]

`pub fn host_slc1_bt_rx_new_packet_int_ena( &self ) -> HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_R`[src]

Bit 25

`pub fn host_slc1_host_rd_retry_int_ena( &self ) -> HOST_SLC1_HOST_RD_RETRY_INT_ENA_R`[src]

Bit 24

`pub fn host_slc1_wifi_rx_new_packet_int_ena( &self ) -> HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_R`[src]

Bit 23

`pub fn host_slc1_ext_bit3_int_ena(&self) -> HOST_SLC1_EXT_BIT3_INT_ENA_R`[src]

Bit 22

`pub fn host_slc1_ext_bit2_int_ena(&self) -> HOST_SLC1_EXT_BIT2_INT_ENA_R`[src]

Bit 21

`pub fn host_slc1_ext_bit1_int_ena(&self) -> HOST_SLC1_EXT_BIT1_INT_ENA_R`[src]

Bit 20

`pub fn host_slc1_ext_bit0_int_ena(&self) -> HOST_SLC1_EXT_BIT0_INT_ENA_R`[src]

Bit 19

`pub fn host_slc1_rx_pf_valid_int_ena(&self) -> HOST_SLC1_RX_PF_VALID_INT_ENA_R`[src]

Bit 18

`pub fn host_slc1_tx_ovf_int_ena(&self) -> HOST_SLC1_TX_OVF_INT_ENA_R`[src]

Bit 17

`pub fn host_slc1_rx_udf_int_ena(&self) -> HOST_SLC1_RX_UDF_INT_ENA_R`[src]

Bit 16

`pub fn host_slc1host_tx_start_int_ena(&self) -> HOST_SLC1HOST_TX_START_INT_ENA_R`[src]

Bit 15

`pub fn host_slc1host_rx_start_int_ena(&self) -> HOST_SLC1HOST_RX_START_INT_ENA_R`[src]

Bit 14

`pub fn host_slc1host_rx_eof_int_ena(&self) -> HOST_SLC1HOST_RX_EOF_INT_ENA_R`[src]

Bit 13

`pub fn host_slc1host_rx_sof_int_ena(&self) -> HOST_SLC1HOST_RX_SOF_INT_ENA_R`[src]

Bit 12

`pub fn host_slc1_token1_0to1_int_ena(&self) -> HOST_SLC1_TOKEN1_0TO1_INT_ENA_R`[src]

Bit 11

`pub fn host_slc1_token0_0to1_int_ena(&self) -> HOST_SLC1_TOKEN0_0TO1_INT_ENA_R`[src]

Bit 10

`pub fn host_slc1_token1_1to0_int_ena(&self) -> HOST_SLC1_TOKEN1_1TO0_INT_ENA_R`[src]

Bit 9

`pub fn host_slc1_token0_1to0_int_ena(&self) -> HOST_SLC1_TOKEN0_1TO0_INT_ENA_R`[src]

Bit 8

`pub fn host_slc1_tohost_bit7_int_ena(&self) -> HOST_SLC1_TOHOST_BIT7_INT_ENA_R`[src]

Bit 7

`pub fn host_slc1_tohost_bit6_int_ena(&self) -> HOST_SLC1_TOHOST_BIT6_INT_ENA_R`[src]

Bit 6

`pub fn host_slc1_tohost_bit5_int_ena(&self) -> HOST_SLC1_TOHOST_BIT5_INT_ENA_R`[src]

Bit 5

`pub fn host_slc1_tohost_bit4_int_ena(&self) -> HOST_SLC1_TOHOST_BIT4_INT_ENA_R`[src]

Bit 4

`pub fn host_slc1_tohost_bit3_int_ena(&self) -> HOST_SLC1_TOHOST_BIT3_INT_ENA_R`[src]

Bit 3

`pub fn host_slc1_tohost_bit2_int_ena(&self) -> HOST_SLC1_TOHOST_BIT2_INT_ENA_R`[src]

Bit 2

`pub fn host_slc1_tohost_bit1_int_ena(&self) -> HOST_SLC1_TOHOST_BIT1_INT_ENA_R`[src]

Bit 1

`pub fn host_slc1_tohost_bit0_int_ena(&self) -> HOST_SLC1_TOHOST_BIT0_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HOST_SLC0HOST_RX_INFOR>>`[src]

`pub fn host_slc0host_rx_infor(&self) -> HOST_SLC0HOST_RX_INFOR_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HOST_SLC1HOST_RX_INFOR>>`[src]

`pub fn host_slc1host_rx_infor(&self) -> HOST_SLC1HOST_RX_INFOR_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HOST_SLC0HOST_LEN_WD>>`[src]

`pub fn host_slc0host_len_wd(&self) -> HOST_SLC0HOST_LEN_WD_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _HOST_SLC_APBWIN_WDATA>>`[src]

`pub fn host_slc_apbwin_wdata(&self) -> HOST_SLC_APBWIN_WDATA_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _HOST_SLC_APBWIN_CONF>>`[src]

`pub fn host_slc_apbwin_start(&self) -> HOST_SLC_APBWIN_START_R`[src]

Bit 29

`pub fn host_slc_apbwin_wr(&self) -> HOST_SLC_APBWIN_WR_R`[src]

Bit 28

`pub fn host_slc_apbwin_addr(&self) -> HOST_SLC_APBWIN_ADDR_R`[src]

Bits 0:27

`impl R<u32, Reg<u32, _HOST_SLC_APBWIN_RDATA>>`[src]

`pub fn host_slc_apbwin_rdata(&self) -> HOST_SLC_APBWIN_RDATA_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _HOST_SLCHOST_RDCLR0>>`[src]

`pub fn host_slchost_slc0_bit6_clraddr(&self) -> HOST_SLCHOST_SLC0_BIT6_CLRADDR_R`[src]

Bits 9:17

`pub fn host_slchost_slc0_bit7_clraddr(&self) -> HOST_SLCHOST_SLC0_BIT7_CLRADDR_R`[src]

Bits 0:8

`impl R<u32, Reg<u32, _HOST_SLCHOST_RDCLR1>>`[src]

`pub fn host_slchost_slc1_bit6_clraddr(&self) -> HOST_SLCHOST_SLC1_BIT6_CLRADDR_R`[src]

Bits 9:17

`pub fn host_slchost_slc1_bit7_clraddr(&self) -> HOST_SLCHOST_SLC1_BIT7_CLRADDR_R`[src]

Bits 0:8

`impl R<u32, Reg<u32, _HOST_SLC0HOST_INT_ENA1>>`[src]

`pub fn host_gpio_sdio_int_ena1(&self) -> HOST_GPIO_SDIO_INT_ENA1_R`[src]

Bit 25

`pub fn host_slc0_host_rd_retry_int_ena1( &self ) -> HOST_SLC0_HOST_RD_RETRY_INT_ENA1_R`[src]

Bit 24

`pub fn host_slc0_rx_new_packet_int_ena1( &self ) -> HOST_SLC0_RX_NEW_PACKET_INT_ENA1_R`[src]

Bit 23

`pub fn host_slc0_ext_bit3_int_ena1(&self) -> HOST_SLC0_EXT_BIT3_INT_ENA1_R`[src]

Bit 22

`pub fn host_slc0_ext_bit2_int_ena1(&self) -> HOST_SLC0_EXT_BIT2_INT_ENA1_R`[src]

Bit 21

`pub fn host_slc0_ext_bit1_int_ena1(&self) -> HOST_SLC0_EXT_BIT1_INT_ENA1_R`[src]

Bit 20

`pub fn host_slc0_ext_bit0_int_ena1(&self) -> HOST_SLC0_EXT_BIT0_INT_ENA1_R`[src]

Bit 19

`pub fn host_slc0_rx_pf_valid_int_ena1(&self) -> HOST_SLC0_RX_PF_VALID_INT_ENA1_R`[src]

Bit 18

`pub fn host_slc0_tx_ovf_int_ena1(&self) -> HOST_SLC0_TX_OVF_INT_ENA1_R`[src]

Bit 17

`pub fn host_slc0_rx_udf_int_ena1(&self) -> HOST_SLC0_RX_UDF_INT_ENA1_R`[src]

Bit 16

`pub fn host_slc0host_tx_start_int_ena1( &self ) -> HOST_SLC0HOST_TX_START_INT_ENA1_R`[src]

Bit 15

`pub fn host_slc0host_rx_start_int_ena1( &self ) -> HOST_SLC0HOST_RX_START_INT_ENA1_R`[src]

Bit 14

`pub fn host_slc0host_rx_eof_int_ena1(&self) -> HOST_SLC0HOST_RX_EOF_INT_ENA1_R`[src]

Bit 13

`pub fn host_slc0host_rx_sof_int_ena1(&self) -> HOST_SLC0HOST_RX_SOF_INT_ENA1_R`[src]

Bit 12

`pub fn host_slc0_token1_0to1_int_ena1(&self) -> HOST_SLC0_TOKEN1_0TO1_INT_ENA1_R`[src]

Bit 11

`pub fn host_slc0_token0_0to1_int_ena1(&self) -> HOST_SLC0_TOKEN0_0TO1_INT_ENA1_R`[src]

Bit 10

`pub fn host_slc0_token1_1to0_int_ena1(&self) -> HOST_SLC0_TOKEN1_1TO0_INT_ENA1_R`[src]

Bit 9

`pub fn host_slc0_token0_1to0_int_ena1(&self) -> HOST_SLC0_TOKEN0_1TO0_INT_ENA1_R`[src]

Bit 8

`pub fn host_slc0_tohost_bit7_int_ena1(&self) -> HOST_SLC0_TOHOST_BIT7_INT_ENA1_R`[src]

Bit 7

`pub fn host_slc0_tohost_bit6_int_ena1(&self) -> HOST_SLC0_TOHOST_BIT6_INT_ENA1_R`[src]

Bit 6

`pub fn host_slc0_tohost_bit5_int_ena1(&self) -> HOST_SLC0_TOHOST_BIT5_INT_ENA1_R`[src]

Bit 5

`pub fn host_slc0_tohost_bit4_int_ena1(&self) -> HOST_SLC0_TOHOST_BIT4_INT_ENA1_R`[src]

Bit 4

`pub fn host_slc0_tohost_bit3_int_ena1(&self) -> HOST_SLC0_TOHOST_BIT3_INT_ENA1_R`[src]

Bit 3

`pub fn host_slc0_tohost_bit2_int_ena1(&self) -> HOST_SLC0_TOHOST_BIT2_INT_ENA1_R`[src]

Bit 2

`pub fn host_slc0_tohost_bit1_int_ena1(&self) -> HOST_SLC0_TOHOST_BIT1_INT_ENA1_R`[src]

Bit 1

`pub fn host_slc0_tohost_bit0_int_ena1(&self) -> HOST_SLC0_TOHOST_BIT0_INT_ENA1_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HOST_SLC1HOST_INT_ENA1>>`[src]

`pub fn host_slc1_bt_rx_new_packet_int_ena1( &self ) -> HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_R`[src]

Bit 25

`pub fn host_slc1_host_rd_retry_int_ena1( &self ) -> HOST_SLC1_HOST_RD_RETRY_INT_ENA1_R`[src]

Bit 24

`pub fn host_slc1_wifi_rx_new_packet_int_ena1( &self ) -> HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_R`[src]

Bit 23

`pub fn host_slc1_ext_bit3_int_ena1(&self) -> HOST_SLC1_EXT_BIT3_INT_ENA1_R`[src]

Bit 22

`pub fn host_slc1_ext_bit2_int_ena1(&self) -> HOST_SLC1_EXT_BIT2_INT_ENA1_R`[src]

Bit 21

`pub fn host_slc1_ext_bit1_int_ena1(&self) -> HOST_SLC1_EXT_BIT1_INT_ENA1_R`[src]

Bit 20

`pub fn host_slc1_ext_bit0_int_ena1(&self) -> HOST_SLC1_EXT_BIT0_INT_ENA1_R`[src]

Bit 19

`pub fn host_slc1_rx_pf_valid_int_ena1(&self) -> HOST_SLC1_RX_PF_VALID_INT_ENA1_R`[src]

Bit 18

`pub fn host_slc1_tx_ovf_int_ena1(&self) -> HOST_SLC1_TX_OVF_INT_ENA1_R`[src]

Bit 17

`pub fn host_slc1_rx_udf_int_ena1(&self) -> HOST_SLC1_RX_UDF_INT_ENA1_R`[src]

Bit 16

`pub fn host_slc1host_tx_start_int_ena1( &self ) -> HOST_SLC1HOST_TX_START_INT_ENA1_R`[src]

Bit 15

`pub fn host_slc1host_rx_start_int_ena1( &self ) -> HOST_SLC1HOST_RX_START_INT_ENA1_R`[src]

Bit 14

`pub fn host_slc1host_rx_eof_int_ena1(&self) -> HOST_SLC1HOST_RX_EOF_INT_ENA1_R`[src]

Bit 13

`pub fn host_slc1host_rx_sof_int_ena1(&self) -> HOST_SLC1HOST_RX_SOF_INT_ENA1_R`[src]

Bit 12

`pub fn host_slc1_token1_0to1_int_ena1(&self) -> HOST_SLC1_TOKEN1_0TO1_INT_ENA1_R`[src]

Bit 11

`pub fn host_slc1_token0_0to1_int_ena1(&self) -> HOST_SLC1_TOKEN0_0TO1_INT_ENA1_R`[src]

Bit 10

`pub fn host_slc1_token1_1to0_int_ena1(&self) -> HOST_SLC1_TOKEN1_1TO0_INT_ENA1_R`[src]

Bit 9

`pub fn host_slc1_token0_1to0_int_ena1(&self) -> HOST_SLC1_TOKEN0_1TO0_INT_ENA1_R`[src]

Bit 8

`pub fn host_slc1_tohost_bit7_int_ena1(&self) -> HOST_SLC1_TOHOST_BIT7_INT_ENA1_R`[src]

Bit 7

`pub fn host_slc1_tohost_bit6_int_ena1(&self) -> HOST_SLC1_TOHOST_BIT6_INT_ENA1_R`[src]

Bit 6

`pub fn host_slc1_tohost_bit5_int_ena1(&self) -> HOST_SLC1_TOHOST_BIT5_INT_ENA1_R`[src]

Bit 5

`pub fn host_slc1_tohost_bit4_int_ena1(&self) -> HOST_SLC1_TOHOST_BIT4_INT_ENA1_R`[src]

Bit 4

`pub fn host_slc1_tohost_bit3_int_ena1(&self) -> HOST_SLC1_TOHOST_BIT3_INT_ENA1_R`[src]

Bit 3

`pub fn host_slc1_tohost_bit2_int_ena1(&self) -> HOST_SLC1_TOHOST_BIT2_INT_ENA1_R`[src]

Bit 2

`pub fn host_slc1_tohost_bit1_int_ena1(&self) -> HOST_SLC1_TOHOST_BIT1_INT_ENA1_R`[src]

Bit 1

`pub fn host_slc1_tohost_bit0_int_ena1(&self) -> HOST_SLC1_TOHOST_BIT0_INT_ENA1_R`[src]

Bit 0

`impl R<u32, Reg<u32, _HOST_SLCHOSTDATE>>`[src]

`pub fn host_slchost_date(&self) -> HOST_SLCHOST_DATE_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _HOST_SLCHOSTID>>`[src]

`pub fn host_slchost_id(&self) -> HOST_SLCHOST_ID_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _HOST_SLCHOST_CONF>>`[src]

`pub fn host_hspeed_con_en(&self) -> HOST_HSPEED_CON_EN_R`[src]

Bit 27

`pub fn host_sdio_pad_pullup(&self) -> HOST_SDIO_PAD_PULLUP_R`[src]

Bit 26

`pub fn host_sdio20_int_delay(&self) -> HOST_SDIO20_INT_DELAY_R`[src]

Bit 25

`pub fn host_frc_quick_in(&self) -> HOST_FRC_QUICK_IN_R`[src]

Bits 20:24

`pub fn host_frc_pos_samp(&self) -> HOST_FRC_POS_SAMP_R`[src]

Bits 15:19

`pub fn host_frc_neg_samp(&self) -> HOST_FRC_NEG_SAMP_R`[src]

Bits 10:14

`pub fn host_frc_sdio20(&self) -> HOST_FRC_SDIO20_R`[src]

Bits 5:9

`pub fn host_frc_sdio11(&self) -> HOST_FRC_SDIO11_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _HOST_SLCHOST_INF_ST>>`[src]

`pub fn host_sdio_quick_in(&self) -> HOST_SDIO_QUICK_IN_R`[src]

Bits 10:14

`pub fn host_sdio_neg_samp(&self) -> HOST_SDIO_NEG_SAMP_R`[src]

Bits 5:9

`pub fn host_sdio20_mode(&self) -> HOST_SDIO20_MODE_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _CONF0>>`[src]

`pub fn slc1_token_sel(&self) -> SLC1_TOKEN_SEL_R`[src]

Bit 31

`pub fn slc1_token_auto_clr(&self) -> SLC1_TOKEN_AUTO_CLR_R`[src]

Bit 30

`pub fn slc1_txdata_burst_en(&self) -> SLC1_TXDATA_BURST_EN_R`[src]

Bit 29

`pub fn slc1_txdscr_burst_en(&self) -> SLC1_TXDSCR_BURST_EN_R`[src]

Bit 28

`pub fn slc1_txlink_auto_ret(&self) -> SLC1_TXLINK_AUTO_RET_R`[src]

Bit 27

`pub fn slc1_rxlink_auto_ret(&self) -> SLC1_RXLINK_AUTO_RET_R`[src]

Bit 26

`pub fn slc1_rxdata_burst_en(&self) -> SLC1_RXDATA_BURST_EN_R`[src]

Bit 25

`pub fn slc1_rxdscr_burst_en(&self) -> SLC1_RXDSCR_BURST_EN_R`[src]

Bit 24

`pub fn slc1_rx_no_restart_clr(&self) -> SLC1_RX_NO_RESTART_CLR_R`[src]

Bit 23

`pub fn slc1_rx_auto_wrback(&self) -> SLC1_RX_AUTO_WRBACK_R`[src]

Bit 22

`pub fn slc1_rx_loop_test(&self) -> SLC1_RX_LOOP_TEST_R`[src]

Bit 21

`pub fn slc1_tx_loop_test(&self) -> SLC1_TX_LOOP_TEST_R`[src]

Bit 20

`pub fn slc1_wr_retry_mask_en(&self) -> SLC1_WR_RETRY_MASK_EN_R`[src]

Bit 19

`pub fn slc0_wr_retry_mask_en(&self) -> SLC0_WR_RETRY_MASK_EN_R`[src]

Bit 18

`pub fn slc1_rx_rst(&self) -> SLC1_RX_RST_R`[src]

Bit 17

`pub fn slc1_tx_rst(&self) -> SLC1_TX_RST_R`[src]

Bit 16

`pub fn slc0_token_sel(&self) -> SLC0_TOKEN_SEL_R`[src]

Bit 15

`pub fn slc0_token_auto_clr(&self) -> SLC0_TOKEN_AUTO_CLR_R`[src]

Bit 14

`pub fn slc0_txdata_burst_en(&self) -> SLC0_TXDATA_BURST_EN_R`[src]

Bit 13

`pub fn slc0_txdscr_burst_en(&self) -> SLC0_TXDSCR_BURST_EN_R`[src]

Bit 12

`pub fn slc0_txlink_auto_ret(&self) -> SLC0_TXLINK_AUTO_RET_R`[src]

Bit 11

`pub fn slc0_rxlink_auto_ret(&self) -> SLC0_RXLINK_AUTO_RET_R`[src]

Bit 10

`pub fn slc0_rxdata_burst_en(&self) -> SLC0_RXDATA_BURST_EN_R`[src]

Bit 9

`pub fn slc0_rxdscr_burst_en(&self) -> SLC0_RXDSCR_BURST_EN_R`[src]

Bit 8

`pub fn slc0_rx_no_restart_clr(&self) -> SLC0_RX_NO_RESTART_CLR_R`[src]

Bit 7

`pub fn slc0_rx_auto_wrback(&self) -> SLC0_RX_AUTO_WRBACK_R`[src]

Bit 6

`pub fn slc0_rx_loop_test(&self) -> SLC0_RX_LOOP_TEST_R`[src]

Bit 5

`pub fn slc0_tx_loop_test(&self) -> SLC0_TX_LOOP_TEST_R`[src]

Bit 4

`pub fn ahbm_rst(&self) -> AHBM_RST_R`[src]

Bit 3

`pub fn ahbm_fifo_rst(&self) -> AHBM_FIFO_RST_R`[src]

Bit 2

`pub fn slc0_rx_rst(&self) -> SLC0_RX_RST_R`[src]

Bit 1

`pub fn slc0_tx_rst(&self) -> SLC0_TX_RST_R`[src]

Bit 0

`impl R<u32, Reg<u32, __0INT_RAW>>`[src]

`pub fn slc0_rx_quick_eof_int_raw(&self) -> SLC0_RX_QUICK_EOF_INT_RAW_R`[src]

Bit 26

`pub fn cmd_dtc_int_raw(&self) -> CMD_DTC_INT_RAW_R`[src]

Bit 25

`pub fn slc0_tx_err_eof_int_raw(&self) -> SLC0_TX_ERR_EOF_INT_RAW_R`[src]

Bit 24

`pub fn slc0_wr_retry_done_int_raw(&self) -> SLC0_WR_RETRY_DONE_INT_RAW_R`[src]

Bit 23

`pub fn slc0_host_rd_ack_int_raw(&self) -> SLC0_HOST_RD_ACK_INT_RAW_R`[src]

Bit 22

`pub fn slc0_tx_dscr_empty_int_raw(&self) -> SLC0_TX_DSCR_EMPTY_INT_RAW_R`[src]

Bit 21

`pub fn slc0_rx_dscr_err_int_raw(&self) -> SLC0_RX_DSCR_ERR_INT_RAW_R`[src]

Bit 20

`pub fn slc0_tx_dscr_err_int_raw(&self) -> SLC0_TX_DSCR_ERR_INT_RAW_R`[src]

Bit 19

`pub fn slc0_tohost_int_raw(&self) -> SLC0_TOHOST_INT_RAW_R`[src]

Bit 18

`pub fn slc0_rx_eof_int_raw(&self) -> SLC0_RX_EOF_INT_RAW_R`[src]

Bit 17

`pub fn slc0_rx_done_int_raw(&self) -> SLC0_RX_DONE_INT_RAW_R`[src]

Bit 16

`pub fn slc0_tx_suc_eof_int_raw(&self) -> SLC0_TX_SUC_EOF_INT_RAW_R`[src]

Bit 15

`pub fn slc0_tx_done_int_raw(&self) -> SLC0_TX_DONE_INT_RAW_R`[src]

Bit 14

`pub fn slc0_token1_1to0_int_raw(&self) -> SLC0_TOKEN1_1TO0_INT_RAW_R`[src]

Bit 13

`pub fn slc0_token0_1to0_int_raw(&self) -> SLC0_TOKEN0_1TO0_INT_RAW_R`[src]

Bit 12

`pub fn slc0_tx_ovf_int_raw(&self) -> SLC0_TX_OVF_INT_RAW_R`[src]

Bit 11

`pub fn slc0_rx_udf_int_raw(&self) -> SLC0_RX_UDF_INT_RAW_R`[src]

Bit 10

`pub fn slc0_tx_start_int_raw(&self) -> SLC0_TX_START_INT_RAW_R`[src]

Bit 9

`pub fn slc0_rx_start_int_raw(&self) -> SLC0_RX_START_INT_RAW_R`[src]

Bit 8

`pub fn frhost_bit7_int_raw(&self) -> FRHOST_BIT7_INT_RAW_R`[src]

Bit 7

`pub fn frhost_bit6_int_raw(&self) -> FRHOST_BIT6_INT_RAW_R`[src]

Bit 6

`pub fn frhost_bit5_int_raw(&self) -> FRHOST_BIT5_INT_RAW_R`[src]

Bit 5

`pub fn frhost_bit4_int_raw(&self) -> FRHOST_BIT4_INT_RAW_R`[src]

Bit 4

`pub fn frhost_bit3_int_raw(&self) -> FRHOST_BIT3_INT_RAW_R`[src]

Bit 3

`pub fn frhost_bit2_int_raw(&self) -> FRHOST_BIT2_INT_RAW_R`[src]

Bit 2

`pub fn frhost_bit1_int_raw(&self) -> FRHOST_BIT1_INT_RAW_R`[src]

Bit 1

`pub fn frhost_bit0_int_raw(&self) -> FRHOST_BIT0_INT_RAW_R`[src]

Bit 0

`impl R<u32, Reg<u32, __0INT_ST>>`[src]

`pub fn slc0_rx_quick_eof_int_st(&self) -> SLC0_RX_QUICK_EOF_INT_ST_R`[src]

Bit 26

`pub fn cmd_dtc_int_st(&self) -> CMD_DTC_INT_ST_R`[src]

Bit 25

`pub fn slc0_tx_err_eof_int_st(&self) -> SLC0_TX_ERR_EOF_INT_ST_R`[src]

Bit 24

`pub fn slc0_wr_retry_done_int_st(&self) -> SLC0_WR_RETRY_DONE_INT_ST_R`[src]

Bit 23

`pub fn slc0_host_rd_ack_int_st(&self) -> SLC0_HOST_RD_ACK_INT_ST_R`[src]

Bit 22

`pub fn slc0_tx_dscr_empty_int_st(&self) -> SLC0_TX_DSCR_EMPTY_INT_ST_R`[src]

Bit 21

`pub fn slc0_rx_dscr_err_int_st(&self) -> SLC0_RX_DSCR_ERR_INT_ST_R`[src]

Bit 20

`pub fn slc0_tx_dscr_err_int_st(&self) -> SLC0_TX_DSCR_ERR_INT_ST_R`[src]

Bit 19

`pub fn slc0_tohost_int_st(&self) -> SLC0_TOHOST_INT_ST_R`[src]

Bit 18

`pub fn slc0_rx_eof_int_st(&self) -> SLC0_RX_EOF_INT_ST_R`[src]

Bit 17

`pub fn slc0_rx_done_int_st(&self) -> SLC0_RX_DONE_INT_ST_R`[src]

Bit 16

`pub fn slc0_tx_suc_eof_int_st(&self) -> SLC0_TX_SUC_EOF_INT_ST_R`[src]

Bit 15

`pub fn slc0_tx_done_int_st(&self) -> SLC0_TX_DONE_INT_ST_R`[src]

Bit 14

`pub fn slc0_token1_1to0_int_st(&self) -> SLC0_TOKEN1_1TO0_INT_ST_R`[src]

Bit 13

`pub fn slc0_token0_1to0_int_st(&self) -> SLC0_TOKEN0_1TO0_INT_ST_R`[src]

Bit 12

`pub fn slc0_tx_ovf_int_st(&self) -> SLC0_TX_OVF_INT_ST_R`[src]

Bit 11

`pub fn slc0_rx_udf_int_st(&self) -> SLC0_RX_UDF_INT_ST_R`[src]

Bit 10

`pub fn slc0_tx_start_int_st(&self) -> SLC0_TX_START_INT_ST_R`[src]

Bit 9

`pub fn slc0_rx_start_int_st(&self) -> SLC0_RX_START_INT_ST_R`[src]

Bit 8

`pub fn frhost_bit7_int_st(&self) -> FRHOST_BIT7_INT_ST_R`[src]

Bit 7

`pub fn frhost_bit6_int_st(&self) -> FRHOST_BIT6_INT_ST_R`[src]

Bit 6

`pub fn frhost_bit5_int_st(&self) -> FRHOST_BIT5_INT_ST_R`[src]

Bit 5

`pub fn frhost_bit4_int_st(&self) -> FRHOST_BIT4_INT_ST_R`[src]

Bit 4

`pub fn frhost_bit3_int_st(&self) -> FRHOST_BIT3_INT_ST_R`[src]

Bit 3

`pub fn frhost_bit2_int_st(&self) -> FRHOST_BIT2_INT_ST_R`[src]

Bit 2

`pub fn frhost_bit1_int_st(&self) -> FRHOST_BIT1_INT_ST_R`[src]

Bit 1

`pub fn frhost_bit0_int_st(&self) -> FRHOST_BIT0_INT_ST_R`[src]

Bit 0

`impl R<u32, Reg<u32, __0INT_ENA>>`[src]

`pub fn slc0_rx_quick_eof_int_ena(&self) -> SLC0_RX_QUICK_EOF_INT_ENA_R`[src]

Bit 26

`pub fn cmd_dtc_int_ena(&self) -> CMD_DTC_INT_ENA_R`[src]

Bit 25

`pub fn slc0_tx_err_eof_int_ena(&self) -> SLC0_TX_ERR_EOF_INT_ENA_R`[src]

Bit 24

`pub fn slc0_wr_retry_done_int_ena(&self) -> SLC0_WR_RETRY_DONE_INT_ENA_R`[src]

Bit 23

`pub fn slc0_host_rd_ack_int_ena(&self) -> SLC0_HOST_RD_ACK_INT_ENA_R`[src]

Bit 22

`pub fn slc0_tx_dscr_empty_int_ena(&self) -> SLC0_TX_DSCR_EMPTY_INT_ENA_R`[src]

Bit 21

`pub fn slc0_rx_dscr_err_int_ena(&self) -> SLC0_RX_DSCR_ERR_INT_ENA_R`[src]

Bit 20

`pub fn slc0_tx_dscr_err_int_ena(&self) -> SLC0_TX_DSCR_ERR_INT_ENA_R`[src]

Bit 19

`pub fn slc0_tohost_int_ena(&self) -> SLC0_TOHOST_INT_ENA_R`[src]

Bit 18

`pub fn slc0_rx_eof_int_ena(&self) -> SLC0_RX_EOF_INT_ENA_R`[src]

Bit 17

`pub fn slc0_rx_done_int_ena(&self) -> SLC0_RX_DONE_INT_ENA_R`[src]

Bit 16

`pub fn slc0_tx_suc_eof_int_ena(&self) -> SLC0_TX_SUC_EOF_INT_ENA_R`[src]

Bit 15

`pub fn slc0_tx_done_int_ena(&self) -> SLC0_TX_DONE_INT_ENA_R`[src]

Bit 14

`pub fn slc0_token1_1to0_int_ena(&self) -> SLC0_TOKEN1_1TO0_INT_ENA_R`[src]

Bit 13

`pub fn slc0_token0_1to0_int_ena(&self) -> SLC0_TOKEN0_1TO0_INT_ENA_R`[src]

Bit 12

`pub fn slc0_tx_ovf_int_ena(&self) -> SLC0_TX_OVF_INT_ENA_R`[src]

Bit 11

`pub fn slc0_rx_udf_int_ena(&self) -> SLC0_RX_UDF_INT_ENA_R`[src]

Bit 10

`pub fn slc0_tx_start_int_ena(&self) -> SLC0_TX_START_INT_ENA_R`[src]

Bit 9

`pub fn slc0_rx_start_int_ena(&self) -> SLC0_RX_START_INT_ENA_R`[src]

Bit 8

`pub fn frhost_bit7_int_ena(&self) -> FRHOST_BIT7_INT_ENA_R`[src]

Bit 7

`pub fn frhost_bit6_int_ena(&self) -> FRHOST_BIT6_INT_ENA_R`[src]

Bit 6

`pub fn frhost_bit5_int_ena(&self) -> FRHOST_BIT5_INT_ENA_R`[src]

Bit 5

`pub fn frhost_bit4_int_ena(&self) -> FRHOST_BIT4_INT_ENA_R`[src]

Bit 4

`pub fn frhost_bit3_int_ena(&self) -> FRHOST_BIT3_INT_ENA_R`[src]

Bit 3

`pub fn frhost_bit2_int_ena(&self) -> FRHOST_BIT2_INT_ENA_R`[src]

Bit 2

`pub fn frhost_bit1_int_ena(&self) -> FRHOST_BIT1_INT_ENA_R`[src]

Bit 1

`pub fn frhost_bit0_int_ena(&self) -> FRHOST_BIT0_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, __0INT_CLR>>`[src]

`pub fn slc0_rx_quick_eof_int_clr(&self) -> SLC0_RX_QUICK_EOF_INT_CLR_R`[src]

Bit 26

`pub fn cmd_dtc_int_clr(&self) -> CMD_DTC_INT_CLR_R`[src]

Bit 25

`pub fn slc0_tx_err_eof_int_clr(&self) -> SLC0_TX_ERR_EOF_INT_CLR_R`[src]

Bit 24

`pub fn slc0_wr_retry_done_int_clr(&self) -> SLC0_WR_RETRY_DONE_INT_CLR_R`[src]

Bit 23

`pub fn slc0_host_rd_ack_int_clr(&self) -> SLC0_HOST_RD_ACK_INT_CLR_R`[src]

Bit 22

`pub fn slc0_tx_dscr_empty_int_clr(&self) -> SLC0_TX_DSCR_EMPTY_INT_CLR_R`[src]

Bit 21

`pub fn slc0_rx_dscr_err_int_clr(&self) -> SLC0_RX_DSCR_ERR_INT_CLR_R`[src]

Bit 20

`pub fn slc0_tx_dscr_err_int_clr(&self) -> SLC0_TX_DSCR_ERR_INT_CLR_R`[src]

Bit 19

`pub fn slc0_tohost_int_clr(&self) -> SLC0_TOHOST_INT_CLR_R`[src]

Bit 18

`pub fn slc0_rx_eof_int_clr(&self) -> SLC0_RX_EOF_INT_CLR_R`[src]

Bit 17

`pub fn slc0_rx_done_int_clr(&self) -> SLC0_RX_DONE_INT_CLR_R`[src]

Bit 16

`pub fn slc0_tx_suc_eof_int_clr(&self) -> SLC0_TX_SUC_EOF_INT_CLR_R`[src]

Bit 15

`pub fn slc0_tx_done_int_clr(&self) -> SLC0_TX_DONE_INT_CLR_R`[src]

Bit 14

`pub fn slc0_token1_1to0_int_clr(&self) -> SLC0_TOKEN1_1TO0_INT_CLR_R`[src]

Bit 13

`pub fn slc0_token0_1to0_int_clr(&self) -> SLC0_TOKEN0_1TO0_INT_CLR_R`[src]

Bit 12

`pub fn slc0_tx_ovf_int_clr(&self) -> SLC0_TX_OVF_INT_CLR_R`[src]

Bit 11

`pub fn slc0_rx_udf_int_clr(&self) -> SLC0_RX_UDF_INT_CLR_R`[src]

Bit 10

`pub fn slc0_tx_start_int_clr(&self) -> SLC0_TX_START_INT_CLR_R`[src]

Bit 9

`pub fn slc0_rx_start_int_clr(&self) -> SLC0_RX_START_INT_CLR_R`[src]

Bit 8

`pub fn frhost_bit7_int_clr(&self) -> FRHOST_BIT7_INT_CLR_R`[src]

Bit 7

`pub fn frhost_bit6_int_clr(&self) -> FRHOST_BIT6_INT_CLR_R`[src]

Bit 6

`pub fn frhost_bit5_int_clr(&self) -> FRHOST_BIT5_INT_CLR_R`[src]

Bit 5

`pub fn frhost_bit4_int_clr(&self) -> FRHOST_BIT4_INT_CLR_R`[src]

Bit 4

`pub fn frhost_bit3_int_clr(&self) -> FRHOST_BIT3_INT_CLR_R`[src]

Bit 3

`pub fn frhost_bit2_int_clr(&self) -> FRHOST_BIT2_INT_CLR_R`[src]

Bit 2

`pub fn frhost_bit1_int_clr(&self) -> FRHOST_BIT1_INT_CLR_R`[src]

Bit 1

`pub fn frhost_bit0_int_clr(&self) -> FRHOST_BIT0_INT_CLR_R`[src]

Bit 0

`impl R<u32, Reg<u32, __1INT_RAW>>`[src]

`pub fn slc1_tx_err_eof_int_raw(&self) -> SLC1_TX_ERR_EOF_INT_RAW_R`[src]

Bit 24

`pub fn slc1_wr_retry_done_int_raw(&self) -> SLC1_WR_RETRY_DONE_INT_RAW_R`[src]

Bit 23

`pub fn slc1_host_rd_ack_int_raw(&self) -> SLC1_HOST_RD_ACK_INT_RAW_R`[src]

Bit 22

`pub fn slc1_tx_dscr_empty_int_raw(&self) -> SLC1_TX_DSCR_EMPTY_INT_RAW_R`[src]

Bit 21

`pub fn slc1_rx_dscr_err_int_raw(&self) -> SLC1_RX_DSCR_ERR_INT_RAW_R`[src]

Bit 20

`pub fn slc1_tx_dscr_err_int_raw(&self) -> SLC1_TX_DSCR_ERR_INT_RAW_R`[src]

Bit 19

`pub fn slc1_tohost_int_raw(&self) -> SLC1_TOHOST_INT_RAW_R`[src]

Bit 18

`pub fn slc1_rx_eof_int_raw(&self) -> SLC1_RX_EOF_INT_RAW_R`[src]

Bit 17

`pub fn slc1_rx_done_int_raw(&self) -> SLC1_RX_DONE_INT_RAW_R`[src]

Bit 16

`pub fn slc1_tx_suc_eof_int_raw(&self) -> SLC1_TX_SUC_EOF_INT_RAW_R`[src]

Bit 15

`pub fn slc1_tx_done_int_raw(&self) -> SLC1_TX_DONE_INT_RAW_R`[src]

Bit 14

`pub fn slc1_token1_1to0_int_raw(&self) -> SLC1_TOKEN1_1TO0_INT_RAW_R`[src]

Bit 13

`pub fn slc1_token0_1to0_int_raw(&self) -> SLC1_TOKEN0_1TO0_INT_RAW_R`[src]

Bit 12

`pub fn slc1_tx_ovf_int_raw(&self) -> SLC1_TX_OVF_INT_RAW_R`[src]

Bit 11

`pub fn slc1_rx_udf_int_raw(&self) -> SLC1_RX_UDF_INT_RAW_R`[src]

Bit 10

`pub fn slc1_tx_start_int_raw(&self) -> SLC1_TX_START_INT_RAW_R`[src]

Bit 9

`pub fn slc1_rx_start_int_raw(&self) -> SLC1_RX_START_INT_RAW_R`[src]

Bit 8

`pub fn frhost_bit15_int_raw(&self) -> FRHOST_BIT15_INT_RAW_R`[src]

Bit 7

`pub fn frhost_bit14_int_raw(&self) -> FRHOST_BIT14_INT_RAW_R`[src]

Bit 6

`pub fn frhost_bit13_int_raw(&self) -> FRHOST_BIT13_INT_RAW_R`[src]

Bit 5

`pub fn frhost_bit12_int_raw(&self) -> FRHOST_BIT12_INT_RAW_R`[src]

Bit 4

`pub fn frhost_bit11_int_raw(&self) -> FRHOST_BIT11_INT_RAW_R`[src]

Bit 3

`pub fn frhost_bit10_int_raw(&self) -> FRHOST_BIT10_INT_RAW_R`[src]

Bit 2

`pub fn frhost_bit9_int_raw(&self) -> FRHOST_BIT9_INT_RAW_R`[src]

Bit 1

`pub fn frhost_bit8_int_raw(&self) -> FRHOST_BIT8_INT_RAW_R`[src]

Bit 0

`impl R<u32, Reg<u32, __1INT_ST>>`[src]

`pub fn slc1_tx_err_eof_int_st(&self) -> SLC1_TX_ERR_EOF_INT_ST_R`[src]

Bit 24

`pub fn slc1_wr_retry_done_int_st(&self) -> SLC1_WR_RETRY_DONE_INT_ST_R`[src]

Bit 23

`pub fn slc1_host_rd_ack_int_st(&self) -> SLC1_HOST_RD_ACK_INT_ST_R`[src]

Bit 22

`pub fn slc1_tx_dscr_empty_int_st(&self) -> SLC1_TX_DSCR_EMPTY_INT_ST_R`[src]

Bit 21

`pub fn slc1_rx_dscr_err_int_st(&self) -> SLC1_RX_DSCR_ERR_INT_ST_R`[src]

Bit 20

`pub fn slc1_tx_dscr_err_int_st(&self) -> SLC1_TX_DSCR_ERR_INT_ST_R`[src]

Bit 19

`pub fn slc1_tohost_int_st(&self) -> SLC1_TOHOST_INT_ST_R`[src]

Bit 18

`pub fn slc1_rx_eof_int_st(&self) -> SLC1_RX_EOF_INT_ST_R`[src]

Bit 17

`pub fn slc1_rx_done_int_st(&self) -> SLC1_RX_DONE_INT_ST_R`[src]

Bit 16

`pub fn slc1_tx_suc_eof_int_st(&self) -> SLC1_TX_SUC_EOF_INT_ST_R`[src]

Bit 15

`pub fn slc1_tx_done_int_st(&self) -> SLC1_TX_DONE_INT_ST_R`[src]

Bit 14

`pub fn slc1_token1_1to0_int_st(&self) -> SLC1_TOKEN1_1TO0_INT_ST_R`[src]

Bit 13

`pub fn slc1_token0_1to0_int_st(&self) -> SLC1_TOKEN0_1TO0_INT_ST_R`[src]

Bit 12

`pub fn slc1_tx_ovf_int_st(&self) -> SLC1_TX_OVF_INT_ST_R`[src]

Bit 11

`pub fn slc1_rx_udf_int_st(&self) -> SLC1_RX_UDF_INT_ST_R`[src]

Bit 10

`pub fn slc1_tx_start_int_st(&self) -> SLC1_TX_START_INT_ST_R`[src]

Bit 9

`pub fn slc1_rx_start_int_st(&self) -> SLC1_RX_START_INT_ST_R`[src]

Bit 8

`pub fn frhost_bit15_int_st(&self) -> FRHOST_BIT15_INT_ST_R`[src]

Bit 7

`pub fn frhost_bit14_int_st(&self) -> FRHOST_BIT14_INT_ST_R`[src]

Bit 6

`pub fn frhost_bit13_int_st(&self) -> FRHOST_BIT13_INT_ST_R`[src]

Bit 5

`pub fn frhost_bit12_int_st(&self) -> FRHOST_BIT12_INT_ST_R`[src]

Bit 4

`pub fn frhost_bit11_int_st(&self) -> FRHOST_BIT11_INT_ST_R`[src]

Bit 3

`pub fn frhost_bit10_int_st(&self) -> FRHOST_BIT10_INT_ST_R`[src]

Bit 2

`pub fn frhost_bit9_int_st(&self) -> FRHOST_BIT9_INT_ST_R`[src]

Bit 1

`pub fn frhost_bit8_int_st(&self) -> FRHOST_BIT8_INT_ST_R`[src]

Bit 0

`impl R<u32, Reg<u32, __1INT_ENA>>`[src]

`pub fn slc1_tx_err_eof_int_ena(&self) -> SLC1_TX_ERR_EOF_INT_ENA_R`[src]

Bit 24

`pub fn slc1_wr_retry_done_int_ena(&self) -> SLC1_WR_RETRY_DONE_INT_ENA_R`[src]

Bit 23

`pub fn slc1_host_rd_ack_int_ena(&self) -> SLC1_HOST_RD_ACK_INT_ENA_R`[src]

Bit 22

`pub fn slc1_tx_dscr_empty_int_ena(&self) -> SLC1_TX_DSCR_EMPTY_INT_ENA_R`[src]

Bit 21

`pub fn slc1_rx_dscr_err_int_ena(&self) -> SLC1_RX_DSCR_ERR_INT_ENA_R`[src]

Bit 20

`pub fn slc1_tx_dscr_err_int_ena(&self) -> SLC1_TX_DSCR_ERR_INT_ENA_R`[src]

Bit 19

`pub fn slc1_tohost_int_ena(&self) -> SLC1_TOHOST_INT_ENA_R`[src]

Bit 18

`pub fn slc1_rx_eof_int_ena(&self) -> SLC1_RX_EOF_INT_ENA_R`[src]

Bit 17

`pub fn slc1_rx_done_int_ena(&self) -> SLC1_RX_DONE_INT_ENA_R`[src]

Bit 16

`pub fn slc1_tx_suc_eof_int_ena(&self) -> SLC1_TX_SUC_EOF_INT_ENA_R`[src]

Bit 15

`pub fn slc1_tx_done_int_ena(&self) -> SLC1_TX_DONE_INT_ENA_R`[src]

Bit 14

`pub fn slc1_token1_1to0_int_ena(&self) -> SLC1_TOKEN1_1TO0_INT_ENA_R`[src]

Bit 13

`pub fn slc1_token0_1to0_int_ena(&self) -> SLC1_TOKEN0_1TO0_INT_ENA_R`[src]

Bit 12

`pub fn slc1_tx_ovf_int_ena(&self) -> SLC1_TX_OVF_INT_ENA_R`[src]

Bit 11

`pub fn slc1_rx_udf_int_ena(&self) -> SLC1_RX_UDF_INT_ENA_R`[src]

Bit 10

`pub fn slc1_tx_start_int_ena(&self) -> SLC1_TX_START_INT_ENA_R`[src]

Bit 9

`pub fn slc1_rx_start_int_ena(&self) -> SLC1_RX_START_INT_ENA_R`[src]

Bit 8

`pub fn frhost_bit15_int_ena(&self) -> FRHOST_BIT15_INT_ENA_R`[src]

Bit 7

`pub fn frhost_bit14_int_ena(&self) -> FRHOST_BIT14_INT_ENA_R`[src]

Bit 6

`pub fn frhost_bit13_int_ena(&self) -> FRHOST_BIT13_INT_ENA_R`[src]

Bit 5

`pub fn frhost_bit12_int_ena(&self) -> FRHOST_BIT12_INT_ENA_R`[src]

Bit 4

`pub fn frhost_bit11_int_ena(&self) -> FRHOST_BIT11_INT_ENA_R`[src]

Bit 3

`pub fn frhost_bit10_int_ena(&self) -> FRHOST_BIT10_INT_ENA_R`[src]

Bit 2

`pub fn frhost_bit9_int_ena(&self) -> FRHOST_BIT9_INT_ENA_R`[src]

Bit 1

`pub fn frhost_bit8_int_ena(&self) -> FRHOST_BIT8_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, __1INT_CLR>>`[src]

`pub fn slc1_tx_err_eof_int_clr(&self) -> SLC1_TX_ERR_EOF_INT_CLR_R`[src]

Bit 24

`pub fn slc1_wr_retry_done_int_clr(&self) -> SLC1_WR_RETRY_DONE_INT_CLR_R`[src]

Bit 23

`pub fn slc1_host_rd_ack_int_clr(&self) -> SLC1_HOST_RD_ACK_INT_CLR_R`[src]

Bit 22

`pub fn slc1_tx_dscr_empty_int_clr(&self) -> SLC1_TX_DSCR_EMPTY_INT_CLR_R`[src]

Bit 21

`pub fn slc1_rx_dscr_err_int_clr(&self) -> SLC1_RX_DSCR_ERR_INT_CLR_R`[src]

Bit 20

`pub fn slc1_tx_dscr_err_int_clr(&self) -> SLC1_TX_DSCR_ERR_INT_CLR_R`[src]

Bit 19

`pub fn slc1_tohost_int_clr(&self) -> SLC1_TOHOST_INT_CLR_R`[src]

Bit 18

`pub fn slc1_rx_eof_int_clr(&self) -> SLC1_RX_EOF_INT_CLR_R`[src]

Bit 17

`pub fn slc1_rx_done_int_clr(&self) -> SLC1_RX_DONE_INT_CLR_R`[src]

Bit 16

`pub fn slc1_tx_suc_eof_int_clr(&self) -> SLC1_TX_SUC_EOF_INT_CLR_R`[src]

Bit 15

`pub fn slc1_tx_done_int_clr(&self) -> SLC1_TX_DONE_INT_CLR_R`[src]

Bit 14

`pub fn slc1_token1_1to0_int_clr(&self) -> SLC1_TOKEN1_1TO0_INT_CLR_R`[src]

Bit 13

`pub fn slc1_token0_1to0_int_clr(&self) -> SLC1_TOKEN0_1TO0_INT_CLR_R`[src]

Bit 12

`pub fn slc1_tx_ovf_int_clr(&self) -> SLC1_TX_OVF_INT_CLR_R`[src]

Bit 11

`pub fn slc1_rx_udf_int_clr(&self) -> SLC1_RX_UDF_INT_CLR_R`[src]

Bit 10

`pub fn slc1_tx_start_int_clr(&self) -> SLC1_TX_START_INT_CLR_R`[src]

Bit 9

`pub fn slc1_rx_start_int_clr(&self) -> SLC1_RX_START_INT_CLR_R`[src]

Bit 8

`pub fn frhost_bit15_int_clr(&self) -> FRHOST_BIT15_INT_CLR_R`[src]

Bit 7

`pub fn frhost_bit14_int_clr(&self) -> FRHOST_BIT14_INT_CLR_R`[src]

Bit 6

`pub fn frhost_bit13_int_clr(&self) -> FRHOST_BIT13_INT_CLR_R`[src]

Bit 5

`pub fn frhost_bit12_int_clr(&self) -> FRHOST_BIT12_INT_CLR_R`[src]

Bit 4

`pub fn frhost_bit11_int_clr(&self) -> FRHOST_BIT11_INT_CLR_R`[src]

Bit 3

`pub fn frhost_bit10_int_clr(&self) -> FRHOST_BIT10_INT_CLR_R`[src]

Bit 2

`pub fn frhost_bit9_int_clr(&self) -> FRHOST_BIT9_INT_CLR_R`[src]

Bit 1

`pub fn frhost_bit8_int_clr(&self) -> FRHOST_BIT8_INT_CLR_R`[src]

Bit 0

`impl R<u32, Reg<u32, _RX_STATUS>>`[src]

`pub fn slc1_rx_empty(&self) -> SLC1_RX_EMPTY_R`[src]

Bit 17

`pub fn slc1_rx_full(&self) -> SLC1_RX_FULL_R`[src]

`pub fn slc0_tx_empty(&self) -> SLC0_TX_EMPTY_R`[src]

Bit 1

`pub fn slc0_tx_full(&self) -> SLC0_TX_FULL_R`[src]

Bit 0

`impl R<u32, Reg<u32, __0TXFIFO_POP>>`[src]

`pub fn slc0_txfifo_pop(&self) -> SLC0_TXFIFO_POP_R`[src]

Bit 16

`pub fn slc0_txfifo_rdata(&self) -> SLC0_TXFIFO_RDATA_R`[src]

Bits 0:10

Bit 29

`pub fn slc1_rxlink_stop(&self) -> SLC1_RXLINK_STOP_R`[src]

Bit 28

`pub fn slc1_bt_packet(&self) -> SLC1_BT_PACKET_R`[src]

Bit 20

`pub fn slc1_rxlink_addr(&self) -> SLC1_RXLINK_ADDR_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, __1TX_LINK>>`[src]

`pub fn slc1_txlink_park(&self) -> SLC1_TXLINK_PARK_R`[src]

Bit 31

`pub fn slc1_txlink_restart(&self) -> SLC1_TXLINK_RESTART_R`[src]

Bit 30

`pub fn slc1_txlink_start(&self) -> SLC1_TXLINK_START_R`[src]

Bit 29

`pub fn slc1_txlink_stop(&self) -> SLC1_TXLINK_STOP_R`[src]

Bit 28

`pub fn slc1_txlink_addr(&self) -> SLC1_TXLINK_ADDR_R`[src]

Bits 0:19

Bit 20

`pub fn host_int_level_sel(&self) -> HOST_INT_LEVEL_SEL_R`[src]

Bit 19

`pub fn slc1_rx_check_sum_en(&self) -> SLC1_RX_CHECK_SUM_EN_R`[src]

Bit 18

`pub fn slc1_tx_check_sum_en(&self) -> SLC1_TX_CHECK_SUM_EN_R`[src]

Bit 17

`pub fn slc1_check_owner(&self) -> SLC1_CHECK_OWNER_R`[src]

Bit 16

`pub fn slc0_rx_stitch_en(&self) -> SLC0_RX_STITCH_EN_R`[src]

Bit 6

`pub fn slc0_tx_stitch_en(&self) -> SLC0_TX_STITCH_EN_R`[src]

Bit 5

`pub fn slc0_len_auto_clr(&self) -> SLC0_LEN_AUTO_CLR_R`[src]

Bit 4

`pub fn cmd_hold_en(&self) -> CMD_HOLD_EN_R`[src]

Bit 3

`pub fn slc0_rx_check_sum_en(&self) -> SLC0_RX_CHECK_SUM_EN_R`[src]

Bit 2

`pub fn slc0_tx_check_sum_en(&self) -> SLC0_TX_CHECK_SUM_EN_R`[src]

Bit 1

`pub fn slc0_check_owner(&self) -> SLC0_CHECK_OWNER_R`[src]

Bit 0

`impl R<u32, Reg<u32, __0_STATE0>>`[src]

`pub fn slc0_state0(&self) -> SLC0_STATE0_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, __0_STATE1>>`[src]

`pub fn slc0_state1(&self) -> SLC0_STATE1_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, __1_STATE0>>`[src]

`pub fn slc1_state0(&self) -> SLC1_STATE0_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, __1_STATE1>>`[src]

`pub fn slc1_state1(&self) -> SLC1_STATE1_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _BRIDGE_CONF>>`[src]

`pub fn tx_push_idle_num(&self) -> TX_PUSH_IDLE_NUM_R`[src]

Bits 16:31

`pub fn slc1_tx_dummy_mode(&self) -> SLC1_TX_DUMMY_MODE_R`[src]

Bit 14

`pub fn hda_map_128k(&self) -> HDA_MAP_128K_R`[src]

Bit 13

`pub fn slc0_tx_dummy_mode(&self) -> SLC0_TX_DUMMY_MODE_R`[src]

Bit 12

`pub fn fifo_map_ena(&self) -> FIFO_MAP_ENA_R`[src]

`pub fn ahb_testmode(&self) -> AHB_TESTMODE_R`[src]

Bits 0:2

`impl R<u32, Reg<u32, _SDIO_ST>>`[src]

`pub fn func2_acc_state(&self) -> FUNC2_ACC_STATE_R`[src]

Bits 24:28

`pub fn func1_acc_state(&self) -> FUNC1_ACC_STATE_R`[src]

Bits 16:20

`pub fn bus_st(&self) -> BUS_ST_R`[src]

Bits 12:14

`pub fn sdio_wakeup(&self) -> SDIO_WAKEUP_R`[src]

Bit 8

`pub fn func_st(&self) -> FUNC_ST_R`[src]

Bits 4:7

`pub fn cmd_st(&self) -> CMD_ST_R`[src]

Bits 0:2

`impl R<u32, Reg<u32, _RX_DSCR_CONF>>`[src]

`pub fn slc1_rd_retry_threshold(&self) -> SLC1_RD_RETRY_THRESHOLD_R`[src]

Bits 21:31

`pub fn slc1_rx_fill_en(&self) -> SLC1_RX_FILL_EN_R`[src]

Bit 20

`pub fn slc1_rx_eof_mode(&self) -> SLC1_RX_EOF_MODE_R`[src]

Bit 19

`pub fn slc1_rx_fill_mode(&self) -> SLC1_RX_FILL_MODE_R`[src]

Bit 18

`pub fn slc1_infor_no_replace(&self) -> SLC1_INFOR_NO_REPLACE_R`[src]

Bit 17

`pub fn slc1_token_no_replace(&self) -> SLC1_TOKEN_NO_REPLACE_R`[src]

Bit 16

`pub fn slc0_rd_retry_threshold(&self) -> SLC0_RD_RETRY_THRESHOLD_R`[src]

Bits 5:15

`pub fn slc0_rx_fill_en(&self) -> SLC0_RX_FILL_EN_R`[src]

Bit 4

`pub fn slc0_rx_eof_mode(&self) -> SLC0_RX_EOF_MODE_R`[src]

Bit 3

`pub fn slc0_rx_fill_mode(&self) -> SLC0_RX_FILL_MODE_R`[src]

Bit 2

`pub fn slc0_infor_no_replace(&self) -> SLC0_INFOR_NO_REPLACE_R`[src]

Bit 1

`pub fn slc0_token_no_replace(&self) -> SLC0_TOKEN_NO_REPLACE_R`[src]

`impl R<u32, Reg<u32, _TX_DSCR_CONF>>`[src]

`pub fn wr_retry_threshold(&self) -> WR_RETRY_THRESHOLD_R`[src]

Bits 0:10

`impl R<u32, Reg<u32, _CMD_INFOR0>>`[src]

`pub fn cmd_content0(&self) -> CMD_CONTENT0_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _CMD_INFOR1>>`[src]

`pub fn cmd_content1(&self) -> CMD_CONTENT1_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, __0_LEN_CONF>>`[src]

`pub fn slc0_tx_new_pkt_ind(&self) -> SLC0_TX_NEW_PKT_IND_R`[src]

Bit 28

`pub fn slc0_rx_new_pkt_ind(&self) -> SLC0_RX_NEW_PKT_IND_R`[src]

Bit 27

`pub fn slc0_tx_get_used_dscr(&self) -> SLC0_TX_GET_USED_DSCR_R`[src]

Bit 26

`pub fn slc0_rx_get_used_dscr(&self) -> SLC0_RX_GET_USED_DSCR_R`[src]

Bit 25

`pub fn slc0_tx_packet_load_en(&self) -> SLC0_TX_PACKET_LOAD_EN_R`[src]

Bit 24

`pub fn slc0_rx_packet_load_en(&self) -> SLC0_RX_PACKET_LOAD_EN_R`[src]

Bit 23

`pub fn slc0_len_inc_more(&self) -> SLC0_LEN_INC_MORE_R`[src]

Bit 22

`pub fn slc0_len_inc(&self) -> SLC0_LEN_INC_R`[src]

Bit 21

`pub fn slc0_len_wr(&self) -> SLC0_LEN_WR_R`[src]

`impl R<u32, Reg<u32, _SEQ_POSITION>>`[src]

`pub fn slc1_seq_position(&self) -> SLC1_SEQ_POSITION_R`[src]

Bits 8:15

`pub fn slc0_seq_position(&self) -> SLC0_SEQ_POSITION_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, __0_DSCR_REC_CONF>>`[src]

`pub fn slc0_rx_dscr_rec_lim(&self) -> SLC0_RX_DSCR_REC_LIM_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _SDIO_CRC_ST0>>`[src]

`pub fn dat3_crc_err_cnt(&self) -> DAT3_CRC_ERR_CNT_R`[src]

Bits 24:31

`pub fn dat2_crc_err_cnt(&self) -> DAT2_CRC_ERR_CNT_R`[src]

Bits 16:23

`pub fn dat1_crc_err_cnt(&self) -> DAT1_CRC_ERR_CNT_R`[src]

Bits 8:15

`pub fn dat0_crc_err_cnt(&self) -> DAT0_CRC_ERR_CNT_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _SDIO_CRC_ST1>>`[src]

`pub fn err_cnt_clr(&self) -> ERR_CNT_CLR_R`[src]

`pub fn slc0_rx_dscr_cnt_lat(&self) -> SLC0_RX_DSCR_CNT_LAT_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, __0_LEN_LIM_CONF>>`[src]

`pub fn slc0_len_lim(&self) -> SLC0_LEN_LIM_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, __0INT_ST1>>`[src]

`pub fn slc0_rx_quick_eof_int_st1(&self) -> SLC0_RX_QUICK_EOF_INT_ST1_R`[src]

Bit 26

`pub fn cmd_dtc_int_st1(&self) -> CMD_DTC_INT_ST1_R`[src]

Bit 25

`pub fn slc0_tx_err_eof_int_st1(&self) -> SLC0_TX_ERR_EOF_INT_ST1_R`[src]

Bit 24

`pub fn slc0_wr_retry_done_int_st1(&self) -> SLC0_WR_RETRY_DONE_INT_ST1_R`[src]

Bit 23

`pub fn slc0_host_rd_ack_int_st1(&self) -> SLC0_HOST_RD_ACK_INT_ST1_R`[src]

Bit 22

`pub fn slc0_tx_dscr_empty_int_st1(&self) -> SLC0_TX_DSCR_EMPTY_INT_ST1_R`[src]

Bit 21

`pub fn slc0_rx_dscr_err_int_st1(&self) -> SLC0_RX_DSCR_ERR_INT_ST1_R`[src]

Bit 20

`pub fn slc0_tx_dscr_err_int_st1(&self) -> SLC0_TX_DSCR_ERR_INT_ST1_R`[src]

Bit 19

`pub fn slc0_tohost_int_st1(&self) -> SLC0_TOHOST_INT_ST1_R`[src]

Bit 18

`pub fn slc0_rx_eof_int_st1(&self) -> SLC0_RX_EOF_INT_ST1_R`[src]

Bit 17

`pub fn slc0_rx_done_int_st1(&self) -> SLC0_RX_DONE_INT_ST1_R`[src]

Bit 16

`pub fn slc0_tx_suc_eof_int_st1(&self) -> SLC0_TX_SUC_EOF_INT_ST1_R`[src]

Bit 15

`pub fn slc0_tx_done_int_st1(&self) -> SLC0_TX_DONE_INT_ST1_R`[src]

Bit 14

`pub fn slc0_token1_1to0_int_st1(&self) -> SLC0_TOKEN1_1TO0_INT_ST1_R`[src]

Bit 13

`pub fn slc0_token0_1to0_int_st1(&self) -> SLC0_TOKEN0_1TO0_INT_ST1_R`[src]

Bit 12

`pub fn slc0_tx_ovf_int_st1(&self) -> SLC0_TX_OVF_INT_ST1_R`[src]

Bit 11

`pub fn slc0_rx_udf_int_st1(&self) -> SLC0_RX_UDF_INT_ST1_R`[src]

Bit 10

`pub fn slc0_tx_start_int_st1(&self) -> SLC0_TX_START_INT_ST1_R`[src]

Bit 9

`pub fn slc0_rx_start_int_st1(&self) -> SLC0_RX_START_INT_ST1_R`[src]

Bit 8

`pub fn frhost_bit7_int_st1(&self) -> FRHOST_BIT7_INT_ST1_R`[src]

Bit 7

`pub fn frhost_bit6_int_st1(&self) -> FRHOST_BIT6_INT_ST1_R`[src]

Bit 6

`pub fn frhost_bit5_int_st1(&self) -> FRHOST_BIT5_INT_ST1_R`[src]

Bit 5

`pub fn frhost_bit4_int_st1(&self) -> FRHOST_BIT4_INT_ST1_R`[src]

Bit 4

`pub fn frhost_bit3_int_st1(&self) -> FRHOST_BIT3_INT_ST1_R`[src]

Bit 3

`pub fn frhost_bit2_int_st1(&self) -> FRHOST_BIT2_INT_ST1_R`[src]

Bit 2

`pub fn frhost_bit1_int_st1(&self) -> FRHOST_BIT1_INT_ST1_R`[src]

Bit 1

`pub fn frhost_bit0_int_st1(&self) -> FRHOST_BIT0_INT_ST1_R`[src]

Bit 0

`impl R<u32, Reg<u32, __0INT_ENA1>>`[src]

`pub fn slc0_rx_quick_eof_int_ena1(&self) -> SLC0_RX_QUICK_EOF_INT_ENA1_R`[src]

Bit 26

`pub fn cmd_dtc_int_ena1(&self) -> CMD_DTC_INT_ENA1_R`[src]

Bit 25

`pub fn slc0_tx_err_eof_int_ena1(&self) -> SLC0_TX_ERR_EOF_INT_ENA1_R`[src]

Bit 24

`pub fn slc0_wr_retry_done_int_ena1(&self) -> SLC0_WR_RETRY_DONE_INT_ENA1_R`[src]

Bit 23

`pub fn slc0_host_rd_ack_int_ena1(&self) -> SLC0_HOST_RD_ACK_INT_ENA1_R`[src]

Bit 22

`pub fn slc0_tx_dscr_empty_int_ena1(&self) -> SLC0_TX_DSCR_EMPTY_INT_ENA1_R`[src]

Bit 21

`pub fn slc0_rx_dscr_err_int_ena1(&self) -> SLC0_RX_DSCR_ERR_INT_ENA1_R`[src]

Bit 20

`pub fn slc0_tx_dscr_err_int_ena1(&self) -> SLC0_TX_DSCR_ERR_INT_ENA1_R`[src]

Bit 19

`pub fn slc0_tohost_int_ena1(&self) -> SLC0_TOHOST_INT_ENA1_R`[src]

Bit 18

`pub fn slc0_rx_eof_int_ena1(&self) -> SLC0_RX_EOF_INT_ENA1_R`[src]

Bit 17

`pub fn slc0_rx_done_int_ena1(&self) -> SLC0_RX_DONE_INT_ENA1_R`[src]

Bit 16

`pub fn slc0_tx_suc_eof_int_ena1(&self) -> SLC0_TX_SUC_EOF_INT_ENA1_R`[src]

Bit 15

`pub fn slc0_tx_done_int_ena1(&self) -> SLC0_TX_DONE_INT_ENA1_R`[src]

Bit 14

`pub fn slc0_token1_1to0_int_ena1(&self) -> SLC0_TOKEN1_1TO0_INT_ENA1_R`[src]

Bit 13

`pub fn slc0_token0_1to0_int_ena1(&self) -> SLC0_TOKEN0_1TO0_INT_ENA1_R`[src]

Bit 12

`pub fn slc0_tx_ovf_int_ena1(&self) -> SLC0_TX_OVF_INT_ENA1_R`[src]

Bit 11

`pub fn slc0_rx_udf_int_ena1(&self) -> SLC0_RX_UDF_INT_ENA1_R`[src]

Bit 10

`pub fn slc0_tx_start_int_ena1(&self) -> SLC0_TX_START_INT_ENA1_R`[src]

Bit 9

`pub fn slc0_rx_start_int_ena1(&self) -> SLC0_RX_START_INT_ENA1_R`[src]

Bit 8

`pub fn frhost_bit7_int_ena1(&self) -> FRHOST_BIT7_INT_ENA1_R`[src]

Bit 7

`pub fn frhost_bit6_int_ena1(&self) -> FRHOST_BIT6_INT_ENA1_R`[src]

Bit 6

`pub fn frhost_bit5_int_ena1(&self) -> FRHOST_BIT5_INT_ENA1_R`[src]

Bit 5

`pub fn frhost_bit4_int_ena1(&self) -> FRHOST_BIT4_INT_ENA1_R`[src]

Bit 4

`pub fn frhost_bit3_int_ena1(&self) -> FRHOST_BIT3_INT_ENA1_R`[src]

Bit 3

`pub fn frhost_bit2_int_ena1(&self) -> FRHOST_BIT2_INT_ENA1_R`[src]

Bit 2

`pub fn frhost_bit1_int_ena1(&self) -> FRHOST_BIT1_INT_ENA1_R`[src]

Bit 1

`pub fn frhost_bit0_int_ena1(&self) -> FRHOST_BIT0_INT_ENA1_R`[src]

Bit 0

`impl R<u32, Reg<u32, __1INT_ST1>>`[src]

`pub fn slc1_tx_err_eof_int_st1(&self) -> SLC1_TX_ERR_EOF_INT_ST1_R`[src]

Bit 24

`pub fn slc1_wr_retry_done_int_st1(&self) -> SLC1_WR_RETRY_DONE_INT_ST1_R`[src]

Bit 23

`pub fn slc1_host_rd_ack_int_st1(&self) -> SLC1_HOST_RD_ACK_INT_ST1_R`[src]

Bit 22

`pub fn slc1_tx_dscr_empty_int_st1(&self) -> SLC1_TX_DSCR_EMPTY_INT_ST1_R`[src]

Bit 21

`pub fn slc1_rx_dscr_err_int_st1(&self) -> SLC1_RX_DSCR_ERR_INT_ST1_R`[src]

Bit 20

`pub fn slc1_tx_dscr_err_int_st1(&self) -> SLC1_TX_DSCR_ERR_INT_ST1_R`[src]

Bit 19

`pub fn slc1_tohost_int_st1(&self) -> SLC1_TOHOST_INT_ST1_R`[src]

Bit 18

`pub fn slc1_rx_eof_int_st1(&self) -> SLC1_RX_EOF_INT_ST1_R`[src]

Bit 17

`pub fn slc1_rx_done_int_st1(&self) -> SLC1_RX_DONE_INT_ST1_R`[src]

Bit 16

`pub fn slc1_tx_suc_eof_int_st1(&self) -> SLC1_TX_SUC_EOF_INT_ST1_R`[src]

Bit 15

`pub fn slc1_tx_done_int_st1(&self) -> SLC1_TX_DONE_INT_ST1_R`[src]

Bit 14

`pub fn slc1_token1_1to0_int_st1(&self) -> SLC1_TOKEN1_1TO0_INT_ST1_R`[src]

Bit 13

`pub fn slc1_token0_1to0_int_st1(&self) -> SLC1_TOKEN0_1TO0_INT_ST1_R`[src]

Bit 12

`pub fn slc1_tx_ovf_int_st1(&self) -> SLC1_TX_OVF_INT_ST1_R`[src]

Bit 11

`pub fn slc1_rx_udf_int_st1(&self) -> SLC1_RX_UDF_INT_ST1_R`[src]

Bit 10

`pub fn slc1_tx_start_int_st1(&self) -> SLC1_TX_START_INT_ST1_R`[src]

Bit 9

`pub fn slc1_rx_start_int_st1(&self) -> SLC1_RX_START_INT_ST1_R`[src]

Bit 8

`pub fn frhost_bit15_int_st1(&self) -> FRHOST_BIT15_INT_ST1_R`[src]

Bit 7

`pub fn frhost_bit14_int_st1(&self) -> FRHOST_BIT14_INT_ST1_R`[src]

Bit 6

`pub fn frhost_bit13_int_st1(&self) -> FRHOST_BIT13_INT_ST1_R`[src]

Bit 5

`pub fn frhost_bit12_int_st1(&self) -> FRHOST_BIT12_INT_ST1_R`[src]

Bit 4

`pub fn frhost_bit11_int_st1(&self) -> FRHOST_BIT11_INT_ST1_R`[src]

Bit 3

`pub fn frhost_bit10_int_st1(&self) -> FRHOST_BIT10_INT_ST1_R`[src]

Bit 2

`pub fn frhost_bit9_int_st1(&self) -> FRHOST_BIT9_INT_ST1_R`[src]

Bit 1

`pub fn frhost_bit8_int_st1(&self) -> FRHOST_BIT8_INT_ST1_R`[src]

Bit 0

`impl R<u32, Reg<u32, __1INT_ENA1>>`[src]

`pub fn slc1_tx_err_eof_int_ena1(&self) -> SLC1_TX_ERR_EOF_INT_ENA1_R`[src]

Bit 24

`pub fn slc1_wr_retry_done_int_ena1(&self) -> SLC1_WR_RETRY_DONE_INT_ENA1_R`[src]

Bit 23

`pub fn slc1_host_rd_ack_int_ena1(&self) -> SLC1_HOST_RD_ACK_INT_ENA1_R`[src]

Bit 22

`pub fn slc1_tx_dscr_empty_int_ena1(&self) -> SLC1_TX_DSCR_EMPTY_INT_ENA1_R`[src]

Bit 21

`pub fn slc1_rx_dscr_err_int_ena1(&self) -> SLC1_RX_DSCR_ERR_INT_ENA1_R`[src]

Bit 20

`pub fn slc1_tx_dscr_err_int_ena1(&self) -> SLC1_TX_DSCR_ERR_INT_ENA1_R`[src]

Bit 19

`pub fn slc1_tohost_int_ena1(&self) -> SLC1_TOHOST_INT_ENA1_R`[src]

Bit 18

`pub fn slc1_rx_eof_int_ena1(&self) -> SLC1_RX_EOF_INT_ENA1_R`[src]

Bit 17

`pub fn slc1_rx_done_int_ena1(&self) -> SLC1_RX_DONE_INT_ENA1_R`[src]

Bit 16

`pub fn slc1_tx_suc_eof_int_ena1(&self) -> SLC1_TX_SUC_EOF_INT_ENA1_R`[src]

Bit 15

`pub fn slc1_tx_done_int_ena1(&self) -> SLC1_TX_DONE_INT_ENA1_R`[src]

Bit 14

`pub fn slc1_token1_1to0_int_ena1(&self) -> SLC1_TOKEN1_1TO0_INT_ENA1_R`[src]

Bit 13

`pub fn slc1_token0_1to0_int_ena1(&self) -> SLC1_TOKEN0_1TO0_INT_ENA1_R`[src]

Bit 12

`pub fn slc1_tx_ovf_int_ena1(&self) -> SLC1_TX_OVF_INT_ENA1_R`[src]

Bit 11

`pub fn slc1_rx_udf_int_ena1(&self) -> SLC1_RX_UDF_INT_ENA1_R`[src]

Bit 10

`pub fn slc1_tx_start_int_ena1(&self) -> SLC1_TX_START_INT_ENA1_R`[src]

Bit 9

`pub fn slc1_rx_start_int_ena1(&self) -> SLC1_RX_START_INT_ENA1_R`[src]

Bit 8

`pub fn frhost_bit15_int_ena1(&self) -> FRHOST_BIT15_INT_ENA1_R`[src]

Bit 7

`pub fn frhost_bit14_int_ena1(&self) -> FRHOST_BIT14_INT_ENA1_R`[src]

Bit 6

`pub fn frhost_bit13_int_ena1(&self) -> FRHOST_BIT13_INT_ENA1_R`[src]

Bit 5

`pub fn frhost_bit12_int_ena1(&self) -> FRHOST_BIT12_INT_ENA1_R`[src]

Bit 4

`pub fn frhost_bit11_int_ena1(&self) -> FRHOST_BIT11_INT_ENA1_R`[src]

Bit 3

`pub fn frhost_bit10_int_ena1(&self) -> FRHOST_BIT10_INT_ENA1_R`[src]

Bit 2

`pub fn frhost_bit9_int_ena1(&self) -> FRHOST_BIT9_INT_ENA1_R`[src]

Bit 1

`pub fn frhost_bit8_int_ena1(&self) -> FRHOST_BIT8_INT_ENA1_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DATE>>`[src]

`pub fn date(&self) -> DATE_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _ID>>`[src]

`pub fn id(&self) -> ID_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _OPTIONS0>>`[src]

`pub fn sw_sys_rst(&self) -> SW_SYS_RST_R`[src]

Bit 31

`pub fn dg_wrap_force_norst(&self) -> DG_WRAP_FORCE_NORST_R`[src]

Bit 30

`pub fn dg_wrap_force_rst(&self) -> DG_WRAP_FORCE_RST_R`[src]

Bit 29

`pub fn analog_force_noiso(&self) -> ANALOG_FORCE_NOISO_R`[src]

Bit 28

`pub fn pll_force_noiso(&self) -> PLL_FORCE_NOISO_R`[src]

Bit 27

`pub fn xtl_force_noiso(&self) -> XTL_FORCE_NOISO_R`[src]

Bit 26

`pub fn analog_force_iso(&self) -> ANALOG_FORCE_ISO_R`[src]

Bit 25

`pub fn pll_force_iso(&self) -> PLL_FORCE_ISO_R`[src]

Bit 24

`pub fn xtl_force_iso(&self) -> XTL_FORCE_ISO_R`[src]

Bit 23

`pub fn bias_core_force_pu(&self) -> BIAS_CORE_FORCE_PU_R`[src]

Bit 22

`pub fn bias_core_force_pd(&self) -> BIAS_CORE_FORCE_PD_R`[src]

Bit 21

`pub fn bias_core_folw_8m(&self) -> BIAS_CORE_FOLW_8M_R`[src]

Bit 20

`pub fn bias_i2c_force_pu(&self) -> BIAS_I2C_FORCE_PU_R`[src]

Bit 19

`pub fn bias_i2c_force_pd(&self) -> BIAS_I2C_FORCE_PD_R`[src]

Bit 18

`pub fn bias_i2c_folw_8m(&self) -> BIAS_I2C_FOLW_8M_R`[src]

Bit 17

`pub fn bias_force_nosleep(&self) -> BIAS_FORCE_NOSLEEP_R`[src]

Bit 16

`pub fn bias_force_sleep(&self) -> BIAS_FORCE_SLEEP_R`[src]

Bit 15

`pub fn bias_sleep_folw_8m(&self) -> BIAS_SLEEP_FOLW_8M_R`[src]

Bit 14

`pub fn xtl_force_pu(&self) -> XTL_FORCE_PU_R`[src]

Bit 13

`pub fn xtl_force_pd(&self) -> XTL_FORCE_PD_R`[src]

Bit 12

`pub fn bbpll_force_pu(&self) -> BBPLL_FORCE_PU_R`[src]

Bit 11

`pub fn bbpll_force_pd(&self) -> BBPLL_FORCE_PD_R`[src]

Bit 10

`pub fn bbpll_i2c_force_pu(&self) -> BBPLL_I2C_FORCE_PU_R`[src]

Bit 9

`pub fn bbpll_i2c_force_pd(&self) -> BBPLL_I2C_FORCE_PD_R`[src]

Bit 8

`pub fn bb_i2c_force_pu(&self) -> BB_I2C_FORCE_PU_R`[src]

Bit 7

`pub fn bb_i2c_force_pd(&self) -> BB_I2C_FORCE_PD_R`[src]

Bit 6

`pub fn sw_procpu_rst(&self) -> SW_PROCPU_RST_R`[src]

Bit 5

`pub fn sw_appcpu_rst(&self) -> SW_APPCPU_RST_R`[src]

Bit 4

`pub fn sw_stall_procpu_c0(&self) -> SW_STALL_PROCPU_C0_R`[src]

Bits 2:3

`pub fn sw_stall_appcpu_c0(&self) -> SW_STALL_APPCPU_C0_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _SLP_TIMER0>>`[src]

`pub fn slp_val_lo(&self) -> SLP_VAL_LO_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _SLP_TIMER1>>`[src]

`pub fn main_timer_alarm_en(&self) -> MAIN_TIMER_ALARM_EN_R`[src]

Bit 16

`pub fn slp_val_hi(&self) -> SLP_VAL_HI_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _TIME_UPDATE>>`[src]

`pub fn time_update(&self) -> TIME_UPDATE_R`[src]

Bit 31

`pub fn time_valid(&self) -> TIME_VALID_R`[src]

Bit 30

`impl R<u32, Reg<u32, _TIME0>>`[src]

`pub fn time_lo(&self) -> TIME_LO_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _TIME1>>`[src]

`pub fn time_hi(&self) -> TIME_HI_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _STATE0>>`[src]

`pub fn sleep_en(&self) -> SLEEP_EN_R`[src]

Bit 31

`pub fn slp_reject(&self) -> SLP_REJECT_R`[src]

Bit 30

`pub fn slp_wakeup(&self) -> SLP_WAKEUP_R`[src]

Bit 29

`pub fn sdio_active_ind(&self) -> SDIO_ACTIVE_IND_R`[src]

Bit 28

`pub fn ulp_cp_slp_timer_en(&self) -> ULP_CP_SLP_TIMER_EN_R`[src]

Bit 24

`pub fn touch_slp_timer_en(&self) -> TOUCH_SLP_TIMER_EN_R`[src]

Bit 23

`pub fn apb2rtc_bridge_sel(&self) -> APB2RTC_BRIDGE_SEL_R`[src]

Bit 22

`pub fn ulp_cp_wakeup_force_en(&self) -> ULP_CP_WAKEUP_FORCE_EN_R`[src]

Bit 21

`pub fn touch_wakeup_force_en(&self) -> TOUCH_WAKEUP_FORCE_EN_R`[src]

Bit 20

`impl R<u32, Reg<u32, _TIMER1>>`[src]

`pub fn pll_buf_wait(&self) -> PLL_BUF_WAIT_R`[src]

Bits 24:31

`pub fn xtl_buf_wait(&self) -> XTL_BUF_WAIT_R`[src]

Bits 14:23

`pub fn ck8m_wait(&self) -> CK8M_WAIT_R`[src]

Bits 6:13

`pub fn cpu_stall_wait(&self) -> CPU_STALL_WAIT_R`[src]

Bits 1:5

`pub fn cpu_stall_en(&self) -> CPU_STALL_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _TIMER2>>`[src]

`pub fn min_time_ck8m_off(&self) -> MIN_TIME_CK8M_OFF_R`[src]

Bits 24:31

`pub fn ulpcp_touch_start_wait(&self) -> ULPCP_TOUCH_START_WAIT_R`[src]

Bits 15:23

`impl R<u32, Reg<u32, _TIMER3>>`[src]

`pub fn rom_ram_powerup_timer(&self) -> ROM_RAM_POWERUP_TIMER_R`[src]

Bits 25:31

`pub fn rom_ram_wait_timer(&self) -> ROM_RAM_WAIT_TIMER_R`[src]

Bits 16:24

`pub fn wifi_powerup_timer(&self) -> WIFI_POWERUP_TIMER_R`[src]

Bits 9:15

`pub fn wifi_wait_timer(&self) -> WIFI_WAIT_TIMER_R`[src]

Bits 0:8

`impl R<u32, Reg<u32, _TIMER4>>`[src]

`pub fn dg_wrap_powerup_timer(&self) -> DG_WRAP_POWERUP_TIMER_R`[src]

Bits 25:31

`pub fn dg_wrap_wait_timer(&self) -> DG_WRAP_WAIT_TIMER_R`[src]

Bits 16:24

`pub fn powerup_timer(&self) -> POWERUP_TIMER_R`[src]

Bits 9:15

`pub fn wait_timer(&self) -> WAIT_TIMER_R`[src]

Bits 0:8

`impl R<u32, Reg<u32, _TIMER5>>`[src]

`pub fn rtcmem_powerup_timer(&self) -> RTCMEM_POWERUP_TIMER_R`[src]

Bits 25:31

`pub fn rtcmem_wait_timer(&self) -> RTCMEM_WAIT_TIMER_R`[src]

Bits 16:24

`pub fn min_slp_val(&self) -> MIN_SLP_VAL_R`[src]

Bits 8:15

`pub fn ulp_cp_subtimer_prediv(&self) -> ULP_CP_SUBTIMER_PREDIV_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _ANA_CONF>>`[src]

`pub fn pll_i2c_pu(&self) -> PLL_I2C_PU_R`[src]

Bit 31

`pub fn ckgen_i2c_pu(&self) -> CKGEN_I2C_PU_R`[src]

Bit 30

`pub fn rfrx_pbus_pu(&self) -> RFRX_PBUS_PU_R`[src]

Bit 28

`pub fn txrf_i2c_pu(&self) -> TXRF_I2C_PU_R`[src]

Bit 27

`pub fn pvtmon_pu(&self) -> PVTMON_PU_R`[src]

Bit 26

`pub fn bbpll_cal_slp_start(&self) -> BBPLL_CAL_SLP_START_R`[src]

Bit 25

`pub fn plla_force_pu(&self) -> PLLA_FORCE_PU_R`[src]

Bit 24

`pub fn plla_force_pd(&self) -> PLLA_FORCE_PD_R`[src]

Bit 23

`impl R<u32, Reg<u32, _RESET_STATE>>`[src]

`pub fn procpu_stat_vector_sel(&self) -> PROCPU_STAT_VECTOR_SEL_R`[src]

Bit 13

`pub fn appcpu_stat_vector_sel(&self) -> APPCPU_STAT_VECTOR_SEL_R`[src]

Bit 12

`pub fn reset_cause_appcpu(&self) -> RESET_CAUSE_APPCPU_R`[src]

Bits 6:11

`pub fn reset_cause_procpu(&self) -> RESET_CAUSE_PROCPU_R`[src]

Bits 0:5

`impl R<u32, Reg<u32, _WAKEUP_STATE>>`[src]

`pub fn gpio_wakeup_filter(&self) -> GPIO_WAKEUP_FILTER_R`[src]

Bit 22

`pub fn wakeup_ena(&self) -> WAKEUP_ENA_R`[src]

Bits 11:21

`pub fn wakeup_cause(&self) -> WAKEUP_CAUSE_R`[src]

Bits 0:10

`impl R<u32, Reg<u32, _INT_ENA>>`[src]

`pub fn main_timer_int_ena(&self) -> MAIN_TIMER_INT_ENA_R`[src]

Bit 8

`pub fn brown_out_int_ena(&self) -> BROWN_OUT_INT_ENA_R`[src]

Bit 7

`pub fn touch_int_ena(&self) -> TOUCH_INT_ENA_R`[src]

Bit 6

`pub fn ulp_cp_int_ena(&self) -> ULP_CP_INT_ENA_R`[src]

Bit 5

`pub fn time_valid_int_ena(&self) -> TIME_VALID_INT_ENA_R`[src]

Bit 4

`pub fn wdt_int_ena(&self) -> WDT_INT_ENA_R`[src]

Bit 3

`pub fn sdio_idle_int_ena(&self) -> SDIO_IDLE_INT_ENA_R`[src]

Bit 2

`pub fn slp_reject_int_ena(&self) -> SLP_REJECT_INT_ENA_R`[src]

Bit 1

`pub fn slp_wakeup_int_ena(&self) -> SLP_WAKEUP_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_RAW>>`[src]

`pub fn main_timer_int_raw(&self) -> MAIN_TIMER_INT_RAW_R`[src]

Bit 8

`pub fn brown_out_int_raw(&self) -> BROWN_OUT_INT_RAW_R`[src]

Bit 7

`pub fn touch_int_raw(&self) -> TOUCH_INT_RAW_R`[src]

Bit 6

`pub fn ulp_cp_int_raw(&self) -> ULP_CP_INT_RAW_R`[src]

Bit 5

`pub fn time_valid_int_raw(&self) -> TIME_VALID_INT_RAW_R`[src]

Bit 4

`pub fn wdt_int_raw(&self) -> WDT_INT_RAW_R`[src]

Bit 3

`pub fn sdio_idle_int_raw(&self) -> SDIO_IDLE_INT_RAW_R`[src]

Bit 2

`pub fn slp_reject_int_raw(&self) -> SLP_REJECT_INT_RAW_R`[src]

Bit 1

`pub fn slp_wakeup_int_raw(&self) -> SLP_WAKEUP_INT_RAW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_ST>>`[src]

`pub fn main_timer_int_st(&self) -> MAIN_TIMER_INT_ST_R`[src]

Bit 8

`pub fn brown_out_int_st(&self) -> BROWN_OUT_INT_ST_R`[src]

Bit 7

`pub fn touch_int_st(&self) -> TOUCH_INT_ST_R`[src]

Bit 6

`pub fn sar_int_st(&self) -> SAR_INT_ST_R`[src]

Bit 5

`pub fn time_valid_int_st(&self) -> TIME_VALID_INT_ST_R`[src]

Bit 4

`pub fn wdt_int_st(&self) -> WDT_INT_ST_R`[src]

Bit 3

`pub fn sdio_idle_int_st(&self) -> SDIO_IDLE_INT_ST_R`[src]

Bit 2

`pub fn slp_reject_int_st(&self) -> SLP_REJECT_INT_ST_R`[src]

Bit 1

`pub fn slp_wakeup_int_st(&self) -> SLP_WAKEUP_INT_ST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_CLR>>`[src]

`pub fn main_timer_int_clr(&self) -> MAIN_TIMER_INT_CLR_R`[src]

Bit 8

`pub fn brown_out_int_clr(&self) -> BROWN_OUT_INT_CLR_R`[src]

Bit 7

`pub fn touch_int_clr(&self) -> TOUCH_INT_CLR_R`[src]

Bit 6

`pub fn sar_int_clr(&self) -> SAR_INT_CLR_R`[src]

Bit 5

`pub fn time_valid_int_clr(&self) -> TIME_VALID_INT_CLR_R`[src]

Bit 4

`pub fn wdt_int_clr(&self) -> WDT_INT_CLR_R`[src]

Bit 3

`pub fn sdio_idle_int_clr(&self) -> SDIO_IDLE_INT_CLR_R`[src]

Bit 2

`pub fn slp_reject_int_clr(&self) -> SLP_REJECT_INT_CLR_R`[src]

Bit 1

`pub fn slp_wakeup_int_clr(&self) -> SLP_WAKEUP_INT_CLR_R`[src]

`impl R<u32, Reg<u32, _EXT_WAKEUP_CONF>>`[src]

`pub fn ext_wakeup1_lv(&self) -> EXT_WAKEUP1_LV_R`[src]

Bit 31

`pub fn ext_wakeup0_lv(&self) -> EXT_WAKEUP0_LV_R`[src]

Bit 30

`impl R<u32, Reg<u32, _SLP_REJECT_CONF>>`[src]

`pub fn reject_cause(&self) -> REJECT_CAUSE_R`[src]

Bits 28:31

`pub fn deep_slp_reject_en(&self) -> DEEP_SLP_REJECT_EN_R`[src]

Bit 27

`pub fn light_slp_reject_en(&self) -> LIGHT_SLP_REJECT_EN_R`[src]

Bit 26

`pub fn sdio_reject_en(&self) -> SDIO_REJECT_EN_R`[src]

Bit 25

`pub fn gpio_reject_en(&self) -> GPIO_REJECT_EN_R`[src]

Bit 24

`impl R<u32, Reg<u32, _CPU_PERIOD_CONF>>`[src]

`pub fn cpuperiod_sel(&self) -> CPUPERIOD_SEL_R`[src]

Bits 30:31

`pub fn cpusel_conf(&self) -> CPUSEL_CONF_R`[src]

Bit 29

`impl R<u32, Reg<u32, _SDIO_ACT_CONF>>`[src]

`pub fn sdio_act_dnum(&self) -> SDIO_ACT_DNUM_R`[src]

Bits 22:31

`impl R<u8, ANA_CLK_RTC_SEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, ANA_CLK_RTC_SEL_A>`[src]

`pub fn is_div128(&self) -> bool`[src]

Checks if the value of the field is DIV128

`pub fn is_div256(&self) -> bool`[src]

Checks if the value of the field is DIV256

`pub fn is_div512(&self) -> bool`[src]

Checks if the value of the field is DIV512

`pub fn is_div1024(&self) -> bool`[src]

Checks if the value of the field is DIV1024

`impl R<u32, Reg<u32, _CLK_CONF>>`[src]

`pub fn ana_clk_rtc_sel(&self) -> ANA_CLK_RTC_SEL_R`[src]

Bits 30:31

`pub fn fast_clk_rtc_sel(&self) -> FAST_CLK_RTC_SEL_R`[src]

Bit 29

`pub fn soc_clk_sel(&self) -> SOC_CLK_SEL_R`[src]

Bits 27:28

`pub fn ck8m_force_pu(&self) -> CK8M_FORCE_PU_R`[src]

Bit 26

`pub fn ck8m_force_pd(&self) -> CK8M_FORCE_PD_R`[src]

Bit 25

`pub fn ck8m_dfreq(&self) -> CK8M_DFREQ_R`[src]

Bits 17:24

`pub fn ck8m_force_nogating(&self) -> CK8M_FORCE_NOGATING_R`[src]

Bit 16

`pub fn xtal_force_nogating(&self) -> XTAL_FORCE_NOGATING_R`[src]

Bit 15

`pub fn ck8m_div_sel(&self) -> CK8M_DIV_SEL_R`[src]

Bits 12:14

`pub fn ck8m_dfreq_force(&self) -> CK8M_DFREQ_FORCE_R`[src]

Bit 11

`pub fn dig_clk8m_en(&self) -> DIG_CLK8M_EN_R`[src]

Bit 10

`pub fn dig_clk8m_d256_en(&self) -> DIG_CLK8M_D256_EN_R`[src]

Bit 9

`pub fn dig_xtal32k_en(&self) -> DIG_XTAL32K_EN_R`[src]

Bit 8

`pub fn enb_ck8m_div(&self) -> ENB_CK8M_DIV_R`[src]

Bit 7

`pub fn enb_ck8m(&self) -> ENB_CK8M_R`[src]

Bit 6

`pub fn ck8m_div(&self) -> CK8M_DIV_R`[src]

Bits 4:5

`impl R<u32, Reg<u32, _SDIO_CONF>>`[src]

`pub fn xpd_sdio_reg(&self) -> XPD_SDIO_REG_R`[src]

Bit 31

`pub fn drefh_sdio(&self) -> DREFH_SDIO_R`[src]

Bits 29:30

`pub fn drefm_sdio(&self) -> DREFM_SDIO_R`[src]

Bits 27:28

`pub fn drefl_sdio(&self) -> DREFL_SDIO_R`[src]

Bits 25:26

`pub fn reg1p8_ready(&self) -> REG1P8_READY_R`[src]

Bit 24

`pub fn sdio_tieh(&self) -> SDIO_TIEH_R`[src]

Bit 23

`pub fn sdio_force(&self) -> SDIO_FORCE_R`[src]

Bit 22

`pub fn sdio_pd_en(&self) -> SDIO_PD_EN_R`[src]

Bit 21

`impl R<u32, Reg<u32, _BIAS_CONF>>`[src]

`pub fn rst_bias_i2c(&self) -> RST_BIAS_I2C_R`[src]

Bit 31

`pub fn dec_heartbeat_width(&self) -> DEC_HEARTBEAT_WIDTH_R`[src]

Bit 30

`pub fn inc_heartbeat_period(&self) -> INC_HEARTBEAT_PERIOD_R`[src]

Bit 29

`pub fn dec_heartbeat_period(&self) -> DEC_HEARTBEAT_PERIOD_R`[src]

Bit 28

`pub fn inc_heartbeat_refresh(&self) -> INC_HEARTBEAT_REFRESH_R`[src]

Bit 27

`pub fn enb_sck_xtal(&self) -> ENB_SCK_XTAL_R`[src]

Bit 26

`pub fn dbg_atten(&self) -> DBG_ATTEN_R`[src]

Bits 24:25

`pub fn force_pu(&self) -> FORCE_PU_R`[src]

Bit 31

`pub fn force_pd(&self) -> FORCE_PD_R`[src]

Bit 30

`pub fn dboost_force_pu(&self) -> DBOOST_FORCE_PU_R`[src]

Bit 29

`pub fn dboost_force_pd(&self) -> DBOOST_FORCE_PD_R`[src]

Bit 28

`pub fn dbias_wak(&self) -> DBIAS_WAK_R`[src]

Bits 25:27

`pub fn dbias_slp(&self) -> DBIAS_SLP_R`[src]

Bits 22:24

`pub fn sck_dcap(&self) -> SCK_DCAP_R`[src]

Bits 14:21

`pub fn dig_dbias_wak(&self) -> DIG_DBIAS_WAK_R`[src]

Bits 11:13

`pub fn dig_dbias_slp(&self) -> DIG_DBIAS_SLP_R`[src]

Bits 8:10

`pub fn sck_dcap_force(&self) -> SCK_DCAP_FORCE_R`[src]

Bit 7

`impl R<u32, Reg<u32, _PWC>>`[src]

`pub fn pd_en(&self) -> PD_EN_R`[src]

Bit 20

`pub fn force_pu(&self) -> FORCE_PU_R`[src]

Bit 19

`pub fn force_pd(&self) -> FORCE_PD_R`[src]

Bit 18

`pub fn slowmem_pd_en(&self) -> SLOWMEM_PD_EN_R`[src]

Bit 17

`pub fn slowmem_force_pu(&self) -> SLOWMEM_FORCE_PU_R`[src]

Bit 16

`pub fn slowmem_force_pd(&self) -> SLOWMEM_FORCE_PD_R`[src]

Bit 15

`pub fn fastmem_pd_en(&self) -> FASTMEM_PD_EN_R`[src]

Bit 14

`pub fn fastmem_force_pu(&self) -> FASTMEM_FORCE_PU_R`[src]

Bit 13

`pub fn fastmem_force_pd(&self) -> FASTMEM_FORCE_PD_R`[src]

Bit 12

`pub fn slowmem_force_lpu(&self) -> SLOWMEM_FORCE_LPU_R`[src]

Bit 11

`pub fn slowmem_force_lpd(&self) -> SLOWMEM_FORCE_LPD_R`[src]

Bit 10

`pub fn slowmem_folw_cpu(&self) -> SLOWMEM_FOLW_CPU_R`[src]

Bit 9

`pub fn fastmem_force_lpu(&self) -> FASTMEM_FORCE_LPU_R`[src]

Bit 8

`pub fn fastmem_force_lpd(&self) -> FASTMEM_FORCE_LPD_R`[src]

Bit 7

`pub fn fastmem_folw_cpu(&self) -> FASTMEM_FOLW_CPU_R`[src]

Bit 6

`pub fn force_noiso(&self) -> FORCE_NOISO_R`[src]

Bit 5

`pub fn force_iso(&self) -> FORCE_ISO_R`[src]

Bit 4

`pub fn slowmem_force_iso(&self) -> SLOWMEM_FORCE_ISO_R`[src]

Bit 3

`pub fn slowmem_force_noiso(&self) -> SLOWMEM_FORCE_NOISO_R`[src]

Bit 2

`pub fn fastmem_force_iso(&self) -> FASTMEM_FORCE_ISO_R`[src]

Bit 1

`pub fn fastmem_force_noiso(&self) -> FASTMEM_FORCE_NOISO_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DIG_PWC>>`[src]

`pub fn dg_wrap_pd_en(&self) -> DG_WRAP_PD_EN_R`[src]

Bit 31

`pub fn wifi_pd_en(&self) -> WIFI_PD_EN_R`[src]

Bit 30

`pub fn inter_ram4_pd_en(&self) -> INTER_RAM4_PD_EN_R`[src]

Bit 29

`pub fn inter_ram3_pd_en(&self) -> INTER_RAM3_PD_EN_R`[src]

Bit 28

`pub fn inter_ram2_pd_en(&self) -> INTER_RAM2_PD_EN_R`[src]

Bit 27

`pub fn inter_ram1_pd_en(&self) -> INTER_RAM1_PD_EN_R`[src]

Bit 26

`pub fn inter_ram0_pd_en(&self) -> INTER_RAM0_PD_EN_R`[src]

Bit 25

`pub fn rom0_pd_en(&self) -> ROM0_PD_EN_R`[src]

Bit 24

`pub fn dg_wrap_force_pu(&self) -> DG_WRAP_FORCE_PU_R`[src]

Bit 20

`pub fn dg_wrap_force_pd(&self) -> DG_WRAP_FORCE_PD_R`[src]

Bit 19

`pub fn wifi_force_pu(&self) -> WIFI_FORCE_PU_R`[src]

Bit 18

`pub fn wifi_force_pd(&self) -> WIFI_FORCE_PD_R`[src]

Bit 17

`pub fn inter_ram4_force_pu(&self) -> INTER_RAM4_FORCE_PU_R`[src]

Bit 16

`pub fn inter_ram4_force_pd(&self) -> INTER_RAM4_FORCE_PD_R`[src]

Bit 15

`pub fn inter_ram3_force_pu(&self) -> INTER_RAM3_FORCE_PU_R`[src]

Bit 14

`pub fn inter_ram3_force_pd(&self) -> INTER_RAM3_FORCE_PD_R`[src]

Bit 13

`pub fn inter_ram2_force_pu(&self) -> INTER_RAM2_FORCE_PU_R`[src]

Bit 12

`pub fn inter_ram2_force_pd(&self) -> INTER_RAM2_FORCE_PD_R`[src]

Bit 11

`pub fn inter_ram1_force_pu(&self) -> INTER_RAM1_FORCE_PU_R`[src]

Bit 10

`pub fn inter_ram1_force_pd(&self) -> INTER_RAM1_FORCE_PD_R`[src]

Bit 9

`pub fn inter_ram0_force_pu(&self) -> INTER_RAM0_FORCE_PU_R`[src]

Bit 8

`pub fn inter_ram0_force_pd(&self) -> INTER_RAM0_FORCE_PD_R`[src]

Bit 7

`pub fn rom0_force_pu(&self) -> ROM0_FORCE_PU_R`[src]

Bit 6

`pub fn rom0_force_pd(&self) -> ROM0_FORCE_PD_R`[src]

Bit 5

`pub fn lslp_mem_force_pu(&self) -> LSLP_MEM_FORCE_PU_R`[src]

Bit 4

`pub fn lslp_mem_force_pd(&self) -> LSLP_MEM_FORCE_PD_R`[src]

Bit 3

`impl R<u32, Reg<u32, _DIG_ISO>>`[src]

`pub fn dg_wrap_force_noiso(&self) -> DG_WRAP_FORCE_NOISO_R`[src]

Bit 31

`pub fn dg_wrap_force_iso(&self) -> DG_WRAP_FORCE_ISO_R`[src]

Bit 30

`pub fn wifi_force_noiso(&self) -> WIFI_FORCE_NOISO_R`[src]

Bit 29

`pub fn wifi_force_iso(&self) -> WIFI_FORCE_ISO_R`[src]

Bit 28

`pub fn inter_ram4_force_noiso(&self) -> INTER_RAM4_FORCE_NOISO_R`[src]

Bit 27

`pub fn inter_ram4_force_iso(&self) -> INTER_RAM4_FORCE_ISO_R`[src]

Bit 26

`pub fn inter_ram3_force_noiso(&self) -> INTER_RAM3_FORCE_NOISO_R`[src]

Bit 25

`pub fn inter_ram3_force_iso(&self) -> INTER_RAM3_FORCE_ISO_R`[src]

Bit 24

`pub fn inter_ram2_force_noiso(&self) -> INTER_RAM2_FORCE_NOISO_R`[src]

Bit 23

`pub fn inter_ram2_force_iso(&self) -> INTER_RAM2_FORCE_ISO_R`[src]

Bit 22

`pub fn inter_ram1_force_noiso(&self) -> INTER_RAM1_FORCE_NOISO_R`[src]

Bit 21

`pub fn inter_ram1_force_iso(&self) -> INTER_RAM1_FORCE_ISO_R`[src]

Bit 20

`pub fn inter_ram0_force_noiso(&self) -> INTER_RAM0_FORCE_NOISO_R`[src]

Bit 19

`pub fn inter_ram0_force_iso(&self) -> INTER_RAM0_FORCE_ISO_R`[src]

Bit 18

`pub fn rom0_force_noiso(&self) -> ROM0_FORCE_NOISO_R`[src]

Bit 17

`pub fn rom0_force_iso(&self) -> ROM0_FORCE_ISO_R`[src]

Bit 16

`pub fn dg_pad_force_hold(&self) -> DG_PAD_FORCE_HOLD_R`[src]

Bit 15

`pub fn dg_pad_force_unhold(&self) -> DG_PAD_FORCE_UNHOLD_R`[src]

Bit 14

`pub fn dg_pad_force_iso(&self) -> DG_PAD_FORCE_ISO_R`[src]

Bit 13

`pub fn dg_pad_force_noiso(&self) -> DG_PAD_FORCE_NOISO_R`[src]

Bit 12

`pub fn dg_pad_autohold_en(&self) -> DG_PAD_AUTOHOLD_EN_R`[src]

Bit 11

`pub fn clr_dg_pad_autohold(&self) -> CLR_DG_PAD_AUTOHOLD_R`[src]

Bit 10

`pub fn dg_pad_autohold(&self) -> DG_PAD_AUTOHOLD_R`[src]

Bit 9

`pub fn dig_iso_force_on(&self) -> DIG_ISO_FORCE_ON_R`[src]

Bit 8

`pub fn dig_iso_force_off(&self) -> DIG_ISO_FORCE_OFF_R`[src]

Bit 7

`impl R<u8, WDT_STG0_A>`[src]

`pub fn variant(&self) -> Variant<u8, WDT_STG0_A>`[src]

Get enumerated values variant

`pub fn is_disable(&self) -> bool`[src]

Checks if the value of the field is DISABLE

`pub fn is_interrupt(&self) -> bool`[src]

Checks if the value of the field is INTERRUPT

`pub fn is_reset_cpu(&self) -> bool`[src]

Checks if the value of the field is RESETCPU

`pub fn is_reset_system(&self) -> bool`[src]

Checks if the value of the field is RESETSYSTEM

`pub fn is_reset_rtc(&self) -> bool`[src]

Checks if the value of the field is RESETRTC

`impl R<u8, WDT_CPU_RESET_LENGTH_A>`[src]

`pub fn variant(&self) -> WDT_CPU_RESET_LENGTH_A`[src]

Get enumerated values variant

`pub fn is_t100ns(&self) -> bool`[src]

Checks if the value of the field is T100NS

`pub fn is_t200ns(&self) -> bool`[src]

Checks if the value of the field is T200NS

`pub fn is_t300ns(&self) -> bool`[src]

Checks if the value of the field is T300NS

`pub fn is_t400ns(&self) -> bool`[src]

Checks if the value of the field is T400NS

`pub fn is_t500ns(&self) -> bool`[src]

Checks if the value of the field is T500NS

`pub fn is_t800ns(&self) -> bool`[src]

Checks if the value of the field is T800NS

`pub fn is_t1600ns(&self) -> bool`[src]

Checks if the value of the field is T1600NS

`pub fn is_t3200ns(&self) -> bool`[src]

Checks if the value of the field is T3200NS

`impl R<u32, Reg<u32, _WDTCONFIG0>>`[src]

`pub fn wdt_en(&self) -> WDT_EN_R`[src]

Bit 31

`pub fn wdt_stg0(&self) -> WDT_STG0_R`[src]

Bits 28:30

`pub fn wdt_stg1(&self) -> WDT_STG1_R`[src]

Bits 25:27

`pub fn wdt_stg2(&self) -> WDT_STG2_R`[src]

Bits 22:24

`pub fn wdt_stg3(&self) -> WDT_STG3_R`[src]

Bits 19:21

`pub fn wdt_edge_int_en(&self) -> WDT_EDGE_INT_EN_R`[src]

Bit 18

`pub fn wdt_level_int_en(&self) -> WDT_LEVEL_INT_EN_R`[src]

Bit 17

`pub fn wdt_cpu_reset_length(&self) -> WDT_CPU_RESET_LENGTH_R`[src]

Bits 14:16

`pub fn wdt_sys_reset_length(&self) -> WDT_SYS_RESET_LENGTH_R`[src]

Bits 11:13

`pub fn wdt_flashboot_mod_en(&self) -> WDT_FLASHBOOT_MOD_EN_R`[src]

Bit 10

`pub fn wdt_procpu_reset_en(&self) -> WDT_PROCPU_RESET_EN_R`[src]

Bit 9

`pub fn wdt_appcpu_reset_en(&self) -> WDT_APPCPU_RESET_EN_R`[src]

`pub fn ent_rtc(&self) -> ENT_RTC_R`[src]

Bit 29

`impl R<u32, Reg<u32, _SW_CPU_STALL>>`[src]

`pub fn sw_stall_procpu_c1(&self) -> SW_STALL_PROCPU_C1_R`[src]

`impl R<u32, Reg<u32, _HOLD_FORCE>>`[src]

`pub fn x32n_hold_force(&self) -> X32N_HOLD_FORCE_R`[src]

Bit 17

`pub fn x32p_hold_force(&self) -> X32P_HOLD_FORCE_R`[src]

Bit 16

`pub fn touch_pad7_hold_force(&self) -> TOUCH_PAD7_HOLD_FORCE_R`[src]

Bit 15

`pub fn touch_pad6_hold_force(&self) -> TOUCH_PAD6_HOLD_FORCE_R`[src]

Bit 14

`pub fn touch_pad5_hold_force(&self) -> TOUCH_PAD5_HOLD_FORCE_R`[src]

Bit 13

`pub fn touch_pad4_hold_force(&self) -> TOUCH_PAD4_HOLD_FORCE_R`[src]

Bit 12

`pub fn touch_pad3_hold_force(&self) -> TOUCH_PAD3_HOLD_FORCE_R`[src]

Bit 11

`pub fn touch_pad2_hold_force(&self) -> TOUCH_PAD2_HOLD_FORCE_R`[src]

Bit 10

`pub fn touch_pad1_hold_force(&self) -> TOUCH_PAD1_HOLD_FORCE_R`[src]

Bit 9

`pub fn touch_pad0_hold_force(&self) -> TOUCH_PAD0_HOLD_FORCE_R`[src]

Bit 8

`pub fn sense4_hold_force(&self) -> SENSE4_HOLD_FORCE_R`[src]

Bit 7

`pub fn sense3_hold_force(&self) -> SENSE3_HOLD_FORCE_R`[src]

Bit 6

`pub fn sense2_hold_force(&self) -> SENSE2_HOLD_FORCE_R`[src]

Bit 5

`pub fn sense1_hold_force(&self) -> SENSE1_HOLD_FORCE_R`[src]

Bit 4

`pub fn pdac2_hold_force(&self) -> PDAC2_HOLD_FORCE_R`[src]

Bit 3

`pub fn pdac1_hold_force(&self) -> PDAC1_HOLD_FORCE_R`[src]

Bit 2

`pub fn adc2_hold_force(&self) -> ADC2_HOLD_FORCE_R`[src]

Bit 1

`pub fn adc1_hold_force(&self) -> ADC1_HOLD_FORCE_R`[src]

Bit 0

`impl R<u32, Reg<u32, _EXT_WAKEUP1>>`[src]

`pub fn ext_wakeup1_status_clr(&self) -> EXT_WAKEUP1_STATUS_CLR_R`[src]

Bit 18

`pub fn ext_wakeup1_sel(&self) -> EXT_WAKEUP1_SEL_R`[src]

Bits 0:17

`impl R<u32, Reg<u32, _EXT_WAKEUP1_STATUS>>`[src]

`pub fn ext_wakeup1_status(&self) -> EXT_WAKEUP1_STATUS_R`[src]

Bits 0:17

`impl R<u32, Reg<u32, _BROWN_OUT>>`[src]

`pub fn brown_out_det(&self) -> BROWN_OUT_DET_R`[src]

Bit 31

`pub fn brown_out_ena(&self) -> BROWN_OUT_ENA_R`[src]

Bit 30

`pub fn dbrown_out_thres(&self) -> DBROWN_OUT_THRES_R`[src]

Bits 27:29

`pub fn brown_out_rst_ena(&self) -> BROWN_OUT_RST_ENA_R`[src]

Bit 26

`pub fn brown_out_rst_wait(&self) -> BROWN_OUT_RST_WAIT_R`[src]

Bits 16:25

`pub fn brown_out_pd_rf_ena(&self) -> BROWN_OUT_PD_RF_ENA_R`[src]

Bit 15

`pub fn brown_out_close_flash_ena(&self) -> BROWN_OUT_CLOSE_FLASH_ENA_R`[src]

Bit 14

`impl R<u32, Reg<u32, _DATE>>`[src]

`pub fn cntl_date(&self) -> CNTL_DATE_R`[src]

Bits 0:27

`impl R<u8, DBIAS_WAK_A>`[src]

`pub fn variant(&self) -> DBIAS_WAK_A`[src]

Get enumerated values variant

`pub fn is_bias_0v90(&self) -> bool`[src]

Checks if the value of the field is BIAS_0V90

`pub fn is_bias_0v95(&self) -> bool`[src]

Checks if the value of the field is BIAS_0V95

`pub fn is_bias_1v00(&self) -> bool`[src]

Checks if the value of the field is BIAS_1V00

`pub fn is_bias_1v05(&self) -> bool`[src]

Checks if the value of the field is BIAS_1V05

`pub fn is_bias_1v10(&self) -> bool`[src]

Checks if the value of the field is BIAS_1V10

`pub fn is_bias_1v15(&self) -> bool`[src]

Checks if the value of the field is BIAS_1V15

`pub fn is_bias_1v20(&self) -> bool`[src]

Checks if the value of the field is BIAS_1V20

`pub fn is_bias_1v25(&self) -> bool`[src]

Checks if the value of the field is BIAS_1V25

`impl R<u32, Reg<u32, _CNTL>>`[src]

`pub fn force_pu(&self) -> FORCE_PU_R`[src]

Bit 31 - Force RTC power up

`pub fn force_pd(&self) -> FORCE_PD_R`[src]

Bit 30 - Force RTC power down (decrease voltage to 0.8V or lower)

`pub fn force_dboost_pu(&self) -> FORCE_DBOOST_PU_R`[src]

Bit 29 - Force DBOOST power up

`pub fn force_dboost_pd(&self) -> FORCE_DBOOST_PD_R`[src]

Bit 28 - Force DBOOST power down

`pub fn dbias_wak(&self) -> DBIAS_WAK_R`[src]

Bits 25:27 - RTC DBIAS during wakeup

`pub fn dbias_slp(&self) -> DBIAS_SLP_R`[src]

Bits 22:24 - RTC DBIAS during sleep

`pub fn sck_dcap(&self) -> SCK_DCAP_R`[src]

Bits 14:21 - 150kHz oscillator tuning

`pub fn dig_dbias_wak(&self) -> DIG_DBIAS_WAK_R`[src]

Bits 11:13 - DBIAS during wakeup

`pub fn dig_dbias_slp(&self) -> DIG_DBIAS_SLP_R`[src]

Bits 8:10 - DBIAS during wakeup

`pub fn sck_dcap_force(&self) -> SCK_DCAP_FORCE_R`[src]

Bit 7 - 150kHz tuning force

`impl R<u32, Reg<u32, _APLL>>`[src]

`pub fn block(&self) -> BLOCK_R`[src]

Bits 0:7 - Block

`pub fn addr(&self) -> ADDR_R`[src]

Bits 8:15 - Address

`pub fn data(&self) -> DATA_R`[src]

Bits 16:23 - Data

`pub fn write(&self) -> WRITE_R`[src]

Bit 24 - Write

`pub fn busy(&self) -> BUSY_R`[src]

Bit 25 - Ready

`impl R<u32, Reg<u32, _PLL>>`[src]

`pub fn block(&self) -> BLOCK_R`[src]

Bits 0:7 - Block

`pub fn addr(&self) -> ADDR_R`[src]

Bits 8:15 - Address

`pub fn data(&self) -> DATA_R`[src]

Bits 16:23 - Data

`pub fn write(&self) -> WRITE_R`[src]

Bit 24 - Write

`pub fn busy(&self) -> BUSY_R`[src]

Bit 25 - Ready

`impl R<u32, Reg<u32, _SAR_READ_CTRL>>`[src]

`pub fn sar1_data_inv(&self) -> SAR1_DATA_INV_R`[src]

Bit 28

`pub fn sar1_dig_force(&self) -> SAR1_DIG_FORCE_R`[src]

Bit 27

`pub fn sar1_sample_num(&self) -> SAR1_SAMPLE_NUM_R`[src]

Bits 19:26

`pub fn sar1_clk_gated(&self) -> SAR1_CLK_GATED_R`[src]

Bit 18

`pub fn sar1_sample_bit(&self) -> SAR1_SAMPLE_BIT_R`[src]

Bits 16:17

`pub fn sar1_sample_cycle(&self) -> SAR1_SAMPLE_CYCLE_R`[src]

Bits 8:15

`pub fn sar1_clk_div(&self) -> SAR1_CLK_DIV_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _SAR_READ_STATUS1>>`[src]

`pub fn sar1_reader_status(&self) -> SAR1_READER_STATUS_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _SAR_MEAS_WAIT1>>`[src]

`pub fn sar_amp_wait2(&self) -> SAR_AMP_WAIT2_R`[src]

Bits 16:31

`pub fn sar_amp_wait1(&self) -> SAR_AMP_WAIT1_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _SAR_MEAS_WAIT2>>`[src]

`pub fn sar2_rstb_wait(&self) -> SAR2_RSTB_WAIT_R`[src]

Bits 20:27

`pub fn force_xpd_sar(&self) -> FORCE_XPD_SAR_R`[src]

Bits 18:19

`pub fn force_xpd_amp(&self) -> FORCE_XPD_AMP_R`[src]

Bits 16:17

`pub fn sar_amp_wait3(&self) -> SAR_AMP_WAIT3_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _SAR_MEAS_CTRL>>`[src]

`pub fn sar2_xpd_wait(&self) -> SAR2_XPD_WAIT_R`[src]

Bits 24:31

`pub fn sar_rstb_fsm(&self) -> SAR_RSTB_FSM_R`[src]

Bits 20:23

`pub fn xpd_sar_fsm(&self) -> XPD_SAR_FSM_R`[src]

Bits 16:19

`pub fn amp_short_ref_gnd_fsm(&self) -> AMP_SHORT_REF_GND_FSM_R`[src]

Bits 12:15

`pub fn amp_short_ref_fsm(&self) -> AMP_SHORT_REF_FSM_R`[src]

Bits 8:11

`pub fn amp_rst_fb_fsm(&self) -> AMP_RST_FB_FSM_R`[src]

`pub fn sar1_stop(&self) -> SAR1_STOP_R`[src]

Bit 23

`pub fn sar2_stop(&self) -> SAR2_STOP_R`[src]

Bit 22

`pub fn pc_init(&self) -> PC_INIT_R`[src]

Bits 11:21

`pub fn sarclk_en(&self) -> SARCLK_EN_R`[src]

Bit 10

`pub fn ulp_cp_start_top(&self) -> ULP_CP_START_TOP_R`[src]

Bit 9

`pub fn ulp_cp_force_start_top(&self) -> ULP_CP_FORCE_START_TOP_R`[src]

Bit 8

`pub fn sar2_pwdet_cct(&self) -> SAR2_PWDET_CCT_R`[src]

Bits 5:7

`pub fn sar2_en_test(&self) -> SAR2_EN_TEST_R`[src]

Bit 4

`pub fn sar2_bit_width(&self) -> SAR2_BIT_WIDTH_R`[src]

Bits 2:3

`pub fn sar1_bit_width(&self) -> SAR1_BIT_WIDTH_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _SAR_MEM_WR_CTRL>>`[src]

`pub fn rtc_mem_wr_offst_clr(&self) -> RTC_MEM_WR_OFFST_CLR_R`[src]

Bit 22

`pub fn mem_wr_addr_size(&self) -> MEM_WR_ADDR_SIZE_R`[src]

Bits 11:21

`pub fn mem_wr_addr_init(&self) -> MEM_WR_ADDR_INIT_R`[src]

Bits 0:10

`impl R<u32, Reg<u32, _SAR_ATTEN1>>`[src]

`pub fn sar1_atten(&self) -> SAR1_ATTEN_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _SAR_ATTEN2>>`[src]

`pub fn sar2_atten(&self) -> SAR2_ATTEN_R`[src]

Bits 0:31

`pub fn i2c_slave_addr7(&self) -> I2C_SLAVE_ADDR7_R`[src]

Bits 0:10

`impl R<u32, Reg<u32, _SAR_TSENS_CTRL>>`[src]

`pub fn tsens_dump_out(&self) -> TSENS_DUMP_OUT_R`[src]

Bit 26

`pub fn tsens_power_up_force(&self) -> TSENS_POWER_UP_FORCE_R`[src]

Bit 25

`pub fn tsens_power_up(&self) -> TSENS_POWER_UP_R`[src]

Bit 24

`pub fn tsens_clk_div(&self) -> TSENS_CLK_DIV_R`[src]

Bits 16:23

`pub fn tsens_in_inv(&self) -> TSENS_IN_INV_R`[src]

Bit 15

`pub fn tsens_clk_gated(&self) -> TSENS_CLK_GATED_R`[src]

Bit 14

`pub fn tsens_clk_inv(&self) -> TSENS_CLK_INV_R`[src]

Bit 13

`pub fn tsens_xpd_force(&self) -> TSENS_XPD_FORCE_R`[src]

Bit 12

`pub fn tsens_xpd_wait(&self) -> TSENS_XPD_WAIT_R`[src]

Bits 0:11

`pub fn touch_start_force(&self) -> TOUCH_START_FORCE_R`[src]

Bit 13

`pub fn touch_start_en(&self) -> TOUCH_START_EN_R`[src]

Bit 12

`pub fn touch_start_fsm_en(&self) -> TOUCH_START_FSM_EN_R`[src]

Bit 11

`pub fn touch_meas_done(&self) -> TOUCH_MEAS_DONE_R`[src]

Bit 10

`pub fn touch_meas_en(&self) -> TOUCH_MEAS_EN_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _SAR_TOUCH_ENABLE>>`[src]

`pub fn touch_pad_outen1(&self) -> TOUCH_PAD_OUTEN1_R`[src]

Bits 20:29

`pub fn touch_pad_outen2(&self) -> TOUCH_PAD_OUTEN2_R`[src]

Bits 10:19

`pub fn touch_pad_worken(&self) -> TOUCH_PAD_WORKEN_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _SAR_READ_CTRL2>>`[src]

`pub fn sar2_data_inv(&self) -> SAR2_DATA_INV_R`[src]

Bit 29

`pub fn sar2_dig_force(&self) -> SAR2_DIG_FORCE_R`[src]

Bit 28

`pub fn sar2_pwdet_force(&self) -> SAR2_PWDET_FORCE_R`[src]

Bit 27

`pub fn sar2_sample_num(&self) -> SAR2_SAMPLE_NUM_R`[src]

Bits 19:26

`pub fn sar2_clk_gated(&self) -> SAR2_CLK_GATED_R`[src]

Bit 18

`pub fn sar2_sample_bit(&self) -> SAR2_SAMPLE_BIT_R`[src]

Bits 16:17

`pub fn sar2_sample_cycle(&self) -> SAR2_SAMPLE_CYCLE_R`[src]

Bits 8:15

`pub fn sar2_clk_div(&self) -> SAR2_CLK_DIV_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _SAR_MEAS_START2>>`[src]

`pub fn sar2_en_pad_force(&self) -> SAR2_EN_PAD_FORCE_R`[src]

Bit 31

`pub fn sar2_en_pad(&self) -> SAR2_EN_PAD_R`[src]

Bits 19:30

`pub fn meas2_start_force(&self) -> MEAS2_START_FORCE_R`[src]

Bit 18

`pub fn meas2_start_sar(&self) -> MEAS2_START_SAR_R`[src]

Bit 17

`pub fn meas2_done_sar(&self) -> MEAS2_DONE_SAR_R`[src]

Bit 16

`pub fn meas2_data_sar(&self) -> MEAS2_DATA_SAR_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _SAR_DAC_CTRL1>>`[src]

`pub fn dac_clk_inv(&self) -> DAC_CLK_INV_R`[src]

Bit 25

`pub fn dac_clk_force_high(&self) -> DAC_CLK_FORCE_HIGH_R`[src]

Bit 24

`pub fn dac_clk_force_low(&self) -> DAC_CLK_FORCE_LOW_R`[src]

Bit 23

`pub fn dac_dig_force(&self) -> DAC_DIG_FORCE_R`[src]

Bit 22

`pub fn debug_bit_sel(&self) -> DEBUG_BIT_SEL_R`[src]

Bits 17:21

`pub fn sw_tone_en(&self) -> SW_TONE_EN_R`[src]

Bit 16

`pub fn sw_fstep(&self) -> SW_FSTEP_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _SAR_DAC_CTRL2>>`[src]

`pub fn dac_cw_en2(&self) -> DAC_CW_EN2_R`[src]

Bit 25

`pub fn dac_cw_en1(&self) -> DAC_CW_EN1_R`[src]

Bit 24

`pub fn dac_inv2(&self) -> DAC_INV2_R`[src]

Bits 22:23

`pub fn dac_inv1(&self) -> DAC_INV1_R`[src]

Bits 20:21

`pub fn dac_scale2(&self) -> DAC_SCALE2_R`[src]

Bits 18:19

`pub fn dac_scale1(&self) -> DAC_SCALE1_R`[src]

Bits 16:17

`pub fn dac_dc2(&self) -> DAC_DC2_R`[src]

Bits 8:15

`pub fn dac_dc1(&self) -> DAC_DC1_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _SAR_MEAS_CTRL2>>`[src]

`pub fn amp_short_ref_gnd_force(&self) -> AMP_SHORT_REF_GND_FORCE_R`[src]

Bits 17:18

`pub fn amp_short_ref_force(&self) -> AMP_SHORT_REF_FORCE_R`[src]

Bits 15:16

`pub fn amp_rst_fb_force(&self) -> AMP_RST_FB_FORCE_R`[src]

Bits 13:14

`pub fn sar2_rstb_force(&self) -> SAR2_RSTB_FORCE_R`[src]

Bits 11:12

`pub fn sar_rstb_fsm_idle(&self) -> SAR_RSTB_FSM_IDLE_R`[src]

Bit 10

`pub fn xpd_sar_fsm_idle(&self) -> XPD_SAR_FSM_IDLE_R`[src]

Bit 9

`pub fn amp_short_ref_gnd_fsm_idle(&self) -> AMP_SHORT_REF_GND_FSM_IDLE_R`[src]

Bit 8

`pub fn amp_short_ref_fsm_idle(&self) -> AMP_SHORT_REF_FSM_IDLE_R`[src]

Bit 7

`pub fn amp_rst_fb_fsm_idle(&self) -> AMP_RST_FB_FSM_IDLE_R`[src]

Bit 6

`pub fn xpd_sar_amp_fsm_idle(&self) -> XPD_SAR_AMP_FSM_IDLE_R`[src]

Bit 5

`pub fn sar1_dac_xpd_fsm_idle(&self) -> SAR1_DAC_XPD_FSM_IDLE_R`[src]

Bit 4

`pub fn sar1_dac_xpd_fsm(&self) -> SAR1_DAC_XPD_FSM_R`[src]

Bits 0:3

`impl R<u32, Reg<u32, _PIN>>`[src]

`pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R`[src]

Bit 10

`pub fn int_type(&self) -> INT_TYPE_R`[src]

Bits 7:9

`pub fn pad_driver(&self) -> PAD_DRIVER_R`[src]

Bit 2

`impl R<u32, Reg<u32, _RTC_DEBUG_SEL>>`[src]

`pub fn debug_12m_no_gating(&self) -> DEBUG_12M_NO_GATING_R`[src]

Bit 25

`pub fn debug_sel4(&self) -> DEBUG_SEL4_R`[src]

Bits 20:24

`pub fn debug_sel3(&self) -> DEBUG_SEL3_R`[src]

Bits 15:19

`pub fn debug_sel2(&self) -> DEBUG_SEL2_R`[src]

Bits 10:14

`pub fn debug_sel1(&self) -> DEBUG_SEL1_R`[src]

Bits 5:9

`pub fn debug_sel0(&self) -> DEBUG_SEL0_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _DIG_PAD_HOLD>>`[src]

`pub fn dig_pad_hold(&self) -> DIG_PAD_HOLD_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _HALL_SENS>>`[src]

`pub fn xpd_hall(&self) -> XPD_HALL_R`[src]

Bit 31

`pub fn hall_phase(&self) -> HALL_PHASE_R`[src]

Bit 30

`impl R<u32, Reg<u32, _SENSOR_PADS>>`[src]

`pub fn sense1_hold(&self) -> SENSE1_HOLD_R`[src]

Bit 31

`pub fn sense2_hold(&self) -> SENSE2_HOLD_R`[src]

Bit 30

`pub fn sense3_hold(&self) -> SENSE3_HOLD_R`[src]

Bit 29

`pub fn sense4_hold(&self) -> SENSE4_HOLD_R`[src]

Bit 28

`pub fn sense1_mux_sel(&self) -> SENSE1_MUX_SEL_R`[src]

Bit 27

`pub fn sense2_mux_sel(&self) -> SENSE2_MUX_SEL_R`[src]

Bit 26

`pub fn sense3_mux_sel(&self) -> SENSE3_MUX_SEL_R`[src]

Bit 25

`pub fn sense4_mux_sel(&self) -> SENSE4_MUX_SEL_R`[src]

Bit 24

`pub fn sense1_fun_sel(&self) -> SENSE1_FUN_SEL_R`[src]

Bits 22:23

`pub fn sense1_slp_sel(&self) -> SENSE1_SLP_SEL_R`[src]

Bit 21

`pub fn sense1_slp_ie(&self) -> SENSE1_SLP_IE_R`[src]

Bit 20

`pub fn sense1_fun_ie(&self) -> SENSE1_FUN_IE_R`[src]

Bit 19

`pub fn sense2_fun_sel(&self) -> SENSE2_FUN_SEL_R`[src]

Bits 17:18

`pub fn sense2_slp_sel(&self) -> SENSE2_SLP_SEL_R`[src]

Bit 16

`pub fn sense2_slp_ie(&self) -> SENSE2_SLP_IE_R`[src]

Bit 15

`pub fn sense2_fun_ie(&self) -> SENSE2_FUN_IE_R`[src]

Bit 14

`pub fn sense3_fun_sel(&self) -> SENSE3_FUN_SEL_R`[src]

Bits 12:13

`pub fn sense3_slp_sel(&self) -> SENSE3_SLP_SEL_R`[src]

Bit 11

`pub fn sense3_slp_ie(&self) -> SENSE3_SLP_IE_R`[src]

Bit 10

`pub fn sense3_fun_ie(&self) -> SENSE3_FUN_IE_R`[src]

Bit 9

`pub fn sense4_fun_sel(&self) -> SENSE4_FUN_SEL_R`[src]

Bits 7:8

`pub fn sense4_slp_sel(&self) -> SENSE4_SLP_SEL_R`[src]

Bit 6

`pub fn sense4_slp_ie(&self) -> SENSE4_SLP_IE_R`[src]

Bit 5

`pub fn sense4_fun_ie(&self) -> SENSE4_FUN_IE_R`[src]

Bit 4

`impl R<u32, Reg<u32, _ADC_PAD>>`[src]

`pub fn adc1_hold(&self) -> ADC1_HOLD_R`[src]

Bit 31

`pub fn adc2_hold(&self) -> ADC2_HOLD_R`[src]

Bit 30

`pub fn adc1_mux_sel(&self) -> ADC1_MUX_SEL_R`[src]

Bit 29

`pub fn adc2_mux_sel(&self) -> ADC2_MUX_SEL_R`[src]

Bit 28

`pub fn adc1_fun_sel(&self) -> ADC1_FUN_SEL_R`[src]

Bits 26:27

`pub fn adc1_slp_sel(&self) -> ADC1_SLP_SEL_R`[src]

Bit 25

`pub fn adc1_slp_ie(&self) -> ADC1_SLP_IE_R`[src]

Bit 24

`pub fn adc1_fun_ie(&self) -> ADC1_FUN_IE_R`[src]

Bit 23

`pub fn adc2_fun_sel(&self) -> ADC2_FUN_SEL_R`[src]

Bits 21:22

`pub fn adc2_slp_sel(&self) -> ADC2_SLP_SEL_R`[src]

Bit 20

`pub fn adc2_slp_ie(&self) -> ADC2_SLP_IE_R`[src]

Bit 19

`pub fn adc2_fun_ie(&self) -> ADC2_FUN_IE_R`[src]

Bit 18

`impl R<u32, Reg<u32, _PAD_DAC1>>`[src]

`pub fn pdac1_drv(&self) -> PDAC1_DRV_R`[src]

Bits 30:31

`pub fn pdac1_hold(&self) -> PDAC1_HOLD_R`[src]

Bit 29

`pub fn pdac1_rde(&self) -> PDAC1_RDE_R`[src]

Bit 28

`pub fn pdac1_rue(&self) -> PDAC1_RUE_R`[src]

Bit 27

`pub fn pdac1_dac(&self) -> PDAC1_DAC_R`[src]

Bits 19:26

`pub fn pdac1_xpd_dac(&self) -> PDAC1_XPD_DAC_R`[src]

Bit 18

`pub fn pdac1_mux_sel(&self) -> PDAC1_MUX_SEL_R`[src]

Bit 17

`pub fn pdac1_fun_sel(&self) -> PDAC1_FUN_SEL_R`[src]

Bits 15:16

`pub fn pdac1_slp_sel(&self) -> PDAC1_SLP_SEL_R`[src]

Bit 14

`pub fn pdac1_slp_ie(&self) -> PDAC1_SLP_IE_R`[src]

Bit 13

`pub fn pdac1_slp_oe(&self) -> PDAC1_SLP_OE_R`[src]

Bit 12

`pub fn pdac1_fun_ie(&self) -> PDAC1_FUN_IE_R`[src]

Bit 11

`pub fn pdac1_dac_xpd_force(&self) -> PDAC1_DAC_XPD_FORCE_R`[src]

Bit 10

`impl R<u32, Reg<u32, _PAD_DAC2>>`[src]

`pub fn pdac2_drv(&self) -> PDAC2_DRV_R`[src]

Bits 30:31

`pub fn pdac2_hold(&self) -> PDAC2_HOLD_R`[src]

Bit 29

`pub fn pdac2_rde(&self) -> PDAC2_RDE_R`[src]

Bit 28

`pub fn pdac2_rue(&self) -> PDAC2_RUE_R`[src]

Bit 27

`pub fn pdac2_dac(&self) -> PDAC2_DAC_R`[src]

Bits 19:26

`pub fn pdac2_xpd_dac(&self) -> PDAC2_XPD_DAC_R`[src]

Bit 18

`pub fn pdac2_mux_sel(&self) -> PDAC2_MUX_SEL_R`[src]

Bit 17

`pub fn pdac2_fun_sel(&self) -> PDAC2_FUN_SEL_R`[src]

Bits 15:16

`pub fn pdac2_slp_sel(&self) -> PDAC2_SLP_SEL_R`[src]

Bit 14

`pub fn pdac2_slp_ie(&self) -> PDAC2_SLP_IE_R`[src]

Bit 13

`pub fn pdac2_slp_oe(&self) -> PDAC2_SLP_OE_R`[src]

Bit 12

`pub fn pdac2_fun_ie(&self) -> PDAC2_FUN_IE_R`[src]

Bit 11

`pub fn pdac2_dac_xpd_force(&self) -> PDAC2_DAC_XPD_FORCE_R`[src]

Bit 10

`impl R<u32, Reg<u32, _XTAL_32K_PAD>>`[src]

`pub fn x32n_drv(&self) -> X32N_DRV_R`[src]

Bits 30:31

`pub fn x32n_hold(&self) -> X32N_HOLD_R`[src]

Bit 29

`pub fn x32n_rde(&self) -> X32N_RDE_R`[src]

Bit 28

`pub fn x32n_rue(&self) -> X32N_RUE_R`[src]

Bit 27

`pub fn x32p_drv(&self) -> X32P_DRV_R`[src]

Bits 25:26

`pub fn x32p_hold(&self) -> X32P_HOLD_R`[src]

Bit 24

`pub fn x32p_rde(&self) -> X32P_RDE_R`[src]

Bit 23

`pub fn x32p_rue(&self) -> X32P_RUE_R`[src]

Bit 22

`pub fn dac_xtal_32k(&self) -> DAC_XTAL_32K_R`[src]

Bits 20:21

`pub fn xpd_xtal_32k(&self) -> XPD_XTAL_32K_R`[src]

Bit 19

`pub fn x32n_mux_sel(&self) -> X32N_MUX_SEL_R`[src]

Bit 18

`pub fn x32p_mux_sel(&self) -> X32P_MUX_SEL_R`[src]

Bit 17

`pub fn x32n_fun_sel(&self) -> X32N_FUN_SEL_R`[src]

Bits 15:16

`pub fn x32n_slp_sel(&self) -> X32N_SLP_SEL_R`[src]

Bit 14

`pub fn x32n_slp_ie(&self) -> X32N_SLP_IE_R`[src]

Bit 13

`pub fn x32n_slp_oe(&self) -> X32N_SLP_OE_R`[src]

Bit 12

`pub fn x32n_fun_ie(&self) -> X32N_FUN_IE_R`[src]

Bit 11

`pub fn x32p_fun_sel(&self) -> X32P_FUN_SEL_R`[src]

Bits 9:10

`pub fn x32p_slp_sel(&self) -> X32P_SLP_SEL_R`[src]

Bit 8

`pub fn x32p_slp_ie(&self) -> X32P_SLP_IE_R`[src]

Bit 7

`pub fn x32p_slp_oe(&self) -> X32P_SLP_OE_R`[src]

Bit 6

`pub fn x32p_fun_ie(&self) -> X32P_FUN_IE_R`[src]

Bit 5

`pub fn dres_xtal_32k(&self) -> DRES_XTAL_32K_R`[src]

Bits 3:4

`pub fn dbias_xtal_32k(&self) -> DBIAS_XTAL_32K_R`[src]

Bits 1:2

`impl R<u32, Reg<u32, _TOUCH_CFG>>`[src]

`pub fn touch_xpd_bias(&self) -> TOUCH_XPD_BIAS_R`[src]

Bit 31

`pub fn touch_drefh(&self) -> TOUCH_DREFH_R`[src]

Bits 29:30

`pub fn touch_drefl(&self) -> TOUCH_DREFL_R`[src]

Bits 27:28

`pub fn touch_drange(&self) -> TOUCH_DRANGE_R`[src]

Bits 25:26

`pub fn touch_dcur(&self) -> TOUCH_DCUR_R`[src]

Bits 23:24

`impl R<u32, Reg<u32, _TOUCH_PAD0>>`[src]

`pub fn hold(&self) -> HOLD_R`[src]

Bit 31

`pub fn drv(&self) -> DRV_R`[src]

Bits 29:30

`pub fn rde(&self) -> RDE_R`[src]

Bit 28

`pub fn rue(&self) -> RUE_R`[src]

Bit 27

`pub fn dac(&self) -> DAC_R`[src]

Bits 23:25

`pub fn start(&self) -> START_R`[src]

Bit 22

`pub fn tie_opt(&self) -> TIE_OPT_R`[src]

Bit 21

`pub fn xpd(&self) -> XPD_R`[src]

Bit 20

`pub fn mux_sel(&self) -> MUX_SEL_R`[src]

Bit 19

`pub fn fun_sel(&self) -> FUN_SEL_R`[src]

Bits 17:18

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 16

`pub fn slp_ie(&self) -> SLP_IE_R`[src]

Bit 15

`pub fn slp_oe(&self) -> SLP_OE_R`[src]

Bit 14

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 13

`pub fn to_gpio(&self) -> TO_GPIO_R`[src]

Bit 12

`impl R<u32, Reg<u32, _TOUCH_PAD1>>`[src]

`pub fn hold(&self) -> HOLD_R`[src]

Bit 31

`pub fn drv(&self) -> DRV_R`[src]

Bits 29:30

`pub fn rde(&self) -> RDE_R`[src]

Bit 28

`pub fn rue(&self) -> RUE_R`[src]

Bit 27

`pub fn dac(&self) -> DAC_R`[src]

Bits 23:25

`pub fn start(&self) -> START_R`[src]

Bit 22

`pub fn tie_opt(&self) -> TIE_OPT_R`[src]

Bit 21

`pub fn xpd(&self) -> XPD_R`[src]

Bit 20

`pub fn mux_sel(&self) -> MUX_SEL_R`[src]

Bit 19

`pub fn fun_sel(&self) -> FUN_SEL_R`[src]

Bits 17:18

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 16

`pub fn slp_ie(&self) -> SLP_IE_R`[src]

Bit 15

`pub fn slp_oe(&self) -> SLP_OE_R`[src]

Bit 14

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 13

`pub fn to_gpio(&self) -> TO_GPIO_R`[src]

Bit 12

`impl R<u32, Reg<u32, _TOUCH_PAD2>>`[src]

`pub fn hold(&self) -> HOLD_R`[src]

Bit 31

`pub fn drv(&self) -> DRV_R`[src]

Bits 29:30

`pub fn rde(&self) -> RDE_R`[src]

Bit 28

`pub fn rue(&self) -> RUE_R`[src]

Bit 27

`pub fn dac(&self) -> DAC_R`[src]

Bits 23:25

`pub fn start(&self) -> START_R`[src]

Bit 22

`pub fn tie_opt(&self) -> TIE_OPT_R`[src]

Bit 21

`pub fn xpd(&self) -> XPD_R`[src]

Bit 20

`pub fn mux_sel(&self) -> MUX_SEL_R`[src]

Bit 19

`pub fn fun_sel(&self) -> FUN_SEL_R`[src]

Bits 17:18

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 16

`pub fn slp_ie(&self) -> SLP_IE_R`[src]

Bit 15

`pub fn slp_oe(&self) -> SLP_OE_R`[src]

Bit 14

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 13

`pub fn to_gpio(&self) -> TO_GPIO_R`[src]

Bit 12

`impl R<u32, Reg<u32, _TOUCH_PAD3>>`[src]

`pub fn hold(&self) -> HOLD_R`[src]

Bit 31

`pub fn drv(&self) -> DRV_R`[src]

Bits 29:30

`pub fn rde(&self) -> RDE_R`[src]

Bit 28

`pub fn rue(&self) -> RUE_R`[src]

Bit 27

`pub fn dac(&self) -> DAC_R`[src]

Bits 23:25

`pub fn start(&self) -> START_R`[src]

Bit 22

`pub fn tie_opt(&self) -> TIE_OPT_R`[src]

Bit 21

`pub fn xpd(&self) -> XPD_R`[src]

Bit 20

`pub fn mux_sel(&self) -> MUX_SEL_R`[src]

Bit 19

`pub fn fun_sel(&self) -> FUN_SEL_R`[src]

Bits 17:18

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 16

`pub fn slp_ie(&self) -> SLP_IE_R`[src]

Bit 15

`pub fn slp_oe(&self) -> SLP_OE_R`[src]

Bit 14

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 13

`pub fn to_gpio(&self) -> TO_GPIO_R`[src]

Bit 12

`impl R<u32, Reg<u32, _TOUCH_PAD4>>`[src]

`pub fn hold(&self) -> HOLD_R`[src]

Bit 31

`pub fn drv(&self) -> DRV_R`[src]

Bits 29:30

`pub fn rde(&self) -> RDE_R`[src]

Bit 28

`pub fn rue(&self) -> RUE_R`[src]

Bit 27

`pub fn dac(&self) -> DAC_R`[src]

Bits 23:25

`pub fn start(&self) -> START_R`[src]

Bit 22

`pub fn tie_opt(&self) -> TIE_OPT_R`[src]

Bit 21

`pub fn xpd(&self) -> XPD_R`[src]

Bit 20

`pub fn mux_sel(&self) -> MUX_SEL_R`[src]

Bit 19

`pub fn fun_sel(&self) -> FUN_SEL_R`[src]

Bits 17:18

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 16

`pub fn slp_ie(&self) -> SLP_IE_R`[src]

Bit 15

`pub fn slp_oe(&self) -> SLP_OE_R`[src]

Bit 14

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 13

`pub fn to_gpio(&self) -> TO_GPIO_R`[src]

Bit 12

`impl R<u32, Reg<u32, _TOUCH_PAD5>>`[src]

`pub fn hold(&self) -> HOLD_R`[src]

Bit 31

`pub fn drv(&self) -> DRV_R`[src]

Bits 29:30

`pub fn rde(&self) -> RDE_R`[src]

Bit 28

`pub fn rue(&self) -> RUE_R`[src]

Bit 27

`pub fn dac(&self) -> DAC_R`[src]

Bits 23:25

`pub fn start(&self) -> START_R`[src]

Bit 22

`pub fn tie_opt(&self) -> TIE_OPT_R`[src]

Bit 21

`pub fn xpd(&self) -> XPD_R`[src]

Bit 20

`pub fn mux_sel(&self) -> MUX_SEL_R`[src]

Bit 19

`pub fn fun_sel(&self) -> FUN_SEL_R`[src]

Bits 17:18

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 16

`pub fn slp_ie(&self) -> SLP_IE_R`[src]

Bit 15

`pub fn slp_oe(&self) -> SLP_OE_R`[src]

Bit 14

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 13

`pub fn to_gpio(&self) -> TO_GPIO_R`[src]

Bit 12

`impl R<u32, Reg<u32, _TOUCH_PAD6>>`[src]

`pub fn hold(&self) -> HOLD_R`[src]

Bit 31

`pub fn drv(&self) -> DRV_R`[src]

Bits 29:30

`pub fn rde(&self) -> RDE_R`[src]

Bit 28

`pub fn rue(&self) -> RUE_R`[src]

Bit 27

`pub fn dac(&self) -> DAC_R`[src]

Bits 23:25

`pub fn start(&self) -> START_R`[src]

Bit 22

`pub fn tie_opt(&self) -> TIE_OPT_R`[src]

Bit 21

`pub fn xpd(&self) -> XPD_R`[src]

Bit 20

`pub fn mux_sel(&self) -> MUX_SEL_R`[src]

Bit 19

`pub fn fun_sel(&self) -> FUN_SEL_R`[src]

Bits 17:18

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 16

`pub fn slp_ie(&self) -> SLP_IE_R`[src]

Bit 15

`pub fn slp_oe(&self) -> SLP_OE_R`[src]

Bit 14

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 13

`pub fn to_gpio(&self) -> TO_GPIO_R`[src]

Bit 12

`impl R<u32, Reg<u32, _TOUCH_PAD7>>`[src]

`pub fn hold(&self) -> HOLD_R`[src]

Bit 31

`pub fn drv(&self) -> DRV_R`[src]

Bits 29:30

`pub fn rde(&self) -> RDE_R`[src]

Bit 28

`pub fn rue(&self) -> RUE_R`[src]

Bit 27

`pub fn dac(&self) -> DAC_R`[src]

Bits 23:25

`pub fn start(&self) -> START_R`[src]

Bit 22

`pub fn tie_opt(&self) -> TIE_OPT_R`[src]

Bit 21

`pub fn xpd(&self) -> XPD_R`[src]

Bit 20

`pub fn mux_sel(&self) -> MUX_SEL_R`[src]

Bit 19

`pub fn fun_sel(&self) -> FUN_SEL_R`[src]

Bits 17:18

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 16

`pub fn slp_ie(&self) -> SLP_IE_R`[src]

Bit 15

`pub fn slp_oe(&self) -> SLP_OE_R`[src]

Bit 14

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 13

`pub fn to_gpio(&self) -> TO_GPIO_R`[src]

Bit 12

`impl R<u32, Reg<u32, _TOUCH_PAD8>>`[src]

`pub fn dac(&self) -> DAC_R`[src]

Bits 23:25

`pub fn start(&self) -> START_R`[src]

Bit 22

`pub fn tie_opt(&self) -> TIE_OPT_R`[src]

Bit 21

`pub fn xpd(&self) -> XPD_R`[src]

Bit 20

`pub fn to_gpio(&self) -> TO_GPIO_R`[src]

Bit 19

`impl R<u32, Reg<u32, _TOUCH_PAD9>>`[src]

`pub fn dac(&self) -> DAC_R`[src]

Bits 23:25

`pub fn start(&self) -> START_R`[src]

Bit 22

`pub fn tie_opt(&self) -> TIE_OPT_R`[src]

Bit 21

`pub fn xpd(&self) -> XPD_R`[src]

Bit 20

`pub fn to_gpio(&self) -> TO_GPIO_R`[src]

Bit 19

`impl R<u32, Reg<u32, _EXT_WAKEUP0>>`[src]

`pub fn ext_wakeup0_sel(&self) -> EXT_WAKEUP0_SEL_R`[src]

Bits 27:31

`impl R<u32, Reg<u32, _XTL_EXT_CTR>>`[src]

`pub fn xtl_ext_ctr_sel(&self) -> XTL_EXT_CTR_SEL_R`[src]

Bits 27:31

`impl R<u32, Reg<u32, _SAR_I2C_IO>>`[src]

`pub fn sar_i2c_sda_sel(&self) -> SAR_I2C_SDA_SEL_R`[src]

Bits 30:31

`pub fn sar_i2c_scl_sel(&self) -> SAR_I2C_SCL_SEL_R`[src]

Bits 28:29

`pub fn sar_debug_bit_sel(&self) -> SAR_DEBUG_BIT_SEL_R`[src]

Bits 23:27

`impl R<u32, Reg<u32, _DATE>>`[src]

`pub fn io_date(&self) -> IO_DATE_R`[src]

Bits 0:27

`impl R<u32, Reg<u32, _PRO_BOOT_REMAP_CTRL>>`[src]

`pub fn pro_boot_remap(&self) -> PRO_BOOT_REMAP_R`[src]

Bit 0

`impl R<u32, Reg<u32, _APP_BOOT_REMAP_CTRL>>`[src]

`pub fn app_boot_remap(&self) -> APP_BOOT_REMAP_R`[src]

Bit 0

`impl R<u32, Reg<u32, _ACCESS_CHECK>>`[src]

`pub fn access_check_app(&self) -> ACCESS_CHECK_APP_R`[src]

`pub fn digital_signature(&self) -> DIGITAL_SIGNATURE_R`[src]

Bit 4

`pub fn secure_boot(&self) -> SECURE_BOOT_R`[src]

Bit 3

`pub fn rsa_accelerator(&self) -> RSA_ACCELERATOR_R`[src]

Bit 2

`pub fn sha_accelerator(&self) -> SHA_ACCELERATOR_R`[src]

Bit 1

`pub fn aes_accelerator(&self) -> AES_ACCELERATOR_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PERI_RST_EN>>`[src]

`pub fn peri_rst_en(&self) -> PERI_RST_EN_R`[src]

Bits 0:31

`pub fn digital_signature(&self) -> DIGITAL_SIGNATURE_R`[src]

Bit 4

`pub fn secure_boot(&self) -> SECURE_BOOT_R`[src]

Bit 3

`pub fn rsa_accelerator(&self) -> RSA_ACCELERATOR_R`[src]

Bit 2

`pub fn sha_accelerator(&self) -> SHA_ACCELERATOR_R`[src]

`pub fn is_sel_80(&self) -> bool`[src]

Checks if the value of the field is SEL_80

`pub fn is_sel_160(&self) -> bool`[src]

Checks if the value of the field is SEL_160

`pub fn is_sel_240(&self) -> bool`[src]

Checks if the value of the field is SEL_240

`impl R<u32, Reg<u32, _CPU_PER_CONF>>`[src]

`pub fn fast_clk_rtc_sel(&self) -> FAST_CLK_RTC_SEL_R`[src]

Bit 3

`pub fn lowspeed_clk_sel(&self) -> LOWSPEED_CLK_SEL_R`[src]

Bit 2

`pub fn cpuperiod_sel(&self) -> CPUPERIOD_SEL_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _PRO_CACHE_CTRL>>`[src]

`pub fn pro_dram_hl(&self) -> PRO_DRAM_HL_R`[src]

Bit 16

`pub fn slave_req(&self) -> SLAVE_REQ_R`[src]

Bit 15

`pub fn ahb_spi_req(&self) -> AHB_SPI_REQ_R`[src]

Bit 14

`pub fn pro_slave_req(&self) -> PRO_SLAVE_REQ_R`[src]

Bit 13

`pub fn pro_ahb_spi_req(&self) -> PRO_AHB_SPI_REQ_R`[src]

Bit 12

`pub fn pro_dram_split(&self) -> PRO_DRAM_SPLIT_R`[src]

Bit 11

`pub fn pro_single_iram_ena(&self) -> PRO_SINGLE_IRAM_ENA_R`[src]

Bit 10

`pub fn pro_cache_lock_3_en(&self) -> PRO_CACHE_LOCK_3_EN_R`[src]

Bit 9

`pub fn pro_cache_lock_2_en(&self) -> PRO_CACHE_LOCK_2_EN_R`[src]

Bit 8

`pub fn pro_cache_lock_1_en(&self) -> PRO_CACHE_LOCK_1_EN_R`[src]

Bit 7

`pub fn pro_cache_lock_0_en(&self) -> PRO_CACHE_LOCK_0_EN_R`[src]

Bit 6

`pub fn pro_cache_flush_done(&self) -> PRO_CACHE_FLUSH_DONE_R`[src]

Bit 5

`pub fn pro_cache_flush_ena(&self) -> PRO_CACHE_FLUSH_ENA_R`[src]

Bit 4

`pub fn pro_cache_enable(&self) -> PRO_CACHE_ENABLE_R`[src]

Bit 3

`pub fn pro_cache_mode(&self) -> PRO_CACHE_MODE_R`[src]

Bit 2

`impl R<u32, Reg<u32, _PRO_CACHE_CTRL1>>`[src]

`pub fn pro_cache_mmu_ia_clr(&self) -> PRO_CACHE_MMU_IA_CLR_R`[src]

Bit 13

`pub fn pro_cmmu_pd(&self) -> PRO_CMMU_PD_R`[src]

Bit 12

`pub fn pro_cmmu_force_on(&self) -> PRO_CMMU_FORCE_ON_R`[src]

Bit 11

`pub fn pro_cmmu_flash_page_mode(&self) -> PRO_CMMU_FLASH_PAGE_MODE_R`[src]

Bits 9:10

`pub fn pro_cmmu_sram_page_mode(&self) -> PRO_CMMU_SRAM_PAGE_MODE_R`[src]

Bits 6:8

`pub fn pro_cache_mask_opsdram(&self) -> PRO_CACHE_MASK_OPSDRAM_R`[src]

Bit 5

`pub fn pro_cache_mask_drom0(&self) -> PRO_CACHE_MASK_DROM0_R`[src]

Bit 4

`pub fn pro_cache_mask_dram1(&self) -> PRO_CACHE_MASK_DRAM1_R`[src]

`pub fn app_dram_split(&self) -> APP_DRAM_SPLIT_R`[src]

Bit 11

`pub fn app_single_iram_ena(&self) -> APP_SINGLE_IRAM_ENA_R`[src]

Bit 10

`pub fn app_cache_lock_3_en(&self) -> APP_CACHE_LOCK_3_EN_R`[src]

Bit 9

`pub fn app_cache_lock_2_en(&self) -> APP_CACHE_LOCK_2_EN_R`[src]

Bit 8

`pub fn app_cache_lock_1_en(&self) -> APP_CACHE_LOCK_1_EN_R`[src]

Bit 7

`pub fn app_cache_lock_0_en(&self) -> APP_CACHE_LOCK_0_EN_R`[src]

Bit 6

`pub fn app_cache_flush_done(&self) -> APP_CACHE_FLUSH_DONE_R`[src]

Bit 5

`pub fn app_cache_flush_ena(&self) -> APP_CACHE_FLUSH_ENA_R`[src]

Bit 4

`pub fn app_cache_enable(&self) -> APP_CACHE_ENABLE_R`[src]

Bit 3

`pub fn app_cache_mode(&self) -> APP_CACHE_MODE_R`[src]

Bit 2

`impl R<u32, Reg<u32, _APP_CACHE_CTRL1>>`[src]

`pub fn app_cache_mmu_ia_clr(&self) -> APP_CACHE_MMU_IA_CLR_R`[src]

Bit 13

`pub fn app_cmmu_pd(&self) -> APP_CMMU_PD_R`[src]

Bit 12

`pub fn app_cmmu_force_on(&self) -> APP_CMMU_FORCE_ON_R`[src]

Bit 11

`pub fn app_cmmu_flash_page_mode(&self) -> APP_CMMU_FLASH_PAGE_MODE_R`[src]

Bits 9:10

`pub fn app_cmmu_sram_page_mode(&self) -> APP_CMMU_SRAM_PAGE_MODE_R`[src]

Bits 6:8

`pub fn app_cache_mask_opsdram(&self) -> APP_CACHE_MASK_OPSDRAM_R`[src]

Bit 5

`pub fn app_cache_mask_drom0(&self) -> APP_CACHE_MASK_DROM0_R`[src]

Bit 4

`pub fn app_cache_mask_dram1(&self) -> APP_CACHE_MASK_DRAM1_R`[src]

Bit 3

`pub fn app_cache_mask_irom0(&self) -> APP_CACHE_MASK_IROM0_R`[src]

Bit 2

`pub fn app_cache_mask_iram1(&self) -> APP_CACHE_MASK_IRAM1_R`[src]

Bit 1

`pub fn app_cache_mask_iram0(&self) -> APP_CACHE_MASK_IRAM0_R`[src]

Bit 0

`impl R<u32, Reg<u32, _APP_CACHE_LOCK_0_ADDR>>`[src]

`pub fn app_cache_lock_0_addr_max(&self) -> APP_CACHE_LOCK_0_ADDR_MAX_R`[src]

Bits 18:21

`pub fn app_cache_lock_0_addr_min(&self) -> APP_CACHE_LOCK_0_ADDR_MIN_R`[src]

Bits 14:17

`pub fn app_cache_lock_0_addr_pre(&self) -> APP_CACHE_LOCK_0_ADDR_PRE_R`[src]

Bits 0:13

`impl R<u32, Reg<u32, _APP_CACHE_LOCK_1_ADDR>>`[src]

`pub fn app_cache_lock_1_addr_max(&self) -> APP_CACHE_LOCK_1_ADDR_MAX_R`[src]

Bits 18:21

`pub fn app_cache_lock_1_addr_min(&self) -> APP_CACHE_LOCK_1_ADDR_MIN_R`[src]

Bits 14:17

`pub fn app_cache_lock_1_addr_pre(&self) -> APP_CACHE_LOCK_1_ADDR_PRE_R`[src]

Bits 0:13

`impl R<u32, Reg<u32, _APP_CACHE_LOCK_2_ADDR>>`[src]

`pub fn app_cache_lock_2_addr_max(&self) -> APP_CACHE_LOCK_2_ADDR_MAX_R`[src]

Bits 18:21

`pub fn app_cache_lock_2_addr_min(&self) -> APP_CACHE_LOCK_2_ADDR_MIN_R`[src]

Bits 14:17

`pub fn app_cache_lock_2_addr_pre(&self) -> APP_CACHE_LOCK_2_ADDR_PRE_R`[src]

Bits 0:13

`impl R<u32, Reg<u32, _APP_CACHE_LOCK_3_ADDR>>`[src]

`pub fn app_cache_lock_3_addr_max(&self) -> APP_CACHE_LOCK_3_ADDR_MAX_R`[src]

Bits 18:21

`pub fn app_cache_lock_3_addr_min(&self) -> APP_CACHE_LOCK_3_ADDR_MIN_R`[src]

Bits 14:17

`pub fn app_cache_lock_3_addr_pre(&self) -> APP_CACHE_LOCK_3_ADDR_PRE_R`[src]

Bits 0:13

`impl R<u32, Reg<u32, _TRACEMEM_MUX_MODE>>`[src]

`pub fn tracemem_mux_mode(&self) -> TRACEMEM_MUX_MODE_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _PRO_TRACEMEM_ENA>>`[src]

`pub fn pro_tracemem_ena(&self) -> PRO_TRACEMEM_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _APP_TRACEMEM_ENA>>`[src]

`pub fn app_tracemem_ena(&self) -> APP_TRACEMEM_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CACHE_MUX_MODE>>`[src]

`pub fn cache_mux_mode(&self) -> CACHE_MUX_MODE_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _IMMU_PAGE_MODE>>`[src]

`pub fn immu_page_mode(&self) -> IMMU_PAGE_MODE_R`[src]

Bits 1:2

`pub fn internal_sram_immu_ena(&self) -> INTERNAL_SRAM_IMMU_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DMMU_PAGE_MODE>>`[src]

`pub fn dmmu_page_mode(&self) -> DMMU_PAGE_MODE_R`[src]

Bits 1:2

`pub fn internal_sram_dmmu_ena(&self) -> INTERNAL_SRAM_DMMU_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _ROM_MPU_ENA>>`[src]

`pub fn app_rom_mpu_ena(&self) -> APP_ROM_MPU_ENA_R`[src]

Bit 2

`pub fn pro_rom_mpu_ena(&self) -> PRO_ROM_MPU_ENA_R`[src]

Bit 1

`pub fn share_rom_mpu_ena(&self) -> SHARE_ROM_MPU_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _MEM_PD_MASK>>`[src]

`pub fn lslp_mem_pd_mask(&self) -> LSLP_MEM_PD_MASK_R`[src]

Bit 0

`impl R<u32, Reg<u32, _ROM_PD_CTRL>>`[src]

`pub fn share_rom_pd(&self) -> SHARE_ROM_PD_R`[src]

Bits 2:7

`pub fn app_rom_pd(&self) -> APP_ROM_PD_R`[src]

Bit 1

`pub fn pro_rom_pd(&self) -> PRO_ROM_PD_R`[src]

Bit 0

`impl R<u32, Reg<u32, _ROM_FO_CTRL>>`[src]

`pub fn share_rom_fo(&self) -> SHARE_ROM_FO_R`[src]

Bits 2:7

`pub fn app_rom_fo(&self) -> APP_ROM_FO_R`[src]

`pub fn mask_ahb(&self) -> MASK_AHB_R`[src]

Bit 4

`pub fn mask_app_dram(&self) -> MASK_APP_DRAM_R`[src]

Bit 3

`pub fn mask_pro_dram(&self) -> MASK_PRO_DRAM_R`[src]

Bit 2

`pub fn mask_app_iram(&self) -> MASK_APP_IRAM_R`[src]

Bit 1

`pub fn mask_pro_iram(&self) -> MASK_PRO_IRAM_R`[src]

Bit 0

`impl R<u32, Reg<u32, _TAG_FO_CTRL>>`[src]

`pub fn app_cache_tag_pd(&self) -> APP_CACHE_TAG_PD_R`[src]

Bit 9

`pub fn app_cache_tag_force_on(&self) -> APP_CACHE_TAG_FORCE_ON_R`[src]

Bit 8

`pub fn pro_cache_tag_pd(&self) -> PRO_CACHE_TAG_PD_R`[src]

Bit 1

`pub fn pro_cache_tag_force_on(&self) -> PRO_CACHE_TAG_FORCE_ON_R`[src]

Bit 0

`impl R<u32, Reg<u32, _AHB_LITE_MASK>>`[src]

`pub fn ahb_lite_sdhost_pid_reg(&self) -> AHB_LITE_SDHOST_PID_REG_R`[src]

Bits 11:13

`pub fn ahb_lite_mask_appdport(&self) -> AHB_LITE_MASK_APPDPORT_R`[src]

Bit 10

`pub fn ahb_lite_mask_prodport(&self) -> AHB_LITE_MASK_PRODPORT_R`[src]

Bit 9

`pub fn ahb_lite_mask_sdio(&self) -> AHB_LITE_MASK_SDIO_R`[src]

Bit 8

`pub fn ahb_lite_mask_app(&self) -> AHB_LITE_MASK_APP_R`[src]

Bit 4

`pub fn ahb_lite_mask_pro(&self) -> AHB_LITE_MASK_PRO_R`[src]

Bit 0

`impl R<u32, Reg<u32, _AHB_MPU_TABLE_0>>`[src]

`pub fn ahb_access_grant_0(&self) -> AHB_ACCESS_GRANT_0_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _AHB_MPU_TABLE_1>>`[src]

`pub fn ahb_access_grant_1(&self) -> AHB_ACCESS_GRANT_1_R`[src]

Bits 0:8

`impl R<u32, Reg<u32, _HOST_INF_SEL>>`[src]

`pub fn link_device_sel(&self) -> LINK_DEVICE_SEL_R`[src]

Bits 8:15

`pub fn peri_io_swap(&self) -> PERI_IO_SWAP_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _PERIP_CLK_EN>>`[src]

`pub fn perip_clk_en(&self) -> PERIP_CLK_EN_R`[src]

Bits 0:31

`pub fn pwm3(&self) -> PWM3_R`[src]

Bit 26

`pub fn pwm2(&self) -> PWM2_R`[src]

Bit 25

`pub fn uart_mem(&self) -> UART_MEM_R`[src]

Bit 24

`pub fn uart2(&self) -> UART2_R`[src]

Bit 23

`pub fn spi_dma(&self) -> SPI_DMA_R`[src]

Bit 22

`pub fn i2s1(&self) -> I2S1_R`[src]

Bit 21

`pub fn pwm1(&self) -> PWM1_R`[src]

Bit 20

`pub fn can(&self) -> CAN_R`[src]

Bit 19

`pub fn i2c1(&self) -> I2C1_R`[src]

Bit 18

`pub fn pwm0(&self) -> PWM0_R`[src]

Bit 17

`pub fn spi3(&self) -> SPI3_R`[src]

Bit 16

`pub fn timer_group1(&self) -> TIMER_GROUP1_R`[src]

Bit 15

`pub fn efuse(&self) -> EFUSE_R`[src]

Bit 14

`pub fn timer_group0(&self) -> TIMER_GROUP0_R`[src]

Bit 13

`pub fn uhci1(&self) -> UHCI1_R`[src]

Bit 12

`pub fn led_pwm(&self) -> LED_PWM_R`[src]

Bit 11

`pub fn pulse_cnt(&self) -> PULSE_CNT_R`[src]

Bit 10

`pub fn remote_controller(&self) -> REMOTE_CONTROLLER_R`[src]

Bit 9

`pub fn uhci0(&self) -> UHCI0_R`[src]

Bit 8

`pub fn i2c0(&self) -> I2C0_R`[src]

Bit 7

`pub fn spi2(&self) -> SPI2_R`[src]

Bit 6

`pub fn uart1(&self) -> UART1_R`[src]

Bit 5

`pub fn i2s0(&self) -> I2S0_R`[src]

Bit 4

`pub fn wdg(&self) -> WDG_R`[src]

Bit 3

`pub fn uart0(&self) -> UART0_R`[src]

Bit 2

`pub fn spi0(&self) -> SPI0_R`[src]

Bit 1

`pub fn timers(&self) -> TIMERS_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PERIP_RST_EN>>`[src]

`pub fn perip_rst(&self) -> PERIP_RST_R`[src]

Bits 0:31

`pub fn spi_decrypt_enable(&self) -> SPI_DECRYPT_ENABLE_R`[src]

Bit 12

`pub fn spi_encrypt_enable(&self) -> SPI_ENCRYPT_ENABLE_R`[src]

Bit 8

`pub fn slave_spi_mask_app(&self) -> SLAVE_SPI_MASK_APP_R`[src]

Bit 4

`pub fn slave_spi_mask_pro(&self) -> SLAVE_SPI_MASK_PRO_R`[src]

Bit 0

`pub fn pwm3(&self) -> PWM3_R`[src]

Bit 26

`pub fn pwm2(&self) -> PWM2_R`[src]

Bit 25

`pub fn uart_mem(&self) -> UART_MEM_R`[src]

Bit 24

`pub fn uart2(&self) -> UART2_R`[src]

Bit 23

`pub fn spi_dma(&self) -> SPI_DMA_R`[src]

Bit 22

`pub fn i2s1(&self) -> I2S1_R`[src]

Bit 21

`pub fn pwm1(&self) -> PWM1_R`[src]

Bit 20

`pub fn can(&self) -> CAN_R`[src]

Bit 19

`pub fn i2c1(&self) -> I2C1_R`[src]

Bit 18

`pub fn pwm0(&self) -> PWM0_R`[src]

Bit 17

`pub fn spi3(&self) -> SPI3_R`[src]

Bit 16

`pub fn timer_group1(&self) -> TIMER_GROUP1_R`[src]

Bit 15

`pub fn efuse(&self) -> EFUSE_R`[src]

Bit 14

`pub fn timer_group0(&self) -> TIMER_GROUP0_R`[src]

Bit 13

`pub fn uhci1(&self) -> UHCI1_R`[src]

Bit 12

`pub fn led_pwm(&self) -> LED_PWM_R`[src]

Bit 11

`pub fn pulse_cnt(&self) -> PULSE_CNT_R`[src]

Bit 10

`pub fn remote_controller(&self) -> REMOTE_CONTROLLER_R`[src]

Bit 9

`pub fn uhci0(&self) -> UHCI0_R`[src]

Bit 8

`pub fn i2c0(&self) -> I2C0_R`[src]

Bit 7

`pub fn spi2(&self) -> SPI2_R`[src]

Bit 6

`pub fn uart1(&self) -> UART1_R`[src]

Bit 5

`pub fn i2s0(&self) -> I2S0_R`[src]

Bit 4

`pub fn wdg(&self) -> WDG_R`[src]

Bit 3

`pub fn uart0(&self) -> UART0_R`[src]

Bit 2

`pub fn spi0(&self) -> SPI0_R`[src]

Bit 1

`pub fn timers(&self) -> TIMERS_R`[src]

Bit 0

`impl R<u32, Reg<u32, _WIFI_CLK_EN>>`[src]

`pub fn wifi_clk_en(&self) -> WIFI_CLK_EN_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _CORE_RST_EN>>`[src]

`pub fn core_rst(&self) -> CORE_RST_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _BT_LPCK_DIV_INT>>`[src]

`pub fn btextwakeup_req(&self) -> BTEXTWAKEUP_REQ_R`[src]

Bit 12

`pub fn bt_lpck_div_num(&self) -> BT_LPCK_DIV_NUM_R`[src]

Bits 0:11

`impl R<u32, Reg<u32, _BT_LPCK_DIV_FRAC>>`[src]

`pub fn lpclk_sel_xtal32k(&self) -> LPCLK_SEL_XTAL32K_R`[src]

Bit 27

`pub fn lpclk_sel_xtal(&self) -> LPCLK_SEL_XTAL_R`[src]

Bit 26

`pub fn lpclk_sel_8m(&self) -> LPCLK_SEL_8M_R`[src]

Bit 25

`pub fn lpclk_sel_rtc_slow(&self) -> LPCLK_SEL_RTC_SLOW_R`[src]

Bit 24

`pub fn bt_lpck_div_a(&self) -> BT_LPCK_DIV_A_R`[src]

`impl R<u32, Reg<u32, _MEM_ACCESS_DBUG0>>`[src]

`pub fn internal_sram_mmu_multi_hit(&self) -> INTERNAL_SRAM_MMU_MULTI_HIT_R`[src]

Bits 26:29

`pub fn internal_sram_ia(&self) -> INTERNAL_SRAM_IA_R`[src]

Bits 14:25

`pub fn internal_sram_mmu_ad(&self) -> INTERNAL_SRAM_MMU_AD_R`[src]

Bits 10:13

`pub fn share_rom_ia(&self) -> SHARE_ROM_IA_R`[src]

Bits 6:9

`pub fn share_rom_mpu_ad(&self) -> SHARE_ROM_MPU_AD_R`[src]

Bits 4:5

`pub fn app_rom_ia(&self) -> APP_ROM_IA_R`[src]

Bit 3

`pub fn app_rom_mpu_ad(&self) -> APP_ROM_MPU_AD_R`[src]

Bit 2

`pub fn pro_rom_ia(&self) -> PRO_ROM_IA_R`[src]

Bit 1

`pub fn pro_rom_mpu_ad(&self) -> PRO_ROM_MPU_AD_R`[src]

Bit 0

`impl R<u32, Reg<u32, _MEM_ACCESS_DBUG1>>`[src]

`pub fn ahblite_ia(&self) -> AHBLITE_IA_R`[src]

Bit 10

`pub fn ahblite_access_deny(&self) -> AHBLITE_ACCESS_DENY_R`[src]

Bit 9

`pub fn ahb_access_deny(&self) -> AHB_ACCESS_DENY_R`[src]

Bit 8

`pub fn pidgen_ia(&self) -> PIDGEN_IA_R`[src]

Bits 6:7

`pub fn arb_ia(&self) -> ARB_IA_R`[src]

Bits 4:5

`pub fn internal_sram_mmu_miss(&self) -> INTERNAL_SRAM_MMU_MISS_R`[src]

Bits 0:3

`impl R<u32, Reg<u32, _PRO_DCACHE_DBUG0>>`[src]

`pub fn pro_rx_end(&self) -> PRO_RX_END_R`[src]

Bit 23

`pub fn pro_slave_wdata_v(&self) -> PRO_SLAVE_WDATA_V_R`[src]

Bit 22

`pub fn pro_slave_wr(&self) -> PRO_SLAVE_WR_R`[src]

Bit 21

`pub fn pro_tx_end(&self) -> PRO_TX_END_R`[src]

Bit 20

`pub fn pro_wr_bak_to_read(&self) -> PRO_WR_BAK_TO_READ_R`[src]

Bit 19

`pub fn pro_cache_state(&self) -> PRO_CACHE_STATE_R`[src]

Bits 7:18

`pub fn pro_cache_ia(&self) -> PRO_CACHE_IA_R`[src]

Bits 1:6

`pub fn pro_cache_mmu_ia(&self) -> PRO_CACHE_MMU_IA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PRO_DCACHE_DBUG1>>`[src]

`pub fn pro_ctag_ram_rdata(&self) -> PRO_CTAG_RAM_RDATA_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _PRO_DCACHE_DBUG2>>`[src]

`pub fn pro_cache_vaddr(&self) -> PRO_CACHE_VADDR_R`[src]

Bits 0:26

`impl R<u32, Reg<u32, _PRO_DCACHE_DBUG3>>`[src]

`pub fn pro_cache_iram0_pid_error(&self) -> PRO_CACHE_IRAM0_PID_ERROR_R`[src]

`pub fn app_slave_wdata_v(&self) -> APP_SLAVE_WDATA_V_R`[src]

Bit 22

`pub fn app_slave_wr(&self) -> APP_SLAVE_WR_R`[src]

Bit 21

`pub fn app_tx_end(&self) -> APP_TX_END_R`[src]

Bit 20

`pub fn app_wr_bak_to_read(&self) -> APP_WR_BAK_TO_READ_R`[src]

Bit 19

`pub fn app_cache_state(&self) -> APP_CACHE_STATE_R`[src]

Bits 7:18

`pub fn app_cache_ia(&self) -> APP_CACHE_IA_R`[src]

Bits 1:6

`pub fn app_cache_mmu_ia(&self) -> APP_CACHE_MMU_IA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _APP_DCACHE_DBUG1>>`[src]

`pub fn app_ctag_ram_rdata(&self) -> APP_CTAG_RAM_RDATA_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _APP_DCACHE_DBUG2>>`[src]

`pub fn app_cache_vaddr(&self) -> APP_CACHE_VADDR_R`[src]

Bits 0:26

`impl R<u32, Reg<u32, _APP_DCACHE_DBUG3>>`[src]

`pub fn app_cache_iram0_pid_error(&self) -> APP_CACHE_IRAM0_PID_ERROR_R`[src]

`pub fn pro_cpu_record_disable(&self) -> PRO_CPU_RECORD_DISABLE_R`[src]

`impl R<u32, Reg<u32, _APP_CPU_RECORD_CTRL>>`[src]

`pub fn app_cpu_pdebug_enable(&self) -> APP_CPU_PDEBUG_ENABLE_R`[src]

Bit 8

`pub fn app_cpu_record_disable(&self) -> APP_CPU_RECORD_DISABLE_R`[src]

`impl R<u32, Reg<u32, _FRONT_END_MEM_PD>>`[src]

`pub fn pbus_mem_force_pd(&self) -> PBUS_MEM_FORCE_PD_R`[src]

Bit 3

`pub fn pbus_mem_force_pu(&self) -> PBUS_MEM_FORCE_PU_R`[src]

Bit 2

`pub fn agc_mem_force_pd(&self) -> AGC_MEM_FORCE_PD_R`[src]

Bit 1

`pub fn agc_mem_force_pu(&self) -> AGC_MEM_FORCE_PU_R`[src]

Bit 0

`impl R<u32, Reg<u32, _MMU_IA_INT_EN>>`[src]

`pub fn mmu_ia_int_en(&self) -> MMU_IA_INT_EN_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _MPU_IA_INT_EN>>`[src]

`pub fn mpu_ia_int_en(&self) -> MPU_IA_INT_EN_R`[src]

Bits 0:16

`impl R<u32, Reg<u32, _CACHE_IA_INT_EN>>`[src]

`pub fn cache_ia_int_en(&self) -> CACHE_IA_INT_EN_R`[src]

Bits 0:27

`pub fn cache_ia_int_pro_opposite(&self) -> CACHE_IA_INT_PRO_OPPOSITE_R`[src]

Bit 19

`pub fn cache_ia_int_pro_dram1(&self) -> CACHE_IA_INT_PRO_DRAM1_R`[src]

Bit 18

`pub fn cache_ia_int_pro_irom0(&self) -> CACHE_IA_INT_PRO_IROM0_R`[src]

Bit 17

`pub fn cache_ia_int_pro_iram1(&self) -> CACHE_IA_INT_PRO_IRAM1_R`[src]

Bit 16

`pub fn cache_ia_int_pro_iram0(&self) -> CACHE_IA_INT_PRO_IRAM0_R`[src]

Bit 15

`pub fn cache_ia_int_pro_drom0(&self) -> CACHE_IA_INT_PRO_DROM0_R`[src]

Bit 14

`pub fn cache_ia_int_app_opposite(&self) -> CACHE_IA_INT_APP_OPPOSITE_R`[src]

Bit 5

`pub fn cache_ia_int_app_irom0(&self) -> CACHE_IA_INT_APP_IROM0_R`[src]

Bit 3

`pub fn cache_ia_int_app_iram1(&self) -> CACHE_IA_INT_APP_IRAM1_R`[src]

Bit 2

`pub fn cache_ia_int_app_iram0(&self) -> CACHE_IA_INT_APP_IRAM0_R`[src]

Bit 1

`pub fn cache_ia_int_app_drom0(&self) -> CACHE_IA_INT_APP_DROM0_R`[src]

Bit 0

`impl R<u32, Reg<u32, _SECURE_BOOT_CTRL>>`[src]

`pub fn sw_bootloader_sel(&self) -> SW_BOOTLOADER_SEL_R`[src]

Bit 0

`impl R<u32, Reg<u32, _SPI_DMA_CHAN_SEL>>`[src]

`pub fn spi3_dma_chan_sel(&self) -> SPI3_DMA_CHAN_SEL_R`[src]

Bits 4:5

`pub fn spi2_dma_chan_sel(&self) -> SPI2_DMA_CHAN_SEL_R`[src]

`impl R<u32, Reg<u32, _T0CONFIG>>`[src]

`pub fn t0_en(&self) -> T0_EN_R`[src]

Bit 31

`pub fn t0_increase(&self) -> T0_INCREASE_R`[src]

Bit 30

`pub fn t0_autoreload(&self) -> T0_AUTORELOAD_R`[src]

Bit 29

`pub fn t0_divider(&self) -> T0_DIVIDER_R`[src]

Bits 13:28

`pub fn t0_edge_int_en(&self) -> T0_EDGE_INT_EN_R`[src]

Bit 12

`pub fn t0_level_int_en(&self) -> T0_LEVEL_INT_EN_R`[src]

`pub fn t1_increase(&self) -> T1_INCREASE_R`[src]

Bit 30

`pub fn t1_autoreload(&self) -> T1_AUTORELOAD_R`[src]

Bit 29

`pub fn t1_divider(&self) -> T1_DIVIDER_R`[src]

Bits 13:28

`pub fn t1_edge_int_en(&self) -> T1_EDGE_INT_EN_R`[src]

Bit 12

`pub fn t1_level_int_en(&self) -> T1_LEVEL_INT_EN_R`[src]

`pub fn is_disable(&self) -> bool`[src]

Checks if the value of the field is DISABLE

`pub fn is_interrupt(&self) -> bool`[src]

Checks if the value of the field is INTERRUPT

`pub fn is_reset_cpu(&self) -> bool`[src]

Checks if the value of the field is RESETCPU

`pub fn is_reset_system(&self) -> bool`[src]

Checks if the value of the field is RESETSYSTEM

`impl R<u8, WDT_CPU_RESET_LENGTH_A>`[src]

`pub fn variant(&self) -> WDT_CPU_RESET_LENGTH_A`[src]

Get enumerated values variant

`pub fn is_t100ns(&self) -> bool`[src]

Checks if the value of the field is T100NS

`pub fn is_t200ns(&self) -> bool`[src]

Checks if the value of the field is T200NS

`pub fn is_t300ns(&self) -> bool`[src]

Checks if the value of the field is T300NS

`pub fn is_t400ns(&self) -> bool`[src]

Checks if the value of the field is T400NS

`pub fn is_t500ns(&self) -> bool`[src]

Checks if the value of the field is T500NS

`pub fn is_t800ns(&self) -> bool`[src]

Checks if the value of the field is T800NS

`pub fn is_t1600ns(&self) -> bool`[src]

Checks if the value of the field is T1600NS

`pub fn is_t3200ns(&self) -> bool`[src]

Checks if the value of the field is T3200NS

`impl R<u32, Reg<u32, _WDTCONFIG0>>`[src]

`pub fn wdt_en(&self) -> WDT_EN_R`[src]

Bit 31

`pub fn wdt_stg0(&self) -> WDT_STG0_R`[src]

Bits 29:30

`pub fn wdt_stg1(&self) -> WDT_STG1_R`[src]

Bits 27:28

`pub fn wdt_stg2(&self) -> WDT_STG2_R`[src]

Bits 25:26

`pub fn wdt_stg3(&self) -> WDT_STG3_R`[src]

Bits 23:24

`pub fn wdt_edge_int_en(&self) -> WDT_EDGE_INT_EN_R`[src]

Bit 22

`pub fn wdt_level_int_en(&self) -> WDT_LEVEL_INT_EN_R`[src]

Bit 21

`pub fn wdt_cpu_reset_length(&self) -> WDT_CPU_RESET_LENGTH_R`[src]

Bits 18:20

`pub fn wdt_sys_reset_length(&self) -> WDT_SYS_RESET_LENGTH_R`[src]

`impl R<u8, CLK_SEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, CLK_SEL_A>`[src]

Get enumerated values variant

`pub fn is_rtc_mux(&self) -> bool`[src]

Checks if the value of the field is RTC_MUX

`pub fn is_ck8m_d256(&self) -> bool`[src]

Checks if the value of the field is CK8M_D256

`pub fn is_xtal32k(&self) -> bool`[src]

Checks if the value of the field is XTAL32K

`impl R<u32, Reg<u32, _RTCCALICFG>>`[src]

`pub fn start(&self) -> START_R`[src]

Bit 31

`pub fn max(&self) -> MAX_R`[src]

Bits 16:30

`pub fn rdy(&self) -> RDY_R`[src]

Bit 15

`pub fn clk_sel(&self) -> CLK_SEL_R`[src]

Bits 13:14

`pub fn start_cycling(&self) -> START_CYCLING_R`[src]

Bit 12

`impl R<u32, Reg<u32, _RTCCALICFG1>>`[src]

`pub fn value(&self) -> VALUE_R`[src]

Bits 7:31

`impl R<u32, Reg<u32, _LACTCONFIG>>`[src]

`pub fn lact_en(&self) -> LACT_EN_R`[src]

Bit 31

`pub fn lact_increase(&self) -> LACT_INCREASE_R`[src]

Bit 30

`pub fn lact_autoreload(&self) -> LACT_AUTORELOAD_R`[src]

Bit 29

`pub fn lact_divider(&self) -> LACT_DIVIDER_R`[src]

Bits 13:28

`pub fn lact_edge_int_en(&self) -> LACT_EDGE_INT_EN_R`[src]

Bit 12

`pub fn lact_level_int_en(&self) -> LACT_LEVEL_INT_EN_R`[src]

Bit 11

`pub fn lact_alarm_en(&self) -> LACT_ALARM_EN_R`[src]

Bit 10

`pub fn lact_lac_en(&self) -> LACT_LAC_EN_R`[src]

Bit 9

`pub fn lact_cpst_en(&self) -> LACT_CPST_EN_R`[src]

`impl R<u32, Reg<u32, _NTIMERS_DATE>>`[src]

`pub fn ntimers_date(&self) -> NTIMERS_DATE_R`[src]

Bits 0:27

`impl R<u32, Reg<u32, _TIMGCLK>>`[src]

`impl R<u32, Reg<u32, _SIGMADELTA_MISC>>`[src]

`pub fn spi_swap(&self) -> SPI_SWAP_R`[src]

Bit 31

`impl R<u32, Reg<u32, _SIGMADELTA_VERSION>>`[src]

`pub fn sd_date(&self) -> SD_DATE_R`[src]

Bits 0:27

`impl R<u32, Reg<u32, _PIN_CTRL>>`[src]

`pub fn pin_ctrl_clk3(&self) -> PIN_CTRL_CLK3_R`[src]

Bits 8:10

`pub fn pin_ctrl_clk2(&self) -> PIN_CTRL_CLK2_R`[src]

Bits 4:6

`pub fn pin_ctrl_clk1(&self) -> PIN_CTRL_CLK1_R`[src]

Bits 0:2

`impl R<u32, Reg<u32, _GPIO36>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO37>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO38>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO39>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO34>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures drive strength during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO35>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO32>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO33>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO25>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO26>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO27>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _MTMS>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _MTDI>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _MTCK>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _MTDO>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO2>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO0>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO4>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO16>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO17>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _SD_DATA2>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _SD_DATA3>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _SD_CMD>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _SD_CLK>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _SD_DATA0>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _SD_DATA1>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO5>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO18>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO19>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO20>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO21>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO22>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _U0RXD>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _U0TXD>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO23>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _GPIO24>>`[src]

`pub fn mcu_sel(&self) -> MCU_SEL_R`[src]

Bits 12:13 - configures IO_MUX function

`pub fn fun_drv(&self) -> FUN_DRV_R`[src]

Bits 10:11 - configures drive strength

`pub fn fun_ie(&self) -> FUN_IE_R`[src]

Bit 9 - configures input enable

`pub fn fun_wpu(&self) -> FUN_WPU_R`[src]

Bit 8 - configures pull up

`pub fn fun_wpd(&self) -> FUN_WPD_R`[src]

Bit 7 - configures pull down

`pub fn mcu_drv(&self) -> MCU_DRV_R`[src]

Bits 5:6 - configures drive strength during sleep mode

`pub fn mcu_ie(&self) -> MCU_IE_R`[src]

Bit 4 - configures input enable during sleep mode

`pub fn mcu_wpu(&self) -> MCU_WPU_R`[src]

Bit 3 - configures pull up during sleep mode

`pub fn mcu_wpd(&self) -> MCU_WPD_R`[src]

Bit 2 - configures pull down during sleep mode

`pub fn slp_sel(&self) -> SLP_SEL_R`[src]

Bit 1 - configures sleep mode selection

`pub fn mcu_oe(&self) -> MCU_OE_R`[src]

Bit 0 - configures output enable during sleep mode

`impl R<u32, Reg<u32, _CONF>>`[src]

`pub fn sig_loopback(&self) -> SIG_LOOPBACK_R`[src]

Bit 18

`pub fn rx_msb_right(&self) -> RX_MSB_RIGHT_R`[src]

Bit 17

`pub fn tx_msb_right(&self) -> TX_MSB_RIGHT_R`[src]

Bit 16

`pub fn rx_mono(&self) -> RX_MONO_R`[src]

Bit 15

`pub fn tx_mono(&self) -> TX_MONO_R`[src]

Bit 14

`pub fn rx_short_sync(&self) -> RX_SHORT_SYNC_R`[src]

Bit 13

`pub fn tx_short_sync(&self) -> TX_SHORT_SYNC_R`[src]

Bit 12

`pub fn rx_msb_shift(&self) -> RX_MSB_SHIFT_R`[src]

Bit 11

`pub fn tx_msb_shift(&self) -> TX_MSB_SHIFT_R`[src]

Bit 10

`pub fn rx_right_first(&self) -> RX_RIGHT_FIRST_R`[src]

Bit 9

`pub fn tx_right_first(&self) -> TX_RIGHT_FIRST_R`[src]

Bit 8

`pub fn rx_slave_mod(&self) -> RX_SLAVE_MOD_R`[src]

Bit 7

`pub fn tx_slave_mod(&self) -> TX_SLAVE_MOD_R`[src]

Bit 6

`pub fn rx_start(&self) -> RX_START_R`[src]

Bit 5

`pub fn tx_start(&self) -> TX_START_R`[src]

Bit 4

`pub fn rx_fifo_reset(&self) -> RX_FIFO_RESET_R`[src]

Bit 3

`pub fn tx_fifo_reset(&self) -> TX_FIFO_RESET_R`[src]

Bit 2

`pub fn rx_reset(&self) -> RX_RESET_R`[src]

Bit 1

`pub fn tx_reset(&self) -> TX_RESET_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_RAW>>`[src]

`pub fn out_total_eof_int_raw(&self) -> OUT_TOTAL_EOF_INT_RAW_R`[src]

Bit 16

`pub fn in_dscr_empty_int_raw(&self) -> IN_DSCR_EMPTY_INT_RAW_R`[src]

Bit 15

`pub fn out_dscr_err_int_raw(&self) -> OUT_DSCR_ERR_INT_RAW_R`[src]

Bit 14

`pub fn in_dscr_err_int_raw(&self) -> IN_DSCR_ERR_INT_RAW_R`[src]

Bit 13

`pub fn out_eof_int_raw(&self) -> OUT_EOF_INT_RAW_R`[src]

Bit 12

`pub fn out_done_int_raw(&self) -> OUT_DONE_INT_RAW_R`[src]

Bit 11

`pub fn in_err_eof_int_raw(&self) -> IN_ERR_EOF_INT_RAW_R`[src]

Bit 10

`pub fn in_suc_eof_int_raw(&self) -> IN_SUC_EOF_INT_RAW_R`[src]

Bit 9

`pub fn in_done_int_raw(&self) -> IN_DONE_INT_RAW_R`[src]

Bit 8

`pub fn tx_hung_int_raw(&self) -> TX_HUNG_INT_RAW_R`[src]

Bit 7

`pub fn rx_hung_int_raw(&self) -> RX_HUNG_INT_RAW_R`[src]

Bit 6

`pub fn tx_rempty_int_raw(&self) -> TX_REMPTY_INT_RAW_R`[src]

Bit 5

`pub fn tx_wfull_int_raw(&self) -> TX_WFULL_INT_RAW_R`[src]

Bit 4

`pub fn rx_rempty_int_raw(&self) -> RX_REMPTY_INT_RAW_R`[src]

Bit 3

`pub fn rx_wfull_int_raw(&self) -> RX_WFULL_INT_RAW_R`[src]

Bit 2

`pub fn tx_put_data_int_raw(&self) -> TX_PUT_DATA_INT_RAW_R`[src]

Bit 1

`pub fn rx_take_data_int_raw(&self) -> RX_TAKE_DATA_INT_RAW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_ST>>`[src]

`pub fn out_total_eof_int_st(&self) -> OUT_TOTAL_EOF_INT_ST_R`[src]

Bit 16

`pub fn in_dscr_empty_int_st(&self) -> IN_DSCR_EMPTY_INT_ST_R`[src]

Bit 15

`pub fn out_dscr_err_int_st(&self) -> OUT_DSCR_ERR_INT_ST_R`[src]

Bit 14

`pub fn in_dscr_err_int_st(&self) -> IN_DSCR_ERR_INT_ST_R`[src]

Bit 13

`pub fn out_eof_int_st(&self) -> OUT_EOF_INT_ST_R`[src]

Bit 12

`pub fn out_done_int_st(&self) -> OUT_DONE_INT_ST_R`[src]

Bit 11

`pub fn in_err_eof_int_st(&self) -> IN_ERR_EOF_INT_ST_R`[src]

Bit 10

`pub fn in_suc_eof_int_st(&self) -> IN_SUC_EOF_INT_ST_R`[src]

Bit 9

`pub fn in_done_int_st(&self) -> IN_DONE_INT_ST_R`[src]

Bit 8

`pub fn tx_hung_int_st(&self) -> TX_HUNG_INT_ST_R`[src]

Bit 7

`pub fn rx_hung_int_st(&self) -> RX_HUNG_INT_ST_R`[src]

Bit 6

`pub fn tx_rempty_int_st(&self) -> TX_REMPTY_INT_ST_R`[src]

Bit 5

`pub fn tx_wfull_int_st(&self) -> TX_WFULL_INT_ST_R`[src]

Bit 4

`pub fn rx_rempty_int_st(&self) -> RX_REMPTY_INT_ST_R`[src]

Bit 3

`pub fn rx_wfull_int_st(&self) -> RX_WFULL_INT_ST_R`[src]

Bit 2

`pub fn tx_put_data_int_st(&self) -> TX_PUT_DATA_INT_ST_R`[src]

Bit 1

`pub fn rx_take_data_int_st(&self) -> RX_TAKE_DATA_INT_ST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_ENA>>`[src]

`pub fn out_total_eof_int_ena(&self) -> OUT_TOTAL_EOF_INT_ENA_R`[src]

Bit 16

`pub fn in_dscr_empty_int_ena(&self) -> IN_DSCR_EMPTY_INT_ENA_R`[src]

Bit 15

`pub fn out_dscr_err_int_ena(&self) -> OUT_DSCR_ERR_INT_ENA_R`[src]

Bit 14

`pub fn in_dscr_err_int_ena(&self) -> IN_DSCR_ERR_INT_ENA_R`[src]

Bit 13

`pub fn out_eof_int_ena(&self) -> OUT_EOF_INT_ENA_R`[src]

Bit 12

`pub fn out_done_int_ena(&self) -> OUT_DONE_INT_ENA_R`[src]

Bit 11

`pub fn in_err_eof_int_ena(&self) -> IN_ERR_EOF_INT_ENA_R`[src]

Bit 10

`pub fn in_suc_eof_int_ena(&self) -> IN_SUC_EOF_INT_ENA_R`[src]

Bit 9

`pub fn in_done_int_ena(&self) -> IN_DONE_INT_ENA_R`[src]

Bit 8

`pub fn tx_hung_int_ena(&self) -> TX_HUNG_INT_ENA_R`[src]

Bit 7

`pub fn rx_hung_int_ena(&self) -> RX_HUNG_INT_ENA_R`[src]

Bit 6

`pub fn tx_rempty_int_ena(&self) -> TX_REMPTY_INT_ENA_R`[src]

Bit 5

`pub fn tx_wfull_int_ena(&self) -> TX_WFULL_INT_ENA_R`[src]

Bit 4

`pub fn rx_rempty_int_ena(&self) -> RX_REMPTY_INT_ENA_R`[src]

Bit 3

`pub fn rx_wfull_int_ena(&self) -> RX_WFULL_INT_ENA_R`[src]

Bit 2

`pub fn tx_put_data_int_ena(&self) -> TX_PUT_DATA_INT_ENA_R`[src]

Bit 1

`pub fn rx_take_data_int_ena(&self) -> RX_TAKE_DATA_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_CLR>>`[src]

`pub fn out_total_eof_int_clr(&self) -> OUT_TOTAL_EOF_INT_CLR_R`[src]

Bit 16

`pub fn in_dscr_empty_int_clr(&self) -> IN_DSCR_EMPTY_INT_CLR_R`[src]

Bit 15

`pub fn out_dscr_err_int_clr(&self) -> OUT_DSCR_ERR_INT_CLR_R`[src]

Bit 14

`pub fn in_dscr_err_int_clr(&self) -> IN_DSCR_ERR_INT_CLR_R`[src]

Bit 13

`pub fn out_eof_int_clr(&self) -> OUT_EOF_INT_CLR_R`[src]

Bit 12

`pub fn out_done_int_clr(&self) -> OUT_DONE_INT_CLR_R`[src]

Bit 11

`pub fn in_err_eof_int_clr(&self) -> IN_ERR_EOF_INT_CLR_R`[src]

Bit 10

`pub fn in_suc_eof_int_clr(&self) -> IN_SUC_EOF_INT_CLR_R`[src]

Bit 9

`pub fn in_done_int_clr(&self) -> IN_DONE_INT_CLR_R`[src]

Bit 8

`pub fn tx_hung_int_clr(&self) -> TX_HUNG_INT_CLR_R`[src]

Bit 7

`pub fn rx_hung_int_clr(&self) -> RX_HUNG_INT_CLR_R`[src]

Bit 6

`pub fn tx_rempty_int_clr(&self) -> TX_REMPTY_INT_CLR_R`[src]

Bit 5

`pub fn tx_wfull_int_clr(&self) -> TX_WFULL_INT_CLR_R`[src]

Bit 4

`pub fn rx_rempty_int_clr(&self) -> RX_REMPTY_INT_CLR_R`[src]

Bit 3

`pub fn rx_wfull_int_clr(&self) -> RX_WFULL_INT_CLR_R`[src]

Bit 2

`pub fn put_data_int_clr(&self) -> PUT_DATA_INT_CLR_R`[src]

Bit 1

`pub fn take_data_int_clr(&self) -> TAKE_DATA_INT_CLR_R`[src]

Bit 0

`impl R<u32, Reg<u32, _TIMING>>`[src]

`pub fn tx_bck_in_inv(&self) -> TX_BCK_IN_INV_R`[src]

Bit 24

`pub fn data_enable_delay(&self) -> DATA_ENABLE_DELAY_R`[src]

Bits 22:23

`pub fn rx_dsync_sw(&self) -> RX_DSYNC_SW_R`[src]

Bit 21

`pub fn tx_dsync_sw(&self) -> TX_DSYNC_SW_R`[src]

Bit 20

`pub fn rx_bck_out_delay(&self) -> RX_BCK_OUT_DELAY_R`[src]

Bits 18:19

`pub fn rx_ws_out_delay(&self) -> RX_WS_OUT_DELAY_R`[src]

Bits 16:17

`pub fn tx_sd_out_delay(&self) -> TX_SD_OUT_DELAY_R`[src]

Bits 14:15

`pub fn tx_ws_out_delay(&self) -> TX_WS_OUT_DELAY_R`[src]

Bits 12:13

`pub fn tx_bck_out_delay(&self) -> TX_BCK_OUT_DELAY_R`[src]

Bits 10:11

`pub fn rx_sd_in_delay(&self) -> RX_SD_IN_DELAY_R`[src]

Bits 8:9

`pub fn rx_ws_in_delay(&self) -> RX_WS_IN_DELAY_R`[src]

Bits 6:7

`pub fn rx_bck_in_delay(&self) -> RX_BCK_IN_DELAY_R`[src]

Bits 4:5

`pub fn tx_ws_in_delay(&self) -> TX_WS_IN_DELAY_R`[src]

Bits 2:3

`pub fn tx_bck_in_delay(&self) -> TX_BCK_IN_DELAY_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _FIFO_CONF>>`[src]

`pub fn rx_fifo_mod_force_en(&self) -> RX_FIFO_MOD_FORCE_EN_R`[src]

Bit 20

`pub fn tx_fifo_mod_force_en(&self) -> TX_FIFO_MOD_FORCE_EN_R`[src]

Bit 19

`pub fn rx_fifo_mod(&self) -> RX_FIFO_MOD_R`[src]

Bits 16:18

`pub fn tx_fifo_mod(&self) -> TX_FIFO_MOD_R`[src]

Bits 13:15

`pub fn dscr_en(&self) -> DSCR_EN_R`[src]

Bit 12

`pub fn tx_data_num(&self) -> TX_DATA_NUM_R`[src]

Bits 6:11

`pub fn rx_data_num(&self) -> RX_DATA_NUM_R`[src]

Bits 0:5

`impl R<u32, Reg<u32, _RXEOF_NUM>>`[src]

`pub fn rx_eof_num(&self) -> RX_EOF_NUM_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _CONF_SIGLE_DATA>>`[src]

`pub fn sigle_data(&self) -> SIGLE_DATA_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _CONF_CHAN>>`[src]

`pub fn rx_chan_mod(&self) -> RX_CHAN_MOD_R`[src]

Bits 3:4

`pub fn tx_chan_mod(&self) -> TX_CHAN_MOD_R`[src]

Bits 0:2

`impl R<u32, Reg<u32, _OUT_LINK>>`[src]

`pub fn outlink_park(&self) -> OUTLINK_PARK_R`[src]

Bit 31

`pub fn outlink_restart(&self) -> OUTLINK_RESTART_R`[src]

Bit 30

`pub fn outlink_start(&self) -> OUTLINK_START_R`[src]

Bit 29

`pub fn outlink_stop(&self) -> OUTLINK_STOP_R`[src]

Bit 28

`pub fn outlink_addr(&self) -> OUTLINK_ADDR_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _IN_LINK>>`[src]

`pub fn inlink_park(&self) -> INLINK_PARK_R`[src]

Bit 31

`pub fn inlink_restart(&self) -> INLINK_RESTART_R`[src]

Bit 30

`pub fn inlink_start(&self) -> INLINK_START_R`[src]

Bit 29

`pub fn inlink_stop(&self) -> INLINK_STOP_R`[src]

Bit 28

`pub fn inlink_addr(&self) -> INLINK_ADDR_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _OUT_EOF_DES_ADDR>>`[src]

`pub fn out_eof_des_addr(&self) -> OUT_EOF_DES_ADDR_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _IN_EOF_DES_ADDR>>`[src]

`pub fn in_suc_eof_des_addr(&self) -> IN_SUC_EOF_DES_ADDR_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _OUT_EOF_BFR_DES_ADDR>>`[src]

`pub fn out_eof_bfr_des_addr(&self) -> OUT_EOF_BFR_DES_ADDR_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _AHB_TEST>>`[src]

`pub fn ahb_testaddr(&self) -> AHB_TESTADDR_R`[src]

`pub fn check_owner(&self) -> CHECK_OWNER_R`[src]

Bit 12

`pub fn out_data_burst_en(&self) -> OUT_DATA_BURST_EN_R`[src]

Bit 11

`pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R`[src]

Bit 10

`pub fn outdscr_burst_en(&self) -> OUTDSCR_BURST_EN_R`[src]

Bit 9

`pub fn out_eof_mode(&self) -> OUT_EOF_MODE_R`[src]

Bit 8

`pub fn out_no_restart_clr(&self) -> OUT_NO_RESTART_CLR_R`[src]

Bit 7

`pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R`[src]

Bit 6

`pub fn in_loop_test(&self) -> IN_LOOP_TEST_R`[src]

Bit 5

`pub fn out_loop_test(&self) -> OUT_LOOP_TEST_R`[src]

Bit 4

`pub fn ahbm_rst(&self) -> AHBM_RST_R`[src]

Bit 3

`pub fn ahbm_fifo_rst(&self) -> AHBM_FIFO_RST_R`[src]

Bit 2

`pub fn out_rst(&self) -> OUT_RST_R`[src]

Bit 1

`pub fn in_rst(&self) -> IN_RST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _OUTFIFO_PUSH>>`[src]

`pub fn outfifo_push(&self) -> OUTFIFO_PUSH_R`[src]

Bit 16

`pub fn outfifo_wdata(&self) -> OUTFIFO_WDATA_R`[src]

Bits 0:8

`impl R<u32, Reg<u32, _INFIFO_POP>>`[src]

`pub fn infifo_pop(&self) -> INFIFO_POP_R`[src]

Bit 16

`pub fn infifo_rdata(&self) -> INFIFO_RDATA_R`[src]

Bits 0:11

`impl R<u32, Reg<u32, _LC_STATE0>>`[src]

`pub fn lc_state0(&self) -> LC_STATE0_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _LC_STATE1>>`[src]

`pub fn lc_state1(&self) -> LC_STATE1_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _LC_HUNG_CONF>>`[src]

`pub fn lc_fifo_timeout_ena(&self) -> LC_FIFO_TIMEOUT_ENA_R`[src]

Bit 11

`pub fn lc_fifo_timeout_shift(&self) -> LC_FIFO_TIMEOUT_SHIFT_R`[src]

Bits 8:10

`pub fn lc_fifo_timeout(&self) -> LC_FIFO_TIMEOUT_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _CVSD_CONF0>>`[src]

`pub fn cvsd_y_min(&self) -> CVSD_Y_MIN_R`[src]

Bits 16:31

`pub fn cvsd_y_max(&self) -> CVSD_Y_MAX_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _CVSD_CONF1>>`[src]

`pub fn cvsd_sigma_min(&self) -> CVSD_SIGMA_MIN_R`[src]

Bits 16:31

`pub fn cvsd_sigma_max(&self) -> CVSD_SIGMA_MAX_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _CVSD_CONF2>>`[src]

`pub fn cvsd_h(&self) -> CVSD_H_R`[src]

Bits 16:18

`pub fn cvsd_beta(&self) -> CVSD_BETA_R`[src]

Bits 6:15

`pub fn cvsd_j(&self) -> CVSD_J_R`[src]

Bits 3:5

`pub fn cvsd_k(&self) -> CVSD_K_R`[src]

Bits 0:2

`impl R<u32, Reg<u32, _PLC_CONF0>>`[src]

`pub fn n_min_err(&self) -> N_MIN_ERR_R`[src]

Bits 25:27

`pub fn pack_len_8k(&self) -> PACK_LEN_8K_R`[src]

Bits 20:24

`pub fn max_slide_sample(&self) -> MAX_SLIDE_SAMPLE_R`[src]

Bits 12:19

`pub fn shift_rate(&self) -> SHIFT_RATE_R`[src]

Bits 9:11

`pub fn n_err_seg(&self) -> N_ERR_SEG_R`[src]

Bits 6:8

`pub fn good_pack_max(&self) -> GOOD_PACK_MAX_R`[src]

Bits 0:5

`impl R<u32, Reg<u32, _PLC_CONF1>>`[src]

`pub fn slide_win_len(&self) -> SLIDE_WIN_LEN_R`[src]

Bits 24:31

`pub fn bad_ola_win2_para(&self) -> BAD_OLA_WIN2_PARA_R`[src]

Bits 16:23

`pub fn bad_ola_win2_para_shift(&self) -> BAD_OLA_WIN2_PARA_SHIFT_R`[src]

Bits 12:15

`pub fn bad_cef_atten_para_shift(&self) -> BAD_CEF_ATTEN_PARA_SHIFT_R`[src]

Bits 8:11

`pub fn bad_cef_atten_para(&self) -> BAD_CEF_ATTEN_PARA_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _PLC_CONF2>>`[src]

`pub fn min_period(&self) -> MIN_PERIOD_R`[src]

Bits 2:6

`pub fn cvsd_seg_mod(&self) -> CVSD_SEG_MOD_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _ESCO_CONF0>>`[src]

`pub fn plc2dma_en(&self) -> PLC2DMA_EN_R`[src]

Bit 12

`pub fn plc_en(&self) -> PLC_EN_R`[src]

Bit 11

`pub fn cvsd_dec_reset(&self) -> CVSD_DEC_RESET_R`[src]

Bit 10

`pub fn cvsd_dec_start(&self) -> CVSD_DEC_START_R`[src]

Bit 9

`pub fn esco_cvsd_inf_en(&self) -> ESCO_CVSD_INF_EN_R`[src]

Bit 8

`pub fn esco_cvsd_pack_len_8k(&self) -> ESCO_CVSD_PACK_LEN_8K_R`[src]

Bits 3:7

`pub fn esco_cvsd_dec_pack_err(&self) -> ESCO_CVSD_DEC_PACK_ERR_R`[src]

Bit 2

`pub fn esco_chan_mod(&self) -> ESCO_CHAN_MOD_R`[src]

Bit 1

`pub fn esco_en(&self) -> ESCO_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _SCO_CONF0>>`[src]

`pub fn cvsd_enc_reset(&self) -> CVSD_ENC_RESET_R`[src]

Bit 3

`pub fn cvsd_enc_start(&self) -> CVSD_ENC_START_R`[src]

Bit 2

`pub fn sco_no_i2s_en(&self) -> SCO_NO_I2S_EN_R`[src]

Bit 1

`pub fn sco_with_i2s_en(&self) -> SCO_WITH_I2S_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CONF1>>`[src]

`pub fn tx_zeros_rm_en(&self) -> TX_ZEROS_RM_EN_R`[src]

Bit 9

`pub fn tx_stop_en(&self) -> TX_STOP_EN_R`[src]

Bit 8

`pub fn rx_pcm_bypass(&self) -> RX_PCM_BYPASS_R`[src]

Bit 7

`pub fn rx_pcm_conf(&self) -> RX_PCM_CONF_R`[src]

Bits 4:6

`pub fn tx_pcm_bypass(&self) -> TX_PCM_BYPASS_R`[src]

Bit 3

`pub fn tx_pcm_conf(&self) -> TX_PCM_CONF_R`[src]

Bits 0:2

`impl R<u32, Reg<u32, _PD_CONF>>`[src]

`pub fn plc_mem_force_pu(&self) -> PLC_MEM_FORCE_PU_R`[src]

Bit 3

`pub fn plc_mem_force_pd(&self) -> PLC_MEM_FORCE_PD_R`[src]

Bit 2

`pub fn fifo_force_pu(&self) -> FIFO_FORCE_PU_R`[src]

Bit 1

`pub fn fifo_force_pd(&self) -> FIFO_FORCE_PD_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CONF2>>`[src]

`pub fn inter_valid_en(&self) -> INTER_VALID_EN_R`[src]

Bit 7

`pub fn ext_adc_start_en(&self) -> EXT_ADC_START_EN_R`[src]

Bit 6

`pub fn lcd_en(&self) -> LCD_EN_R`[src]

Bit 5

`pub fn data_enable(&self) -> DATA_ENABLE_R`[src]

Bit 4

`pub fn data_enable_test_en(&self) -> DATA_ENABLE_TEST_EN_R`[src]

Bit 3

`pub fn lcd_tx_sdx2_en(&self) -> LCD_TX_SDX2_EN_R`[src]

Bit 2

`pub fn lcd_tx_wrx2_en(&self) -> LCD_TX_WRX2_EN_R`[src]

Bit 1

`pub fn camera_en(&self) -> CAMERA_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CLKM_CONF>>`[src]

`pub fn clka_ena(&self) -> CLKA_ENA_R`[src]

Bit 21

`pub fn clk_en(&self) -> CLK_EN_R`[src]

Bit 20

`pub fn clkm_div_a(&self) -> CLKM_DIV_A_R`[src]

Bits 14:19

`pub fn clkm_div_b(&self) -> CLKM_DIV_B_R`[src]

Bits 8:13

`pub fn clkm_div_num(&self) -> CLKM_DIV_NUM_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _SAMPLE_RATE_CONF>>`[src]

`pub fn rx_bits_mod(&self) -> RX_BITS_MOD_R`[src]

Bits 18:23

`pub fn tx_bits_mod(&self) -> TX_BITS_MOD_R`[src]

Bits 12:17

`pub fn rx_bck_div_num(&self) -> RX_BCK_DIV_NUM_R`[src]

Bits 6:11

`pub fn tx_bck_div_num(&self) -> TX_BCK_DIV_NUM_R`[src]

Bits 0:5

`impl R<u32, Reg<u32, _PDM_CONF>>`[src]

`pub fn tx_pdm_hp_bypass(&self) -> TX_PDM_HP_BYPASS_R`[src]

Bit 25

`pub fn rx_pdm_sinc_dsr_16_en(&self) -> RX_PDM_SINC_DSR_16_EN_R`[src]

Bit 24

`pub fn tx_pdm_sigmadelta_in_shift(&self) -> TX_PDM_SIGMADELTA_IN_SHIFT_R`[src]

Bits 22:23

`pub fn tx_pdm_sinc_in_shift(&self) -> TX_PDM_SINC_IN_SHIFT_R`[src]

Bits 20:21

`pub fn tx_pdm_lp_in_shift(&self) -> TX_PDM_LP_IN_SHIFT_R`[src]

Bits 18:19

`pub fn tx_pdm_hp_in_shift(&self) -> TX_PDM_HP_IN_SHIFT_R`[src]

Bits 16:17

`pub fn tx_pdm_prescale(&self) -> TX_PDM_PRESCALE_R`[src]

Bits 8:15

`pub fn tx_pdm_sinc_osr2(&self) -> TX_PDM_SINC_OSR2_R`[src]

Bits 4:7

`pub fn pdm2pcm_conv_en(&self) -> PDM2PCM_CONV_EN_R`[src]

Bit 3

`pub fn pcm2pdm_conv_en(&self) -> PCM2PDM_CONV_EN_R`[src]

Bit 2

`pub fn rx_pdm_en(&self) -> RX_PDM_EN_R`[src]

Bit 1

`pub fn tx_pdm_en(&self) -> TX_PDM_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _PDM_FREQ_CONF>>`[src]

`pub fn tx_pdm_fp(&self) -> TX_PDM_FP_R`[src]

Bits 10:19

`pub fn tx_pdm_fs(&self) -> TX_PDM_FS_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _STATE>>`[src]

`pub fn rx_fifo_reset_back(&self) -> RX_FIFO_RESET_BACK_R`[src]

Bit 2

`pub fn tx_fifo_reset_back(&self) -> TX_FIFO_RESET_BACK_R`[src]

Bit 1

`pub fn tx_idle(&self) -> TX_IDLE_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DATE>>`[src]

`pub fn i2sdate(&self) -> I2SDATE_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _SYSCLK_CONF>>`[src]

`pub fn quick_clk_chng(&self) -> QUICK_CLK_CHNG_R`[src]

Bit 13

`pub fn rst_tick_cnt(&self) -> RST_TICK_CNT_R`[src]

Bit 12

`pub fn clk_en(&self) -> CLK_EN_R`[src]

Bit 11

`pub fn clk_320m_en(&self) -> CLK_320M_EN_R`[src]

Bit 10

`pub fn pre_div_cnt(&self) -> PRE_DIV_CNT_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _XTAL_TICK_CONF>>`[src]

`pub fn xtal_tick_num(&self) -> XTAL_TICK_NUM_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _PLL_TICK_CONF>>`[src]

`pub fn pll_tick_num(&self) -> PLL_TICK_NUM_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _CK8M_TICK_CONF>>`[src]

`pub fn ck8m_tick_num(&self) -> CK8M_TICK_NUM_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _APB_SARADC_CTRL>>`[src]

`pub fn saradc_data_to_i2s(&self) -> SARADC_DATA_TO_I2S_R`[src]

Bit 26

`pub fn saradc_data_sar_sel(&self) -> SARADC_DATA_SAR_SEL_R`[src]

Bit 25

`pub fn saradc_sar2_patt_p_clear(&self) -> SARADC_SAR2_PATT_P_CLEAR_R`[src]

Bit 24

`pub fn saradc_sar1_patt_p_clear(&self) -> SARADC_SAR1_PATT_P_CLEAR_R`[src]

Bit 23

`pub fn saradc_sar2_patt_len(&self) -> SARADC_SAR2_PATT_LEN_R`[src]

Bits 19:22

`pub fn saradc_sar1_patt_len(&self) -> SARADC_SAR1_PATT_LEN_R`[src]

Bits 15:18

`pub fn saradc_sar_clk_div(&self) -> SARADC_SAR_CLK_DIV_R`[src]

Bits 7:14

`pub fn saradc_sar_clk_gated(&self) -> SARADC_SAR_CLK_GATED_R`[src]

Bit 6

`pub fn saradc_sar_sel(&self) -> SARADC_SAR_SEL_R`[src]

Bit 5

`pub fn saradc_work_mode(&self) -> SARADC_WORK_MODE_R`[src]

Bits 3:4

`pub fn saradc_sar2_mux(&self) -> SARADC_SAR2_MUX_R`[src]

Bit 2

`pub fn saradc_start(&self) -> SARADC_START_R`[src]

Bit 1

`pub fn saradc_start_force(&self) -> SARADC_START_FORCE_R`[src]

Bit 0

`impl R<u32, Reg<u32, _APB_SARADC_CTRL2>>`[src]

`pub fn saradc_sar2_inv(&self) -> SARADC_SAR2_INV_R`[src]

Bit 10

`pub fn saradc_sar1_inv(&self) -> SARADC_SAR1_INV_R`[src]

Bit 9

`pub fn saradc_max_meas_num(&self) -> SARADC_MAX_MEAS_NUM_R`[src]

Bits 1:8

`pub fn saradc_meas_num_limit(&self) -> SARADC_MEAS_NUM_LIMIT_R`[src]

Bit 0

`impl R<u32, Reg<u32, _APB_SARADC_FSM>>`[src]

`pub fn saradc_sample_cycle(&self) -> SARADC_SAMPLE_CYCLE_R`[src]

Bits 24:31

`pub fn saradc_start_wait(&self) -> SARADC_START_WAIT_R`[src]

Bits 16:23

`pub fn saradc_standby_wait(&self) -> SARADC_STANDBY_WAIT_R`[src]

`pub fn rst_tick_cnt(&self) -> RST_TICK_CNT_R`[src]

Bit 12

`pub fn clk_en(&self) -> CLK_EN_R`[src]

Bit 11

`pub fn clk_320m_en(&self) -> CLK_320M_EN_R`[src]

Bit 10

`pub fn pre_div_cnt(&self) -> PRE_DIV_CNT_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _XTAL_TICK_CONF>>`[src]

`pub fn xtal_tick_num(&self) -> XTAL_TICK_NUM_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _PLL_TICK_CONF>>`[src]

`pub fn pll_tick_num(&self) -> PLL_TICK_NUM_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _CK8M_TICK_CONF>>`[src]

`pub fn ck8m_tick_num(&self) -> CK8M_TICK_NUM_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _SARADC_CTRL>>`[src]

`pub fn saradc_data_to_i2s(&self) -> SARADC_DATA_TO_I2S_R`[src]

Bit 26

`pub fn saradc_data_sar_sel(&self) -> SARADC_DATA_SAR_SEL_R`[src]

Bit 25

`pub fn saradc_sar2_patt_p_clear(&self) -> SARADC_SAR2_PATT_P_CLEAR_R`[src]

Bit 24

`pub fn saradc_sar1_patt_p_clear(&self) -> SARADC_SAR1_PATT_P_CLEAR_R`[src]

Bit 23

`pub fn saradc_sar2_patt_len(&self) -> SARADC_SAR2_PATT_LEN_R`[src]

Bits 19:22

`pub fn saradc_sar1_patt_len(&self) -> SARADC_SAR1_PATT_LEN_R`[src]

Bits 15:18

`pub fn saradc_sar_clk_div(&self) -> SARADC_SAR_CLK_DIV_R`[src]

Bits 7:14

`pub fn saradc_sar_clk_gated(&self) -> SARADC_SAR_CLK_GATED_R`[src]

Bit 6

`pub fn saradc_sar_sel(&self) -> SARADC_SAR_SEL_R`[src]

Bit 5

`pub fn saradc_work_mode(&self) -> SARADC_WORK_MODE_R`[src]

Bits 3:4

`pub fn saradc_sar2_mux(&self) -> SARADC_SAR2_MUX_R`[src]

Bit 2

`pub fn saradc_start(&self) -> SARADC_START_R`[src]

Bit 1

`pub fn saradc_start_force(&self) -> SARADC_START_FORCE_R`[src]

Bit 0

`impl R<u32, Reg<u32, _SARADC_CTRL2>>`[src]

`pub fn saradc_sar2_inv(&self) -> SARADC_SAR2_INV_R`[src]

Bit 10

`pub fn saradc_sar1_inv(&self) -> SARADC_SAR1_INV_R`[src]

Bit 9

`pub fn saradc_max_meas_num(&self) -> SARADC_MAX_MEAS_NUM_R`[src]

Bits 1:8

`pub fn saradc_meas_num_limit(&self) -> SARADC_MEAS_NUM_LIMIT_R`[src]

Bit 0

`impl R<u32, Reg<u32, _SARADC_FSM>>`[src]

`pub fn saradc_sample_cycle(&self) -> SARADC_SAMPLE_CYCLE_R`[src]

Bits 24:31

`pub fn saradc_start_wait(&self) -> SARADC_START_WAIT_R`[src]

Bits 16:23

`pub fn saradc_standby_wait(&self) -> SARADC_STANDBY_WAIT_R`[src]

`impl R<u32, Reg<u32, _CTRL>>`[src]

`pub fn rx_lsb_first(&self) -> RX_LSB_FIRST_R`[src]

Bit 7

`pub fn tx_lsb_first(&self) -> TX_LSB_FIRST_R`[src]

Bit 6

`pub fn trans_start(&self) -> TRANS_START_R`[src]

Bit 5

`pub fn ms_mode(&self) -> MS_MODE_R`[src]

Bit 4

`pub fn scl_force_out(&self) -> SCL_FORCE_OUT_R`[src]

Bit 1

`pub fn sda_force_out(&self) -> SDA_FORCE_OUT_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DEBUG_STATUS>>`[src]

`pub fn scl_state(&self) -> SCL_STATE_R`[src]

Bits 28:30

`pub fn main_state(&self) -> MAIN_STATE_R`[src]

Bits 25:27

`pub fn byte_trans(&self) -> BYTE_TRANS_R`[src]

Bit 6

`pub fn slave_addr_match(&self) -> SLAVE_ADDR_MATCH_R`[src]

Bit 5

`pub fn bus_busy(&self) -> BUS_BUSY_R`[src]

Bit 4

`pub fn arb_lost(&self) -> ARB_LOST_R`[src]

Bit 3

`pub fn timed_out(&self) -> TIMED_OUT_R`[src]

Bit 2

`pub fn slave_rw(&self) -> SLAVE_RW_R`[src]

Bit 1

`pub fn ack_val(&self) -> ACK_VAL_R`[src]

Bit 0

`impl R<u32, Reg<u32, _TIMEOUT>>`[src]

`pub fn timeout(&self) -> TIMEOUT_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _SLAVE_ADDR>>`[src]

`pub fn slave_addr_10bit(&self) -> SLAVE_ADDR_10BIT_R`[src]

Bit 31

`pub fn slave_addr(&self) -> SLAVE_ADDR_R`[src]

Bits 0:14

`impl R<u32, Reg<u32, _INT_RAW>>`[src]

`pub fn time_out_int_raw(&self) -> TIME_OUT_INT_RAW_R`[src]

Bit 7

`pub fn trans_complete_int_raw(&self) -> TRANS_COMPLETE_INT_RAW_R`[src]

Bit 6

`pub fn master_trans_complete_int_raw(&self) -> MASTER_TRANS_COMPLETE_INT_RAW_R`[src]

Bit 5

`pub fn arbitration_lost_int_raw(&self) -> ARBITRATION_LOST_INT_RAW_R`[src]

Bit 4

`pub fn slave_trans_complete_int_raw(&self) -> SLAVE_TRANS_COMPLETE_INT_RAW_R`[src]

Bit 3

`impl R<u32, Reg<u32, _INT_CLR>>`[src]

`pub fn time_out_int_clr(&self) -> TIME_OUT_INT_CLR_R`[src]

Bit 8

`pub fn trans_complete_int_clr(&self) -> TRANS_COMPLETE_INT_CLR_R`[src]

Bit 7

`pub fn master_trans_complete_int_clr(&self) -> MASTER_TRANS_COMPLETE_INT_CLR_R`[src]

Bit 6

`pub fn arbitration_lost_int_clr(&self) -> ARBITRATION_LOST_INT_CLR_R`[src]

`pub fn rs485_clash_int_raw(&self) -> RS485_CLASH_INT_RAW_R`[src]

Bit 17

`pub fn rs485_frm_err_int_raw(&self) -> RS485_FRM_ERR_INT_RAW_R`[src]

Bit 16

`pub fn rs485_parity_err_int_raw(&self) -> RS485_PARITY_ERR_INT_RAW_R`[src]

Bit 15

`pub fn tx_done_int_raw(&self) -> TX_DONE_INT_RAW_R`[src]

Bit 14

`pub fn tx_brk_idle_done_int_raw(&self) -> TX_BRK_IDLE_DONE_INT_RAW_R`[src]

Bit 13

`pub fn tx_brk_done_int_raw(&self) -> TX_BRK_DONE_INT_RAW_R`[src]

Bit 12

`pub fn glitch_det_int_raw(&self) -> GLITCH_DET_INT_RAW_R`[src]

Bit 11

`pub fn sw_xoff_int_raw(&self) -> SW_XOFF_INT_RAW_R`[src]

Bit 10

`pub fn sw_xon_int_raw(&self) -> SW_XON_INT_RAW_R`[src]

Bit 9

`pub fn rxfifo_tout_int_raw(&self) -> RXFIFO_TOUT_INT_RAW_R`[src]

Bit 8

`pub fn brk_det_int_raw(&self) -> BRK_DET_INT_RAW_R`[src]

Bit 7

`pub fn cts_chg_int_raw(&self) -> CTS_CHG_INT_RAW_R`[src]

Bit 6

`pub fn dsr_chg_int_raw(&self) -> DSR_CHG_INT_RAW_R`[src]

Bit 5

`pub fn rxfifo_ovf_int_raw(&self) -> RXFIFO_OVF_INT_RAW_R`[src]

Bit 4

`pub fn frm_err_int_raw(&self) -> FRM_ERR_INT_RAW_R`[src]

Bit 3

`pub fn parity_err_int_raw(&self) -> PARITY_ERR_INT_RAW_R`[src]

Bit 2

`pub fn txfifo_empty_int_raw(&self) -> TXFIFO_EMPTY_INT_RAW_R`[src]

Bit 1

`pub fn rxfifo_full_int_raw(&self) -> RXFIFO_FULL_INT_RAW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_ST>>`[src]

`pub fn at_cmd_char_det_int_st(&self) -> AT_CMD_CHAR_DET_INT_ST_R`[src]

Bit 18

`pub fn rs485_clash_int_st(&self) -> RS485_CLASH_INT_ST_R`[src]

Bit 17

`pub fn rs485_frm_err_int_st(&self) -> RS485_FRM_ERR_INT_ST_R`[src]

Bit 16

`pub fn rs485_parity_err_int_st(&self) -> RS485_PARITY_ERR_INT_ST_R`[src]

Bit 15

`pub fn tx_done_int_st(&self) -> TX_DONE_INT_ST_R`[src]

Bit 14

`pub fn tx_brk_idle_done_int_st(&self) -> TX_BRK_IDLE_DONE_INT_ST_R`[src]

Bit 13

`pub fn tx_brk_done_int_st(&self) -> TX_BRK_DONE_INT_ST_R`[src]

Bit 12

`pub fn glitch_det_int_st(&self) -> GLITCH_DET_INT_ST_R`[src]

Bit 11

`pub fn sw_xoff_int_st(&self) -> SW_XOFF_INT_ST_R`[src]

Bit 10

`pub fn sw_xon_int_st(&self) -> SW_XON_INT_ST_R`[src]

Bit 9

`pub fn rxfifo_tout_int_st(&self) -> RXFIFO_TOUT_INT_ST_R`[src]

Bit 8

`pub fn brk_det_int_st(&self) -> BRK_DET_INT_ST_R`[src]

Bit 7

`pub fn cts_chg_int_st(&self) -> CTS_CHG_INT_ST_R`[src]

Bit 6

`pub fn dsr_chg_int_st(&self) -> DSR_CHG_INT_ST_R`[src]

Bit 5

`pub fn rxfifo_ovf_int_st(&self) -> RXFIFO_OVF_INT_ST_R`[src]

Bit 4

`pub fn frm_err_int_st(&self) -> FRM_ERR_INT_ST_R`[src]

Bit 3

`pub fn parity_err_int_st(&self) -> PARITY_ERR_INT_ST_R`[src]

Bit 2

`pub fn txfifo_empty_int_st(&self) -> TXFIFO_EMPTY_INT_ST_R`[src]

Bit 1

`pub fn rxfifo_full_int_st(&self) -> RXFIFO_FULL_INT_ST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_ENA>>`[src]

`pub fn at_cmd_char_det_int_ena(&self) -> AT_CMD_CHAR_DET_INT_ENA_R`[src]

Bit 18

`pub fn rs485_clash_int_ena(&self) -> RS485_CLASH_INT_ENA_R`[src]

Bit 17

`pub fn rs485_frm_err_int_ena(&self) -> RS485_FRM_ERR_INT_ENA_R`[src]

Bit 16

`pub fn rs485_parity_err_int_ena(&self) -> RS485_PARITY_ERR_INT_ENA_R`[src]

Bit 15

`pub fn tx_done_int_ena(&self) -> TX_DONE_INT_ENA_R`[src]

Bit 14

`pub fn tx_brk_idle_done_int_ena(&self) -> TX_BRK_IDLE_DONE_INT_ENA_R`[src]

Bit 13

`pub fn tx_brk_done_int_ena(&self) -> TX_BRK_DONE_INT_ENA_R`[src]

Bit 12

`pub fn glitch_det_int_ena(&self) -> GLITCH_DET_INT_ENA_R`[src]

Bit 11

`pub fn sw_xoff_int_ena(&self) -> SW_XOFF_INT_ENA_R`[src]

Bit 10

`pub fn sw_xon_int_ena(&self) -> SW_XON_INT_ENA_R`[src]

Bit 9

`pub fn rxfifo_tout_int_ena(&self) -> RXFIFO_TOUT_INT_ENA_R`[src]

Bit 8

`pub fn brk_det_int_ena(&self) -> BRK_DET_INT_ENA_R`[src]

Bit 7

`pub fn cts_chg_int_ena(&self) -> CTS_CHG_INT_ENA_R`[src]

Bit 6

`pub fn dsr_chg_int_ena(&self) -> DSR_CHG_INT_ENA_R`[src]

Bit 5

`pub fn rxfifo_ovf_int_ena(&self) -> RXFIFO_OVF_INT_ENA_R`[src]

Bit 4

`pub fn frm_err_int_ena(&self) -> FRM_ERR_INT_ENA_R`[src]

Bit 3

`pub fn parity_err_int_ena(&self) -> PARITY_ERR_INT_ENA_R`[src]

Bit 2

`pub fn txfifo_empty_int_ena(&self) -> TXFIFO_EMPTY_INT_ENA_R`[src]

Bit 1

`pub fn rxfifo_full_int_ena(&self) -> RXFIFO_FULL_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_CLR>>`[src]

`pub fn at_cmd_char_det_int_clr(&self) -> AT_CMD_CHAR_DET_INT_CLR_R`[src]

Bit 18

`pub fn rs485_clash_int_clr(&self) -> RS485_CLASH_INT_CLR_R`[src]

Bit 17

`pub fn rs485_frm_err_int_clr(&self) -> RS485_FRM_ERR_INT_CLR_R`[src]

Bit 16

`pub fn rs485_parity_err_int_clr(&self) -> RS485_PARITY_ERR_INT_CLR_R`[src]

Bit 15

`pub fn tx_done_int_clr(&self) -> TX_DONE_INT_CLR_R`[src]

Bit 14

`pub fn tx_brk_idle_done_int_clr(&self) -> TX_BRK_IDLE_DONE_INT_CLR_R`[src]

Bit 13

`pub fn tx_brk_done_int_clr(&self) -> TX_BRK_DONE_INT_CLR_R`[src]

Bit 12

`pub fn glitch_det_int_clr(&self) -> GLITCH_DET_INT_CLR_R`[src]

Bit 11

`pub fn sw_xoff_int_clr(&self) -> SW_XOFF_INT_CLR_R`[src]

Bit 10

`pub fn sw_xon_int_clr(&self) -> SW_XON_INT_CLR_R`[src]

Bit 9

`pub fn rxfifo_tout_int_clr(&self) -> RXFIFO_TOUT_INT_CLR_R`[src]

Bit 8

`pub fn brk_det_int_clr(&self) -> BRK_DET_INT_CLR_R`[src]

Bit 7

`pub fn cts_chg_int_clr(&self) -> CTS_CHG_INT_CLR_R`[src]

Bit 6

`pub fn dsr_chg_int_clr(&self) -> DSR_CHG_INT_CLR_R`[src]

Bit 5

`pub fn rxfifo_ovf_int_clr(&self) -> RXFIFO_OVF_INT_CLR_R`[src]

Bit 4

`pub fn frm_err_int_clr(&self) -> FRM_ERR_INT_CLR_R`[src]

Bit 3

`pub fn parity_err_int_clr(&self) -> PARITY_ERR_INT_CLR_R`[src]

Bit 2

`pub fn txfifo_empty_int_clr(&self) -> TXFIFO_EMPTY_INT_CLR_R`[src]

Bit 1

`pub fn rxfifo_full_int_clr(&self) -> RXFIFO_FULL_INT_CLR_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CLKDIV>>`[src]

`pub fn clkdiv_frag(&self) -> CLKDIV_FRAG_R`[src]

Bits 20:23

`pub fn clkdiv(&self) -> CLKDIV_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _AUTOBAUD>>`[src]

`pub fn glitch_filt(&self) -> GLITCH_FILT_R`[src]

Bits 8:15

`pub fn autobaud_en(&self) -> AUTOBAUD_EN_R`[src]

Bit 0

`impl R<u8, ST_UTX_OUT_A>`[src]

`pub fn variant(&self) -> Variant<u8, ST_UTX_OUT_A>`[src]

Get enumerated values variant

`pub fn is_tx_idle(&self) -> bool`[src]

Checks if the value of the field is TX_IDLE

`pub fn is_tx_strt(&self) -> bool`[src]

Checks if the value of the field is TX_STRT

`pub fn is_tx_dat0(&self) -> bool`[src]

Checks if the value of the field is TX_DAT0

`pub fn is_tx_dat1(&self) -> bool`[src]

Checks if the value of the field is TX_DAT1

`pub fn is_tx_dat2(&self) -> bool`[src]

Checks if the value of the field is TX_DAT2

`pub fn is_tx_dat3(&self) -> bool`[src]

Checks if the value of the field is TX_DAT3

`pub fn is_tx_dat4(&self) -> bool`[src]

Checks if the value of the field is TX_DAT4

`pub fn is_tx_dat5(&self) -> bool`[src]

Checks if the value of the field is TX_DAT5

`pub fn is_tx_dat6(&self) -> bool`[src]

Checks if the value of the field is TX_DAT6

`pub fn is_tx_dat7(&self) -> bool`[src]

Checks if the value of the field is TX_DAT7

`pub fn is_tx_prty(&self) -> bool`[src]

Checks if the value of the field is TX_PRTY

`pub fn is_tx_stp1(&self) -> bool`[src]

Checks if the value of the field is TX_STP1

`pub fn is_tx_stp2(&self) -> bool`[src]

Checks if the value of the field is TX_STP2

`pub fn is_tx_dl1(&self) -> bool`[src]

Checks if the value of the field is TX_DL1

`impl R<u8, ST_URX_OUT_A>`[src]

`pub fn variant(&self) -> Variant<u8, ST_URX_OUT_A>`[src]

Get enumerated values variant

`pub fn is_rx_idle(&self) -> bool`[src]

Checks if the value of the field is RX_IDLE

`pub fn is_rx_strt(&self) -> bool`[src]

Checks if the value of the field is RX_STRT

`pub fn is_rx_dat0(&self) -> bool`[src]

Checks if the value of the field is RX_DAT0

`pub fn is_rx_dat1(&self) -> bool`[src]

Checks if the value of the field is RX_DAT1

`pub fn is_rx_dat2(&self) -> bool`[src]

Checks if the value of the field is RX_DAT2

`pub fn is_rx_dat3(&self) -> bool`[src]

Checks if the value of the field is RX_DAT3

`pub fn is_rx_dat4(&self) -> bool`[src]

Checks if the value of the field is RX_DAT4

`pub fn is_rx_dat5(&self) -> bool`[src]

Checks if the value of the field is RX_DAT5

`pub fn is_rx_dat6(&self) -> bool`[src]

Checks if the value of the field is RX_DAT6

`pub fn is_rx_dat7(&self) -> bool`[src]

Checks if the value of the field is RX_DAT7

`pub fn is_rx_prty(&self) -> bool`[src]

Checks if the value of the field is RX_PRTY

`pub fn is_rx_stp1(&self) -> bool`[src]

Checks if the value of the field is RX_STP1

`pub fn is_rx_stp2(&self) -> bool`[src]

Checks if the value of the field is RX_STP2

`pub fn is_rx_dl1(&self) -> bool`[src]

Checks if the value of the field is RX_DL1

`impl R<u32, Reg<u32, _STATUS>>`[src]

`pub fn txd(&self) -> TXD_R`[src]

Bit 31

`pub fn rtsn(&self) -> RTSN_R`[src]

Bit 30

`pub fn dtrn(&self) -> DTRN_R`[src]

Bit 29

`pub fn st_utx_out(&self) -> ST_UTX_OUT_R`[src]

Bits 24:27

`pub fn txfifo_cnt(&self) -> TXFIFO_CNT_R`[src]

Bits 16:23

`pub fn rxd(&self) -> RXD_R`[src]

Bit 15

`pub fn ctsn(&self) -> CTSN_R`[src]

Bit 14

`pub fn dsrn(&self) -> DSRN_R`[src]

Bit 13

`pub fn st_urx_out(&self) -> ST_URX_OUT_R`[src]

Bits 8:11

`pub fn rxfifo_cnt(&self) -> RXFIFO_CNT_R`[src]

Bits 0:7

`impl R<u8, STOP_BIT_NUM_A>`[src]

`pub fn variant(&self) -> Variant<u8, STOP_BIT_NUM_A>`[src]

Get enumerated values variant

`pub fn is_stop_bits_1(&self) -> bool`[src]

Checks if the value of the field is STOP_BITS_1

`pub fn is_stop_bits_1p5(&self) -> bool`[src]

Checks if the value of the field is STOP_BITS_1P5

`pub fn is_stop_bits_2(&self) -> bool`[src]

Checks if the value of the field is STOP_BITS_2

`impl R<u8, BIT_NUM_A>`[src]

`pub fn variant(&self) -> BIT_NUM_A`[src]

Get enumerated values variant

`pub fn is_data_bits_5(&self) -> bool`[src]

Checks if the value of the field is DATA_BITS_5

`pub fn is_data_bits_6(&self) -> bool`[src]

Checks if the value of the field is DATA_BITS_6

`pub fn is_data_bits_7(&self) -> bool`[src]

Checks if the value of the field is DATA_BITS_7

`pub fn is_data_bits_8(&self) -> bool`[src]

Checks if the value of the field is DATA_BITS_8

`impl R<u32, Reg<u32, _CONF0>>`[src]

`pub fn tick_ref_always_on(&self) -> TICK_REF_ALWAYS_ON_R`[src]

Bit 27

`pub fn err_wr_mask(&self) -> ERR_WR_MASK_R`[src]

Bit 26

`pub fn clk_en(&self) -> CLK_EN_R`[src]

Bit 25

`pub fn dtr_inv(&self) -> DTR_INV_R`[src]

Bit 24

`pub fn rts_inv(&self) -> RTS_INV_R`[src]

Bit 23

`pub fn txd_inv(&self) -> TXD_INV_R`[src]

Bit 22

`pub fn dsr_inv(&self) -> DSR_INV_R`[src]

Bit 21

`pub fn cts_inv(&self) -> CTS_INV_R`[src]

Bit 20

`pub fn rxd_inv(&self) -> RXD_INV_R`[src]

Bit 19

`pub fn txfifo_rst(&self) -> TXFIFO_RST_R`[src]

Bit 18

`pub fn rxfifo_rst(&self) -> RXFIFO_RST_R`[src]

Bit 17

`pub fn irda_en(&self) -> IRDA_EN_R`[src]

Bit 16

`pub fn tx_flow_en(&self) -> TX_FLOW_EN_R`[src]

Bit 15

`pub fn loopback(&self) -> LOOPBACK_R`[src]

Bit 14

`pub fn irda_rx_inv(&self) -> IRDA_RX_INV_R`[src]

Bit 13

`pub fn irda_tx_inv(&self) -> IRDA_TX_INV_R`[src]

Bit 12

`pub fn irda_wctl(&self) -> IRDA_WCTL_R`[src]

Bit 11

`pub fn irda_tx_en(&self) -> IRDA_TX_EN_R`[src]

Bit 10

`pub fn irda_dplx(&self) -> IRDA_DPLX_R`[src]

Bit 9

`pub fn txd_brk(&self) -> TXD_BRK_R`[src]

Bit 8

`pub fn sw_dtr(&self) -> SW_DTR_R`[src]

Bit 7

`pub fn sw_rts(&self) -> SW_RTS_R`[src]

Bit 6

`pub fn stop_bit_num(&self) -> STOP_BIT_NUM_R`[src]

Bits 4:5

`pub fn bit_num(&self) -> BIT_NUM_R`[src]

Bits 2:3

`pub fn parity_en(&self) -> PARITY_EN_R`[src]

Bit 1

`pub fn parity(&self) -> PARITY_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CONF1>>`[src]

`pub fn rx_tout_en(&self) -> RX_TOUT_EN_R`[src]

Bit 31

`pub fn rx_tout_thrhd(&self) -> RX_TOUT_THRHD_R`[src]

Bits 24:30

`pub fn rx_flow_en(&self) -> RX_FLOW_EN_R`[src]

Bit 23

`pub fn rx_flow_thrhd(&self) -> RX_FLOW_THRHD_R`[src]

Bits 16:22

`pub fn txfifo_empty_thrhd(&self) -> TXFIFO_EMPTY_THRHD_R`[src]

Bits 8:14

`pub fn rxfifo_full_thrhd(&self) -> RXFIFO_FULL_THRHD_R`[src]

Bits 0:6

`impl R<u32, Reg<u32, _LOWPULSE>>`[src]

`pub fn lowpulse_min_cnt(&self) -> LOWPULSE_MIN_CNT_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HIGHPULSE>>`[src]

`pub fn highpulse_min_cnt(&self) -> HIGHPULSE_MIN_CNT_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _RXD_CNT>>`[src]

`pub fn rxd_edge_cnt(&self) -> RXD_EDGE_CNT_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _FLOW_CONF>>`[src]

`pub fn send_xoff(&self) -> SEND_XOFF_R`[src]

Bit 5

`pub fn send_xon(&self) -> SEND_XON_R`[src]

Bit 4

`pub fn force_xoff(&self) -> FORCE_XOFF_R`[src]

Bit 3

`pub fn force_xon(&self) -> FORCE_XON_R`[src]

Bit 2

`pub fn xonoff_del(&self) -> XONOFF_DEL_R`[src]

Bit 1

`pub fn sw_flow_con_en(&self) -> SW_FLOW_CON_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _SLEEP_CONF>>`[src]

`pub fn active_threshold(&self) -> ACTIVE_THRESHOLD_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _SWFC_CONF>>`[src]

`pub fn xoff_char(&self) -> XOFF_CHAR_R`[src]

Bits 24:31

`pub fn xon_char(&self) -> XON_CHAR_R`[src]

Bits 16:23

`pub fn xoff_threshold(&self) -> XOFF_THRESHOLD_R`[src]

Bits 8:15

`pub fn xon_threshold(&self) -> XON_THRESHOLD_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _IDLE_CONF>>`[src]

`pub fn tx_brk_num(&self) -> TX_BRK_NUM_R`[src]

Bits 20:27

`pub fn tx_idle_num(&self) -> TX_IDLE_NUM_R`[src]

Bits 10:19

`pub fn rx_idle_thrhd(&self) -> RX_IDLE_THRHD_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _RS485_CONF>>`[src]

`pub fn rs485_tx_dly_num(&self) -> RS485_TX_DLY_NUM_R`[src]

Bits 6:9

`pub fn rs485_rx_dly_num(&self) -> RS485_RX_DLY_NUM_R`[src]

Bit 5

`pub fn rs485rxby_tx_en(&self) -> RS485RXBY_TX_EN_R`[src]

Bit 4

`pub fn rs485tx_rx_en(&self) -> RS485TX_RX_EN_R`[src]

Bit 3

`pub fn dl1_en(&self) -> DL1_EN_R`[src]

Bit 2

`pub fn dl0_en(&self) -> DL0_EN_R`[src]

Bit 1

`pub fn rs485_en(&self) -> RS485_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _AT_CMD_PRECNT>>`[src]

`pub fn pre_idle_num(&self) -> PRE_IDLE_NUM_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _AT_CMD_POSTCNT>>`[src]

`pub fn post_idle_num(&self) -> POST_IDLE_NUM_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _AT_CMD_GAPTOUT>>`[src]

`pub fn rx_gap_tout(&self) -> RX_GAP_TOUT_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _AT_CMD_CHAR>>`[src]

`pub fn char_num(&self) -> CHAR_NUM_R`[src]

Bits 8:15

`pub fn at_cmd_char(&self) -> AT_CMD_CHAR_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _MEM_CONF>>`[src]

`pub fn tx_mem_empty_thrhd(&self) -> TX_MEM_EMPTY_THRHD_R`[src]

Bits 28:30

`pub fn rx_mem_full_thrhd(&self) -> RX_MEM_FULL_THRHD_R`[src]

Bits 25:27

`pub fn xoff_threshold_h2(&self) -> XOFF_THRESHOLD_H2_R`[src]

Bits 23:24

`pub fn xon_threshold_h2(&self) -> XON_THRESHOLD_H2_R`[src]

Bits 21:22

`pub fn rx_tout_thrhd_h3(&self) -> RX_TOUT_THRHD_H3_R`[src]

Bits 18:20

`pub fn rx_flow_thrhd_h3(&self) -> RX_FLOW_THRHD_H3_R`[src]

Bits 15:17

`pub fn tx_size(&self) -> TX_SIZE_R`[src]

Bits 7:10

`pub fn rx_size(&self) -> RX_SIZE_R`[src]

Bits 3:6

`pub fn mem_pd(&self) -> MEM_PD_R`[src]

Bit 0

`impl R<u32, Reg<u32, _MEM_TX_STATUS>>`[src]

`pub fn mem_tx_status(&self) -> MEM_TX_STATUS_R`[src]

Bits 0:23

`impl R<u32, Reg<u32, _MEM_RX_STATUS>>`[src]

`pub fn mem_rx_status(&self) -> MEM_RX_STATUS_R`[src]

Bits 0:23

`pub fn mem_rx_rd_addr(&self) -> MEM_RX_RD_ADDR_R`[src]

Bits 2:12

`pub fn mem_rx_wr_addr(&self) -> MEM_RX_WR_ADDR_R`[src]

Bits 13:23

`impl R<u32, Reg<u32, _MEM_CNT_STATUS>>`[src]

`pub fn tx_mem_cnt(&self) -> TX_MEM_CNT_R`[src]

Bits 3:5

`pub fn rx_mem_cnt(&self) -> RX_MEM_CNT_R`[src]

Bits 0:2

`impl R<u32, Reg<u32, _POSPULSE>>`[src]

`pub fn posedge_min_cnt(&self) -> POSEDGE_MIN_CNT_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _NEGPULSE>>`[src]

`pub fn negedge_min_cnt(&self) -> NEGEDGE_MIN_CNT_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _DATE>>`[src]

`pub fn date(&self) -> DATE_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _ID>>`[src]

`pub fn id(&self) -> ID_R`[src]

Bits 0:31

`impl R<u8, Reg<u8, _RX_FIFO>>`[src]

`pub fn data(&self) -> DATA_R`[src]

Bits 0:7 - TX FIFO Data

`impl R<u32, Reg<u32, _HSCH0_CONF0>>`[src]

`pub fn clk_en(&self) -> CLK_EN_R`[src]

Bit 31

`pub fn idle_lv_hsch0(&self) -> IDLE_LV_HSCH0_R`[src]

Bit 3

`pub fn sig_out_en_hsch0(&self) -> SIG_OUT_EN_HSCH0_R`[src]

Bit 2

`pub fn timer_sel_hsch0(&self) -> TIMER_SEL_HSCH0_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _HSCH0_HPOINT>>`[src]

`pub fn hpoint_hsch0(&self) -> HPOINT_HSCH0_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HSCH0_DUTY>>`[src]

`pub fn duty_hsch0(&self) -> DUTY_HSCH0_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSCH0_CONF1>>`[src]

`pub fn duty_start_hsch0(&self) -> DUTY_START_HSCH0_R`[src]

Bit 31

`pub fn duty_inc_hsch0(&self) -> DUTY_INC_HSCH0_R`[src]

Bit 30

`pub fn duty_num_hsch0(&self) -> DUTY_NUM_HSCH0_R`[src]

Bits 20:29

`pub fn duty_cycle_hsch0(&self) -> DUTY_CYCLE_HSCH0_R`[src]

Bits 10:19

`pub fn duty_scale_hsch0(&self) -> DUTY_SCALE_HSCH0_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _HSCH0_DUTY_R>>`[src]

`pub fn duty_hsch0(&self) -> DUTY_HSCH0_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSCH1_CONF0>>`[src]

`pub fn idle_lv_hsch1(&self) -> IDLE_LV_HSCH1_R`[src]

Bit 3

`pub fn sig_out_en_hsch1(&self) -> SIG_OUT_EN_HSCH1_R`[src]

Bit 2

`pub fn timer_sel_hsch1(&self) -> TIMER_SEL_HSCH1_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _HSCH1_HPOINT>>`[src]

`pub fn hpoint_hsch1(&self) -> HPOINT_HSCH1_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HSCH1_DUTY>>`[src]

`pub fn duty_hsch1(&self) -> DUTY_HSCH1_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSCH1_CONF1>>`[src]

`pub fn duty_start_hsch1(&self) -> DUTY_START_HSCH1_R`[src]

Bit 31

`pub fn duty_inc_hsch1(&self) -> DUTY_INC_HSCH1_R`[src]

Bit 30

`pub fn duty_num_hsch1(&self) -> DUTY_NUM_HSCH1_R`[src]

Bits 20:29

`pub fn duty_cycle_hsch1(&self) -> DUTY_CYCLE_HSCH1_R`[src]

Bits 10:19

`pub fn duty_scale_hsch1(&self) -> DUTY_SCALE_HSCH1_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _HSCH1_DUTY_R>>`[src]

`pub fn duty_hsch1(&self) -> DUTY_HSCH1_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSCH2_CONF0>>`[src]

`pub fn idle_lv_hsch2(&self) -> IDLE_LV_HSCH2_R`[src]

Bit 3

`pub fn sig_out_en_hsch2(&self) -> SIG_OUT_EN_HSCH2_R`[src]

Bit 2

`pub fn timer_sel_hsch2(&self) -> TIMER_SEL_HSCH2_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _HSCH2_HPOINT>>`[src]

`pub fn hpoint_hsch2(&self) -> HPOINT_HSCH2_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HSCH2_DUTY>>`[src]

`pub fn duty_hsch2(&self) -> DUTY_HSCH2_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSCH2_CONF1>>`[src]

`pub fn duty_start_hsch2(&self) -> DUTY_START_HSCH2_R`[src]

Bit 31

`pub fn duty_inc_hsch2(&self) -> DUTY_INC_HSCH2_R`[src]

Bit 30

`pub fn duty_num_hsch2(&self) -> DUTY_NUM_HSCH2_R`[src]

Bits 20:29

`pub fn duty_cycle_hsch2(&self) -> DUTY_CYCLE_HSCH2_R`[src]

Bits 10:19

`pub fn duty_scale_hsch2(&self) -> DUTY_SCALE_HSCH2_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _HSCH2_DUTY_R>>`[src]

`pub fn duty_hsch2(&self) -> DUTY_HSCH2_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSCH3_CONF0>>`[src]

`pub fn idle_lv_hsch3(&self) -> IDLE_LV_HSCH3_R`[src]

Bit 3

`pub fn sig_out_en_hsch3(&self) -> SIG_OUT_EN_HSCH3_R`[src]

Bit 2

`pub fn timer_sel_hsch3(&self) -> TIMER_SEL_HSCH3_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _HSCH3_HPOINT>>`[src]

`pub fn hpoint_hsch3(&self) -> HPOINT_HSCH3_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HSCH3_DUTY>>`[src]

`pub fn duty_hsch3(&self) -> DUTY_HSCH3_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSCH3_CONF1>>`[src]

`pub fn duty_start_hsch3(&self) -> DUTY_START_HSCH3_R`[src]

Bit 31

`pub fn duty_inc_hsch3(&self) -> DUTY_INC_HSCH3_R`[src]

Bit 30

`pub fn duty_num_hsch3(&self) -> DUTY_NUM_HSCH3_R`[src]

Bits 20:29

`pub fn duty_cycle_hsch3(&self) -> DUTY_CYCLE_HSCH3_R`[src]

Bits 10:19

`pub fn duty_scale_hsch3(&self) -> DUTY_SCALE_HSCH3_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _HSCH3_DUTY_R>>`[src]

`pub fn duty_hsch3(&self) -> DUTY_HSCH3_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSCH4_CONF0>>`[src]

`pub fn idle_lv_hsch4(&self) -> IDLE_LV_HSCH4_R`[src]

Bit 3

`pub fn sig_out_en_hsch4(&self) -> SIG_OUT_EN_HSCH4_R`[src]

Bit 2

`pub fn timer_sel_hsch4(&self) -> TIMER_SEL_HSCH4_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _HSCH4_HPOINT>>`[src]

`pub fn hpoint_hsch4(&self) -> HPOINT_HSCH4_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HSCH4_DUTY>>`[src]

`pub fn duty_hsch4(&self) -> DUTY_HSCH4_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSCH4_CONF1>>`[src]

`pub fn duty_start_hsch4(&self) -> DUTY_START_HSCH4_R`[src]

Bit 31

`pub fn duty_inc_hsch4(&self) -> DUTY_INC_HSCH4_R`[src]

Bit 30

`pub fn duty_num_hsch4(&self) -> DUTY_NUM_HSCH4_R`[src]

Bits 20:29

`pub fn duty_cycle_hsch4(&self) -> DUTY_CYCLE_HSCH4_R`[src]

Bits 10:19

`pub fn duty_scale_hsch4(&self) -> DUTY_SCALE_HSCH4_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _HSCH4_DUTY_R>>`[src]

`pub fn duty_hsch4(&self) -> DUTY_HSCH4_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSCH5_CONF0>>`[src]

`pub fn idle_lv_hsch5(&self) -> IDLE_LV_HSCH5_R`[src]

Bit 3

`pub fn sig_out_en_hsch5(&self) -> SIG_OUT_EN_HSCH5_R`[src]

Bit 2

`pub fn timer_sel_hsch5(&self) -> TIMER_SEL_HSCH5_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _HSCH5_HPOINT>>`[src]

`pub fn hpoint_hsch5(&self) -> HPOINT_HSCH5_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HSCH5_DUTY>>`[src]

`pub fn duty_hsch5(&self) -> DUTY_HSCH5_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSCH5_CONF1>>`[src]

`pub fn duty_start_hsch5(&self) -> DUTY_START_HSCH5_R`[src]

Bit 31

`pub fn duty_inc_hsch5(&self) -> DUTY_INC_HSCH5_R`[src]

Bit 30

`pub fn duty_num_hsch5(&self) -> DUTY_NUM_HSCH5_R`[src]

Bits 20:29

`pub fn duty_cycle_hsch5(&self) -> DUTY_CYCLE_HSCH5_R`[src]

Bits 10:19

`pub fn duty_scale_hsch5(&self) -> DUTY_SCALE_HSCH5_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _HSCH5_DUTY_R>>`[src]

`pub fn duty_hsch5(&self) -> DUTY_HSCH5_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSCH6_CONF0>>`[src]

`pub fn idle_lv_hsch6(&self) -> IDLE_LV_HSCH6_R`[src]

Bit 3

`pub fn sig_out_en_hsch6(&self) -> SIG_OUT_EN_HSCH6_R`[src]

Bit 2

`pub fn timer_sel_hsch6(&self) -> TIMER_SEL_HSCH6_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _HSCH6_HPOINT>>`[src]

`pub fn hpoint_hsch6(&self) -> HPOINT_HSCH6_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HSCH6_DUTY>>`[src]

`pub fn duty_hsch6(&self) -> DUTY_HSCH6_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSCH6_CONF1>>`[src]

`pub fn duty_start_hsch6(&self) -> DUTY_START_HSCH6_R`[src]

Bit 31

`pub fn duty_inc_hsch6(&self) -> DUTY_INC_HSCH6_R`[src]

Bit 30

`pub fn duty_num_hsch6(&self) -> DUTY_NUM_HSCH6_R`[src]

Bits 20:29

`pub fn duty_cycle_hsch6(&self) -> DUTY_CYCLE_HSCH6_R`[src]

Bits 10:19

`pub fn duty_scale_hsch6(&self) -> DUTY_SCALE_HSCH6_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _HSCH6_DUTY_R>>`[src]

`pub fn duty_hsch6(&self) -> DUTY_HSCH6_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSCH7_CONF0>>`[src]

`pub fn idle_lv_hsch7(&self) -> IDLE_LV_HSCH7_R`[src]

Bit 3

`pub fn sig_out_en_hsch7(&self) -> SIG_OUT_EN_HSCH7_R`[src]

Bit 2

`pub fn timer_sel_hsch7(&self) -> TIMER_SEL_HSCH7_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _HSCH7_HPOINT>>`[src]

`pub fn hpoint_hsch7(&self) -> HPOINT_HSCH7_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HSCH7_DUTY>>`[src]

`pub fn duty_hsch7(&self) -> DUTY_HSCH7_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSCH7_CONF1>>`[src]

`pub fn duty_start_hsch7(&self) -> DUTY_START_HSCH7_R`[src]

Bit 31

`pub fn duty_inc_hsch7(&self) -> DUTY_INC_HSCH7_R`[src]

Bit 30

`pub fn duty_num_hsch7(&self) -> DUTY_NUM_HSCH7_R`[src]

Bits 20:29

`pub fn duty_cycle_hsch7(&self) -> DUTY_CYCLE_HSCH7_R`[src]

Bits 10:19

`pub fn duty_scale_hsch7(&self) -> DUTY_SCALE_HSCH7_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _HSCH7_DUTY_R>>`[src]

`pub fn duty_hsch7(&self) -> DUTY_HSCH7_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH0_CONF0>>`[src]

`pub fn para_up_lsch0(&self) -> PARA_UP_LSCH0_R`[src]

Bit 4

`pub fn idle_lv_lsch0(&self) -> IDLE_LV_LSCH0_R`[src]

Bit 3

`pub fn sig_out_en_lsch0(&self) -> SIG_OUT_EN_LSCH0_R`[src]

Bit 2

`pub fn timer_sel_lsch0(&self) -> TIMER_SEL_LSCH0_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _LSCH0_HPOINT>>`[src]

`pub fn hpoint_lsch0(&self) -> HPOINT_LSCH0_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _LSCH0_DUTY>>`[src]

`pub fn duty_lsch0(&self) -> DUTY_LSCH0_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH0_CONF1>>`[src]

`pub fn duty_start_lsch0(&self) -> DUTY_START_LSCH0_R`[src]

Bit 31

`pub fn duty_inc_lsch0(&self) -> DUTY_INC_LSCH0_R`[src]

Bit 30

`pub fn duty_num_lsch0(&self) -> DUTY_NUM_LSCH0_R`[src]

Bits 20:29

`pub fn duty_cycle_lsch0(&self) -> DUTY_CYCLE_LSCH0_R`[src]

Bits 10:19

`pub fn duty_scale_lsch0(&self) -> DUTY_SCALE_LSCH0_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _LSCH0_DUTY_R>>`[src]

`pub fn duty_lsch0(&self) -> DUTY_LSCH0_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH1_CONF0>>`[src]

`pub fn para_up_lsch1(&self) -> PARA_UP_LSCH1_R`[src]

Bit 4

`pub fn idle_lv_lsch1(&self) -> IDLE_LV_LSCH1_R`[src]

Bit 3

`pub fn sig_out_en_lsch1(&self) -> SIG_OUT_EN_LSCH1_R`[src]

Bit 2

`pub fn timer_sel_lsch1(&self) -> TIMER_SEL_LSCH1_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _LSCH1_HPOINT>>`[src]

`pub fn hpoint_lsch1(&self) -> HPOINT_LSCH1_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _LSCH1_DUTY>>`[src]

`pub fn duty_lsch1(&self) -> DUTY_LSCH1_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH1_CONF1>>`[src]

`pub fn duty_start_lsch1(&self) -> DUTY_START_LSCH1_R`[src]

Bit 31

`pub fn duty_inc_lsch1(&self) -> DUTY_INC_LSCH1_R`[src]

Bit 30

`pub fn duty_num_lsch1(&self) -> DUTY_NUM_LSCH1_R`[src]

Bits 20:29

`pub fn duty_cycle_lsch1(&self) -> DUTY_CYCLE_LSCH1_R`[src]

Bits 10:19

`pub fn duty_scale_lsch1(&self) -> DUTY_SCALE_LSCH1_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _LSCH1_DUTY_R>>`[src]

`pub fn duty_lsch1(&self) -> DUTY_LSCH1_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH2_CONF0>>`[src]

`pub fn para_up_lsch2(&self) -> PARA_UP_LSCH2_R`[src]

Bit 4

`pub fn idle_lv_lsch2(&self) -> IDLE_LV_LSCH2_R`[src]

Bit 3

`pub fn sig_out_en_lsch2(&self) -> SIG_OUT_EN_LSCH2_R`[src]

Bit 2

`pub fn timer_sel_lsch2(&self) -> TIMER_SEL_LSCH2_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _LSCH2_HPOINT>>`[src]

`pub fn hpoint_lsch2(&self) -> HPOINT_LSCH2_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _LSCH2_DUTY>>`[src]

`pub fn duty_lsch2(&self) -> DUTY_LSCH2_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH2_CONF1>>`[src]

`pub fn duty_start_lsch2(&self) -> DUTY_START_LSCH2_R`[src]

Bit 31

`pub fn duty_inc_lsch2(&self) -> DUTY_INC_LSCH2_R`[src]

Bit 30

`pub fn duty_num_lsch2(&self) -> DUTY_NUM_LSCH2_R`[src]

Bits 20:29

`pub fn duty_cycle_lsch2(&self) -> DUTY_CYCLE_LSCH2_R`[src]

Bits 10:19

`pub fn duty_scale_lsch2(&self) -> DUTY_SCALE_LSCH2_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _LSCH2_DUTY_R>>`[src]

`pub fn duty_lsch2(&self) -> DUTY_LSCH2_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH3_CONF0>>`[src]

`pub fn para_up_lsch3(&self) -> PARA_UP_LSCH3_R`[src]

Bit 4

`pub fn idle_lv_lsch3(&self) -> IDLE_LV_LSCH3_R`[src]

Bit 3

`pub fn sig_out_en_lsch3(&self) -> SIG_OUT_EN_LSCH3_R`[src]

Bit 2

`pub fn timer_sel_lsch3(&self) -> TIMER_SEL_LSCH3_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _LSCH3_HPOINT>>`[src]

`pub fn hpoint_lsch3(&self) -> HPOINT_LSCH3_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _LSCH3_DUTY>>`[src]

`pub fn duty_lsch3(&self) -> DUTY_LSCH3_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH3_CONF1>>`[src]

`pub fn duty_start_lsch3(&self) -> DUTY_START_LSCH3_R`[src]

Bit 31

`pub fn duty_inc_lsch3(&self) -> DUTY_INC_LSCH3_R`[src]

Bit 30

`pub fn duty_num_lsch3(&self) -> DUTY_NUM_LSCH3_R`[src]

Bits 20:29

`pub fn duty_cycle_lsch3(&self) -> DUTY_CYCLE_LSCH3_R`[src]

Bits 10:19

`pub fn duty_scale_lsch3(&self) -> DUTY_SCALE_LSCH3_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _LSCH3_DUTY_R>>`[src]

`pub fn duty_lsch3(&self) -> DUTY_LSCH3_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH4_CONF0>>`[src]

`pub fn para_up_lsch4(&self) -> PARA_UP_LSCH4_R`[src]

Bit 4

`pub fn idle_lv_lsch4(&self) -> IDLE_LV_LSCH4_R`[src]

Bit 3

`pub fn sig_out_en_lsch4(&self) -> SIG_OUT_EN_LSCH4_R`[src]

Bit 2

`pub fn timer_sel_lsch4(&self) -> TIMER_SEL_LSCH4_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _LSCH4_HPOINT>>`[src]

`pub fn hpoint_lsch4(&self) -> HPOINT_LSCH4_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _LSCH4_DUTY>>`[src]

`pub fn duty_lsch4(&self) -> DUTY_LSCH4_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH4_CONF1>>`[src]

`pub fn duty_start_lsch4(&self) -> DUTY_START_LSCH4_R`[src]

Bit 31

`pub fn duty_inc_lsch4(&self) -> DUTY_INC_LSCH4_R`[src]

Bit 30

`pub fn duty_num_lsch4(&self) -> DUTY_NUM_LSCH4_R`[src]

Bits 20:29

`pub fn duty_cycle_lsch4(&self) -> DUTY_CYCLE_LSCH4_R`[src]

Bits 10:19

`pub fn duty_scale_lsch4(&self) -> DUTY_SCALE_LSCH4_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _LSCH4_DUTY_R>>`[src]

`pub fn duty_lsch4(&self) -> DUTY_LSCH4_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH5_CONF0>>`[src]

`pub fn para_up_lsch5(&self) -> PARA_UP_LSCH5_R`[src]

Bit 4

`pub fn idle_lv_lsch5(&self) -> IDLE_LV_LSCH5_R`[src]

Bit 3

`pub fn sig_out_en_lsch5(&self) -> SIG_OUT_EN_LSCH5_R`[src]

Bit 2

`pub fn timer_sel_lsch5(&self) -> TIMER_SEL_LSCH5_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _LSCH5_HPOINT>>`[src]

`pub fn hpoint_lsch5(&self) -> HPOINT_LSCH5_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _LSCH5_DUTY>>`[src]

`pub fn duty_lsch5(&self) -> DUTY_LSCH5_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH5_CONF1>>`[src]

`pub fn duty_start_lsch5(&self) -> DUTY_START_LSCH5_R`[src]

Bit 31

`pub fn duty_inc_lsch5(&self) -> DUTY_INC_LSCH5_R`[src]

Bit 30

`pub fn duty_num_lsch5(&self) -> DUTY_NUM_LSCH5_R`[src]

Bits 20:29

`pub fn duty_cycle_lsch5(&self) -> DUTY_CYCLE_LSCH5_R`[src]

Bits 10:19

`pub fn duty_scale_lsch5(&self) -> DUTY_SCALE_LSCH5_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _LSCH5_DUTY_R>>`[src]

`pub fn duty_lsch5(&self) -> DUTY_LSCH5_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH6_CONF0>>`[src]

`pub fn para_up_lsch6(&self) -> PARA_UP_LSCH6_R`[src]

Bit 4

`pub fn idle_lv_lsch6(&self) -> IDLE_LV_LSCH6_R`[src]

Bit 3

`pub fn sig_out_en_lsch6(&self) -> SIG_OUT_EN_LSCH6_R`[src]

Bit 2

`pub fn timer_sel_lsch6(&self) -> TIMER_SEL_LSCH6_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _LSCH6_HPOINT>>`[src]

`pub fn hpoint_lsch6(&self) -> HPOINT_LSCH6_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _LSCH6_DUTY>>`[src]

`pub fn duty_lsch6(&self) -> DUTY_LSCH6_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH6_CONF1>>`[src]

`pub fn duty_start_lsch6(&self) -> DUTY_START_LSCH6_R`[src]

Bit 31

`pub fn duty_inc_lsch6(&self) -> DUTY_INC_LSCH6_R`[src]

Bit 30

`pub fn duty_num_lsch6(&self) -> DUTY_NUM_LSCH6_R`[src]

Bits 20:29

`pub fn duty_cycle_lsch6(&self) -> DUTY_CYCLE_LSCH6_R`[src]

Bits 10:19

`pub fn duty_scale_lsch6(&self) -> DUTY_SCALE_LSCH6_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _LSCH6_DUTY_R>>`[src]

`pub fn duty_lsch6(&self) -> DUTY_LSCH6_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH7_CONF0>>`[src]

`pub fn para_up_lsch7(&self) -> PARA_UP_LSCH7_R`[src]

Bit 4

`pub fn idle_lv_lsch7(&self) -> IDLE_LV_LSCH7_R`[src]

Bit 3

`pub fn sig_out_en_lsch7(&self) -> SIG_OUT_EN_LSCH7_R`[src]

Bit 2

`pub fn timer_sel_lsch7(&self) -> TIMER_SEL_LSCH7_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _LSCH7_HPOINT>>`[src]

`pub fn hpoint_lsch7(&self) -> HPOINT_LSCH7_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _LSCH7_DUTY>>`[src]

`pub fn duty_lsch7(&self) -> DUTY_LSCH7_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _LSCH7_CONF1>>`[src]

`pub fn duty_start_lsch7(&self) -> DUTY_START_LSCH7_R`[src]

Bit 31

`pub fn duty_inc_lsch7(&self) -> DUTY_INC_LSCH7_R`[src]

Bit 30

`pub fn duty_num_lsch7(&self) -> DUTY_NUM_LSCH7_R`[src]

Bits 20:29

`pub fn duty_cycle_lsch7(&self) -> DUTY_CYCLE_LSCH7_R`[src]

Bits 10:19

`pub fn duty_scale_lsch7(&self) -> DUTY_SCALE_LSCH7_R`[src]

Bits 0:9

`impl R<u32, Reg<u32, _LSCH7_DUTY_R>>`[src]

`pub fn duty_lsch7(&self) -> DUTY_LSCH7_R`[src]

Bits 0:24

`impl R<u32, Reg<u32, _HSTIMER0_CONF>>`[src]

`pub fn tick_sel_hstimer0(&self) -> TICK_SEL_HSTIMER0_R`[src]

Bit 25

`pub fn hstimer0_rst(&self) -> HSTIMER0_RST_R`[src]

Bit 24

`pub fn hstimer0_pause(&self) -> HSTIMER0_PAUSE_R`[src]

Bit 23

`pub fn div_num_hstimer0(&self) -> DIV_NUM_HSTIMER0_R`[src]

Bits 5:22

`pub fn hstimer0_lim(&self) -> HSTIMER0_LIM_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _HSTIMER0_VALUE>>`[src]

`pub fn hstimer0_cnt(&self) -> HSTIMER0_CNT_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HSTIMER1_CONF>>`[src]

`pub fn tick_sel_hstimer1(&self) -> TICK_SEL_HSTIMER1_R`[src]

Bit 25

`pub fn hstimer1_rst(&self) -> HSTIMER1_RST_R`[src]

Bit 24

`pub fn hstimer1_pause(&self) -> HSTIMER1_PAUSE_R`[src]

Bit 23

`pub fn div_num_hstimer1(&self) -> DIV_NUM_HSTIMER1_R`[src]

Bits 5:22

`pub fn hstimer1_lim(&self) -> HSTIMER1_LIM_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _HSTIMER1_VALUE>>`[src]

`pub fn hstimer1_cnt(&self) -> HSTIMER1_CNT_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HSTIMER2_CONF>>`[src]

`pub fn tick_sel_hstimer2(&self) -> TICK_SEL_HSTIMER2_R`[src]

Bit 25

`pub fn hstimer2_rst(&self) -> HSTIMER2_RST_R`[src]

Bit 24

`pub fn hstimer2_pause(&self) -> HSTIMER2_PAUSE_R`[src]

Bit 23

`pub fn div_num_hstimer2(&self) -> DIV_NUM_HSTIMER2_R`[src]

Bits 5:22

`pub fn hstimer2_lim(&self) -> HSTIMER2_LIM_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _HSTIMER2_VALUE>>`[src]

`pub fn hstimer2_cnt(&self) -> HSTIMER2_CNT_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _HSTIMER3_CONF>>`[src]

`pub fn tick_sel_hstimer3(&self) -> TICK_SEL_HSTIMER3_R`[src]

Bit 25

`pub fn hstimer3_rst(&self) -> HSTIMER3_RST_R`[src]

Bit 24

`pub fn hstimer3_pause(&self) -> HSTIMER3_PAUSE_R`[src]

Bit 23

`pub fn div_num_hstimer3(&self) -> DIV_NUM_HSTIMER3_R`[src]

Bits 5:22

`pub fn hstimer3_lim(&self) -> HSTIMER3_LIM_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _HSTIMER3_VALUE>>`[src]

`pub fn hstimer3_cnt(&self) -> HSTIMER3_CNT_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _LSTIMER0_CONF>>`[src]

`pub fn lstimer0_para_up(&self) -> LSTIMER0_PARA_UP_R`[src]

Bit 26

`pub fn tick_sel_lstimer0(&self) -> TICK_SEL_LSTIMER0_R`[src]

Bit 25

`pub fn lstimer0_rst(&self) -> LSTIMER0_RST_R`[src]

Bit 24

`pub fn lstimer0_pause(&self) -> LSTIMER0_PAUSE_R`[src]

Bit 23

`pub fn div_num_lstimer0(&self) -> DIV_NUM_LSTIMER0_R`[src]

Bits 5:22

`pub fn lstimer0_lim(&self) -> LSTIMER0_LIM_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _LSTIMER0_VALUE>>`[src]

`pub fn lstimer0_cnt(&self) -> LSTIMER0_CNT_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _LSTIMER1_CONF>>`[src]

`pub fn lstimer1_para_up(&self) -> LSTIMER1_PARA_UP_R`[src]

Bit 26

`pub fn tick_sel_lstimer1(&self) -> TICK_SEL_LSTIMER1_R`[src]

Bit 25

`pub fn lstimer1_rst(&self) -> LSTIMER1_RST_R`[src]

Bit 24

`pub fn lstimer1_pause(&self) -> LSTIMER1_PAUSE_R`[src]

Bit 23

`pub fn div_num_lstimer1(&self) -> DIV_NUM_LSTIMER1_R`[src]

Bits 5:22

`pub fn lstimer1_lim(&self) -> LSTIMER1_LIM_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _LSTIMER1_VALUE>>`[src]

`pub fn lstimer1_cnt(&self) -> LSTIMER1_CNT_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _LSTIMER2_CONF>>`[src]

`pub fn lstimer2_para_up(&self) -> LSTIMER2_PARA_UP_R`[src]

Bit 26

`pub fn tick_sel_lstimer2(&self) -> TICK_SEL_LSTIMER2_R`[src]

Bit 25

`pub fn lstimer2_rst(&self) -> LSTIMER2_RST_R`[src]

Bit 24

`pub fn lstimer2_pause(&self) -> LSTIMER2_PAUSE_R`[src]

Bit 23

`pub fn div_num_lstimer2(&self) -> DIV_NUM_LSTIMER2_R`[src]

Bits 5:22

`pub fn lstimer2_lim(&self) -> LSTIMER2_LIM_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _LSTIMER2_VALUE>>`[src]

`pub fn lstimer2_cnt(&self) -> LSTIMER2_CNT_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _LSTIMER3_CONF>>`[src]

`pub fn lstimer3_para_up(&self) -> LSTIMER3_PARA_UP_R`[src]

Bit 26

`pub fn tick_sel_lstimer3(&self) -> TICK_SEL_LSTIMER3_R`[src]

Bit 25

`pub fn lstimer3_rst(&self) -> LSTIMER3_RST_R`[src]

Bit 24

`pub fn lstimer3_pause(&self) -> LSTIMER3_PAUSE_R`[src]

Bit 23

`pub fn div_num_lstimer3(&self) -> DIV_NUM_LSTIMER3_R`[src]

Bits 5:22

`pub fn lstimer3_lim(&self) -> LSTIMER3_LIM_R`[src]

Bits 0:4

`impl R<u32, Reg<u32, _LSTIMER3_VALUE>>`[src]

`pub fn lstimer3_cnt(&self) -> LSTIMER3_CNT_R`[src]

Bits 0:19

`impl R<u32, Reg<u32, _INT_RAW>>`[src]

`pub fn duty_chng_end_lsch7_int_raw(&self) -> DUTY_CHNG_END_LSCH7_INT_RAW_R`[src]

Bit 23

`pub fn duty_chng_end_lsch6_int_raw(&self) -> DUTY_CHNG_END_LSCH6_INT_RAW_R`[src]

Bit 22

`pub fn duty_chng_end_lsch5_int_raw(&self) -> DUTY_CHNG_END_LSCH5_INT_RAW_R`[src]

Bit 21

`pub fn duty_chng_end_lsch4_int_raw(&self) -> DUTY_CHNG_END_LSCH4_INT_RAW_R`[src]

Bit 20

`pub fn duty_chng_end_lsch3_int_raw(&self) -> DUTY_CHNG_END_LSCH3_INT_RAW_R`[src]

Bit 19

`pub fn duty_chng_end_lsch2_int_raw(&self) -> DUTY_CHNG_END_LSCH2_INT_RAW_R`[src]

Bit 18

`pub fn duty_chng_end_lsch1_int_raw(&self) -> DUTY_CHNG_END_LSCH1_INT_RAW_R`[src]

Bit 17

`pub fn duty_chng_end_lsch0_int_raw(&self) -> DUTY_CHNG_END_LSCH0_INT_RAW_R`[src]

Bit 16

`pub fn duty_chng_end_hsch7_int_raw(&self) -> DUTY_CHNG_END_HSCH7_INT_RAW_R`[src]

Bit 15

`pub fn duty_chng_end_hsch6_int_raw(&self) -> DUTY_CHNG_END_HSCH6_INT_RAW_R`[src]

Bit 14

`pub fn duty_chng_end_hsch5_int_raw(&self) -> DUTY_CHNG_END_HSCH5_INT_RAW_R`[src]

Bit 13

`pub fn duty_chng_end_hsch4_int_raw(&self) -> DUTY_CHNG_END_HSCH4_INT_RAW_R`[src]

Bit 12

`pub fn duty_chng_end_hsch3_int_raw(&self) -> DUTY_CHNG_END_HSCH3_INT_RAW_R`[src]

Bit 11

`pub fn duty_chng_end_hsch2_int_raw(&self) -> DUTY_CHNG_END_HSCH2_INT_RAW_R`[src]

Bit 10

`pub fn duty_chng_end_hsch1_int_raw(&self) -> DUTY_CHNG_END_HSCH1_INT_RAW_R`[src]

Bit 9

`pub fn duty_chng_end_hsch0_int_raw(&self) -> DUTY_CHNG_END_HSCH0_INT_RAW_R`[src]

Bit 8

`pub fn lstimer3_ovf_int_raw(&self) -> LSTIMER3_OVF_INT_RAW_R`[src]

Bit 7

`pub fn lstimer2_ovf_int_raw(&self) -> LSTIMER2_OVF_INT_RAW_R`[src]

Bit 6

`pub fn lstimer1_ovf_int_raw(&self) -> LSTIMER1_OVF_INT_RAW_R`[src]

Bit 5

`pub fn lstimer0_ovf_int_raw(&self) -> LSTIMER0_OVF_INT_RAW_R`[src]

Bit 4

`pub fn hstimer3_ovf_int_raw(&self) -> HSTIMER3_OVF_INT_RAW_R`[src]

Bit 3

`pub fn hstimer2_ovf_int_raw(&self) -> HSTIMER2_OVF_INT_RAW_R`[src]

Bit 2

`pub fn hstimer1_ovf_int_raw(&self) -> HSTIMER1_OVF_INT_RAW_R`[src]

Bit 1

`pub fn hstimer0_ovf_int_raw(&self) -> HSTIMER0_OVF_INT_RAW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_ST>>`[src]

`pub fn duty_chng_end_lsch7_int_st(&self) -> DUTY_CHNG_END_LSCH7_INT_ST_R`[src]

Bit 23

`pub fn duty_chng_end_lsch6_int_st(&self) -> DUTY_CHNG_END_LSCH6_INT_ST_R`[src]

Bit 22

`pub fn duty_chng_end_lsch5_int_st(&self) -> DUTY_CHNG_END_LSCH5_INT_ST_R`[src]

Bit 21

`pub fn duty_chng_end_lsch4_int_st(&self) -> DUTY_CHNG_END_LSCH4_INT_ST_R`[src]

Bit 20

`pub fn duty_chng_end_lsch3_int_st(&self) -> DUTY_CHNG_END_LSCH3_INT_ST_R`[src]

Bit 19

`pub fn duty_chng_end_lsch2_int_st(&self) -> DUTY_CHNG_END_LSCH2_INT_ST_R`[src]

Bit 18

`pub fn duty_chng_end_lsch1_int_st(&self) -> DUTY_CHNG_END_LSCH1_INT_ST_R`[src]

Bit 17

`pub fn duty_chng_end_lsch0_int_st(&self) -> DUTY_CHNG_END_LSCH0_INT_ST_R`[src]

Bit 16

`pub fn duty_chng_end_hsch7_int_st(&self) -> DUTY_CHNG_END_HSCH7_INT_ST_R`[src]

Bit 15

`pub fn duty_chng_end_hsch6_int_st(&self) -> DUTY_CHNG_END_HSCH6_INT_ST_R`[src]

Bit 14

`pub fn duty_chng_end_hsch5_int_st(&self) -> DUTY_CHNG_END_HSCH5_INT_ST_R`[src]

Bit 13

`pub fn duty_chng_end_hsch4_int_st(&self) -> DUTY_CHNG_END_HSCH4_INT_ST_R`[src]

Bit 12

`pub fn duty_chng_end_hsch3_int_st(&self) -> DUTY_CHNG_END_HSCH3_INT_ST_R`[src]

Bit 11

`pub fn duty_chng_end_hsch2_int_st(&self) -> DUTY_CHNG_END_HSCH2_INT_ST_R`[src]

Bit 10

`pub fn duty_chng_end_hsch1_int_st(&self) -> DUTY_CHNG_END_HSCH1_INT_ST_R`[src]

Bit 9

`pub fn duty_chng_end_hsch0_int_st(&self) -> DUTY_CHNG_END_HSCH0_INT_ST_R`[src]

Bit 8

`pub fn lstimer3_ovf_int_st(&self) -> LSTIMER3_OVF_INT_ST_R`[src]

Bit 7

`pub fn lstimer2_ovf_int_st(&self) -> LSTIMER2_OVF_INT_ST_R`[src]

Bit 6

`pub fn lstimer1_ovf_int_st(&self) -> LSTIMER1_OVF_INT_ST_R`[src]

Bit 5

`pub fn lstimer0_ovf_int_st(&self) -> LSTIMER0_OVF_INT_ST_R`[src]

Bit 4

`pub fn hstimer3_ovf_int_st(&self) -> HSTIMER3_OVF_INT_ST_R`[src]

Bit 3

`pub fn hstimer2_ovf_int_st(&self) -> HSTIMER2_OVF_INT_ST_R`[src]

Bit 2

`pub fn hstimer1_ovf_int_st(&self) -> HSTIMER1_OVF_INT_ST_R`[src]

Bit 1

`pub fn hstimer0_ovf_int_st(&self) -> HSTIMER0_OVF_INT_ST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_ENA>>`[src]

`pub fn duty_chng_end_lsch7_int_ena(&self) -> DUTY_CHNG_END_LSCH7_INT_ENA_R`[src]

Bit 23

`pub fn duty_chng_end_lsch6_int_ena(&self) -> DUTY_CHNG_END_LSCH6_INT_ENA_R`[src]

Bit 22

`pub fn duty_chng_end_lsch5_int_ena(&self) -> DUTY_CHNG_END_LSCH5_INT_ENA_R`[src]

Bit 21

`pub fn duty_chng_end_lsch4_int_ena(&self) -> DUTY_CHNG_END_LSCH4_INT_ENA_R`[src]

Bit 20

`pub fn duty_chng_end_lsch3_int_ena(&self) -> DUTY_CHNG_END_LSCH3_INT_ENA_R`[src]

Bit 19

`pub fn duty_chng_end_lsch2_int_ena(&self) -> DUTY_CHNG_END_LSCH2_INT_ENA_R`[src]

Bit 18

`pub fn duty_chng_end_lsch1_int_ena(&self) -> DUTY_CHNG_END_LSCH1_INT_ENA_R`[src]

Bit 17

`pub fn duty_chng_end_lsch0_int_ena(&self) -> DUTY_CHNG_END_LSCH0_INT_ENA_R`[src]

Bit 16

`pub fn duty_chng_end_hsch7_int_ena(&self) -> DUTY_CHNG_END_HSCH7_INT_ENA_R`[src]

Bit 15

`pub fn duty_chng_end_hsch6_int_ena(&self) -> DUTY_CHNG_END_HSCH6_INT_ENA_R`[src]

Bit 14

`pub fn duty_chng_end_hsch5_int_ena(&self) -> DUTY_CHNG_END_HSCH5_INT_ENA_R`[src]

Bit 13

`pub fn duty_chng_end_hsch4_int_ena(&self) -> DUTY_CHNG_END_HSCH4_INT_ENA_R`[src]

Bit 12

`pub fn duty_chng_end_hsch3_int_ena(&self) -> DUTY_CHNG_END_HSCH3_INT_ENA_R`[src]

Bit 11

`pub fn duty_chng_end_hsch2_int_ena(&self) -> DUTY_CHNG_END_HSCH2_INT_ENA_R`[src]

Bit 10

`pub fn duty_chng_end_hsch1_int_ena(&self) -> DUTY_CHNG_END_HSCH1_INT_ENA_R`[src]

Bit 9

`pub fn duty_chng_end_hsch0_int_ena(&self) -> DUTY_CHNG_END_HSCH0_INT_ENA_R`[src]

Bit 8

`pub fn lstimer3_ovf_int_ena(&self) -> LSTIMER3_OVF_INT_ENA_R`[src]

Bit 7

`pub fn lstimer2_ovf_int_ena(&self) -> LSTIMER2_OVF_INT_ENA_R`[src]

Bit 6

`pub fn lstimer1_ovf_int_ena(&self) -> LSTIMER1_OVF_INT_ENA_R`[src]

Bit 5

`pub fn lstimer0_ovf_int_ena(&self) -> LSTIMER0_OVF_INT_ENA_R`[src]

Bit 4

`pub fn hstimer3_ovf_int_ena(&self) -> HSTIMER3_OVF_INT_ENA_R`[src]

Bit 3

`pub fn hstimer2_ovf_int_ena(&self) -> HSTIMER2_OVF_INT_ENA_R`[src]

Bit 2

`pub fn hstimer1_ovf_int_ena(&self) -> HSTIMER1_OVF_INT_ENA_R`[src]

Bit 1

`pub fn hstimer0_ovf_int_ena(&self) -> HSTIMER0_OVF_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _INT_CLR>>`[src]

`pub fn duty_chng_end_lsch7_int_clr(&self) -> DUTY_CHNG_END_LSCH7_INT_CLR_R`[src]

Bit 23

`pub fn duty_chng_end_lsch6_int_clr(&self) -> DUTY_CHNG_END_LSCH6_INT_CLR_R`[src]

Bit 22

`pub fn duty_chng_end_lsch5_int_clr(&self) -> DUTY_CHNG_END_LSCH5_INT_CLR_R`[src]

Bit 21

`pub fn duty_chng_end_lsch4_int_clr(&self) -> DUTY_CHNG_END_LSCH4_INT_CLR_R`[src]

Bit 20

`pub fn duty_chng_end_lsch3_int_clr(&self) -> DUTY_CHNG_END_LSCH3_INT_CLR_R`[src]

Bit 19

`pub fn duty_chng_end_lsch2_int_clr(&self) -> DUTY_CHNG_END_LSCH2_INT_CLR_R`[src]

Bit 18

`pub fn duty_chng_end_lsch1_int_clr(&self) -> DUTY_CHNG_END_LSCH1_INT_CLR_R`[src]

Bit 17

`pub fn duty_chng_end_lsch0_int_clr(&self) -> DUTY_CHNG_END_LSCH0_INT_CLR_R`[src]

Bit 16

`pub fn duty_chng_end_hsch7_int_clr(&self) -> DUTY_CHNG_END_HSCH7_INT_CLR_R`[src]

Bit 15

`pub fn duty_chng_end_hsch6_int_clr(&self) -> DUTY_CHNG_END_HSCH6_INT_CLR_R`[src]

Bit 14

`pub fn duty_chng_end_hsch5_int_clr(&self) -> DUTY_CHNG_END_HSCH5_INT_CLR_R`[src]

Bit 13

`pub fn duty_chng_end_hsch4_int_clr(&self) -> DUTY_CHNG_END_HSCH4_INT_CLR_R`[src]

Bit 12

`pub fn duty_chng_end_hsch3_int_clr(&self) -> DUTY_CHNG_END_HSCH3_INT_CLR_R`[src]

Bit 11

`pub fn duty_chng_end_hsch2_int_clr(&self) -> DUTY_CHNG_END_HSCH2_INT_CLR_R`[src]

Bit 10

`pub fn duty_chng_end_hsch1_int_clr(&self) -> DUTY_CHNG_END_HSCH1_INT_CLR_R`[src]

Bit 9

`pub fn duty_chng_end_hsch0_int_clr(&self) -> DUTY_CHNG_END_HSCH0_INT_CLR_R`[src]

Bit 8

`pub fn lstimer3_ovf_int_clr(&self) -> LSTIMER3_OVF_INT_CLR_R`[src]

Bit 7

`pub fn lstimer2_ovf_int_clr(&self) -> LSTIMER2_OVF_INT_CLR_R`[src]

Bit 6

`pub fn lstimer1_ovf_int_clr(&self) -> LSTIMER1_OVF_INT_CLR_R`[src]

Bit 5

`pub fn lstimer0_ovf_int_clr(&self) -> LSTIMER0_OVF_INT_CLR_R`[src]

Bit 4

`pub fn hstimer3_ovf_int_clr(&self) -> HSTIMER3_OVF_INT_CLR_R`[src]

Bit 3

`pub fn hstimer2_ovf_int_clr(&self) -> HSTIMER2_OVF_INT_CLR_R`[src]

Bit 2

`pub fn hstimer1_ovf_int_clr(&self) -> HSTIMER1_OVF_INT_CLR_R`[src]

Bit 1

`pub fn hstimer0_ovf_int_clr(&self) -> HSTIMER0_OVF_INT_CLR_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CONF>>`[src]

`pub fn apb_clk_sel(&self) -> APB_CLK_SEL_R`[src]

Bit 0

`impl R<u32, Reg<u32, _DATE>>`[src]

`pub fn date(&self) -> DATE_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _CLK_CFG>>`[src]

`pub fn clk_prescale(&self) -> CLK_PRESCALE_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _TIMER0_CFG0>>`[src]

`pub fn timer0_period_upmethod(&self) -> TIMER0_PERIOD_UPMETHOD_R`[src]

Bits 24:25

`pub fn timer0_period(&self) -> TIMER0_PERIOD_R`[src]

Bits 8:23

`pub fn timer0_prescale(&self) -> TIMER0_PRESCALE_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _TIMER0_CFG1>>`[src]

`pub fn timer0_mod(&self) -> TIMER0_MOD_R`[src]

Bits 3:4

`pub fn timer0_start(&self) -> TIMER0_START_R`[src]

Bits 0:2

`impl R<u32, Reg<u32, _TIMER0_SYNC>>`[src]

`pub fn timer0_phase(&self) -> TIMER0_PHASE_R`[src]

Bits 4:20

`pub fn timer0_synco_sel(&self) -> TIMER0_SYNCO_SEL_R`[src]

Bits 2:3

`pub fn timer0_sync_sw(&self) -> TIMER0_SYNC_SW_R`[src]

Bit 1

`pub fn timer0_synci_en(&self) -> TIMER0_SYNCI_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _TIMER0_STATUS>>`[src]

`pub fn timer0_direction(&self) -> TIMER0_DIRECTION_R`[src]

Bit 16

`pub fn timer0_value(&self) -> TIMER0_VALUE_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _TIMER1_CFG0>>`[src]

`pub fn timer1_period_upmethod(&self) -> TIMER1_PERIOD_UPMETHOD_R`[src]

Bits 24:25

`pub fn timer1_period(&self) -> TIMER1_PERIOD_R`[src]

Bits 8:23

`pub fn timer1_prescale(&self) -> TIMER1_PRESCALE_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _TIMER1_CFG1>>`[src]

`pub fn timer1_mod(&self) -> TIMER1_MOD_R`[src]

Bits 3:4

`pub fn timer1_start(&self) -> TIMER1_START_R`[src]

Bits 0:2

`impl R<u32, Reg<u32, _TIMER1_SYNC>>`[src]

`pub fn timer1_phase(&self) -> TIMER1_PHASE_R`[src]

Bits 4:20

`pub fn timer1_synco_sel(&self) -> TIMER1_SYNCO_SEL_R`[src]

Bits 2:3

`pub fn timer1_sync_sw(&self) -> TIMER1_SYNC_SW_R`[src]

Bit 1

`pub fn timer1_synci_en(&self) -> TIMER1_SYNCI_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _TIMER1_STATUS>>`[src]

`pub fn timer1_direction(&self) -> TIMER1_DIRECTION_R`[src]

Bit 16

`pub fn timer1_value(&self) -> TIMER1_VALUE_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _TIMER2_CFG0>>`[src]

`pub fn timer2_period_upmethod(&self) -> TIMER2_PERIOD_UPMETHOD_R`[src]

Bits 24:25

`pub fn timer2_period(&self) -> TIMER2_PERIOD_R`[src]

Bits 8:23

`pub fn timer2_prescale(&self) -> TIMER2_PRESCALE_R`[src]

Bits 0:7

`impl R<u32, Reg<u32, _TIMER2_CFG1>>`[src]

`pub fn timer2_mod(&self) -> TIMER2_MOD_R`[src]

Bits 3:4

`pub fn timer2_start(&self) -> TIMER2_START_R`[src]

Bits 0:2

`impl R<u32, Reg<u32, _TIMER2_SYNC>>`[src]

`pub fn timer2_phase(&self) -> TIMER2_PHASE_R`[src]

Bits 4:20

`pub fn timer2_synco_sel(&self) -> TIMER2_SYNCO_SEL_R`[src]

Bits 2:3

`pub fn timer2_sync_sw(&self) -> TIMER2_SYNC_SW_R`[src]

Bit 1

`pub fn timer2_synci_en(&self) -> TIMER2_SYNCI_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _TIMER2_STATUS>>`[src]

`pub fn timer2_direction(&self) -> TIMER2_DIRECTION_R`[src]

Bit 16

`pub fn timer2_value(&self) -> TIMER2_VALUE_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _TIMER_SYNCI_CFG>>`[src]

`pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI2_INVERT_R`[src]

Bit 11

`pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI1_INVERT_R`[src]

Bit 10

`pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI0_INVERT_R`[src]

Bit 9

`pub fn timer2_syncisel(&self) -> TIMER2_SYNCISEL_R`[src]

Bits 6:8

`pub fn timer1_syncisel(&self) -> TIMER1_SYNCISEL_R`[src]

Bits 3:5

`pub fn timer0_syncisel(&self) -> TIMER0_SYNCISEL_R`[src]

Bits 0:2

`impl R<u32, Reg<u32, _OPERATOR_TIMERSEL>>`[src]

`pub fn operator2_timersel(&self) -> OPERATOR2_TIMERSEL_R`[src]

Bits 4:5

`pub fn operator1_timersel(&self) -> OPERATOR1_TIMERSEL_R`[src]

Bits 2:3

`pub fn operator0_timersel(&self) -> OPERATOR0_TIMERSEL_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _GEN0_STMP_CFG>>`[src]

`pub fn gen0_b_shdw_full(&self) -> GEN0_B_SHDW_FULL_R`[src]

Bit 9

`pub fn gen0_a_shdw_full(&self) -> GEN0_A_SHDW_FULL_R`[src]

Bit 8

`pub fn gen0_b_upmethod(&self) -> GEN0_B_UPMETHOD_R`[src]

Bits 4:7

`pub fn gen0_a_upmethod(&self) -> GEN0_A_UPMETHOD_R`[src]

Bits 0:3

`impl R<u32, Reg<u32, _GEN0_TSTMP_A>>`[src]

`pub fn gen0_a(&self) -> GEN0_A_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _GEN0_TSTMP_B>>`[src]

`pub fn gen0_b(&self) -> GEN0_B_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _GEN0_CFG0>>`[src]

`pub fn gen0_t1_sel(&self) -> GEN0_T1_SEL_R`[src]

Bits 7:9

`pub fn gen0_t0_sel(&self) -> GEN0_T0_SEL_R`[src]

Bits 4:6

`pub fn gen0_cfg_upmethod(&self) -> GEN0_CFG_UPMETHOD_R`[src]

Bits 0:3

`impl R<u32, Reg<u32, _GEN0_FORCE>>`[src]

`pub fn gen0_b_nciforce_mode(&self) -> GEN0_B_NCIFORCE_MODE_R`[src]

Bits 14:15

`pub fn gen0_b_nciforce(&self) -> GEN0_B_NCIFORCE_R`[src]

Bit 13

`pub fn gen0_a_nciforce_mode(&self) -> GEN0_A_NCIFORCE_MODE_R`[src]

Bits 11:12

`pub fn gen0_a_nciforce(&self) -> GEN0_A_NCIFORCE_R`[src]

Bit 10

`pub fn gen0_b_cntuforce_mode(&self) -> GEN0_B_CNTUFORCE_MODE_R`[src]

Bits 8:9

`pub fn gen0_a_cntuforce_mode(&self) -> GEN0_A_CNTUFORCE_MODE_R`[src]

Bits 6:7

`pub fn gen0_cntuforce_upmethod(&self) -> GEN0_CNTUFORCE_UPMETHOD_R`[src]

Bits 0:5

`impl R<u32, Reg<u32, _GEN0_A>>`[src]

`pub fn gen0_a_dt1(&self) -> GEN0_A_DT1_R`[src]

Bits 22:23

`pub fn gen0_a_dt0(&self) -> GEN0_A_DT0_R`[src]

Bits 20:21

`pub fn gen0_a_dteb(&self) -> GEN0_A_DTEB_R`[src]

Bits 18:19

`pub fn gen0_a_dtea(&self) -> GEN0_A_DTEA_R`[src]

Bits 16:17

`pub fn gen0_a_dtep(&self) -> GEN0_A_DTEP_R`[src]

Bits 14:15

`pub fn gen0_a_dtez(&self) -> GEN0_A_DTEZ_R`[src]

Bits 12:13

`pub fn gen0_a_ut1(&self) -> GEN0_A_UT1_R`[src]

Bits 10:11

`pub fn gen0_a_ut0(&self) -> GEN0_A_UT0_R`[src]

Bits 8:9

`pub fn gen0_a_uteb(&self) -> GEN0_A_UTEB_R`[src]

Bits 6:7

`pub fn gen0_a_utea(&self) -> GEN0_A_UTEA_R`[src]

Bits 4:5

`pub fn gen0_a_utep(&self) -> GEN0_A_UTEP_R`[src]

Bits 2:3

`pub fn gen0_a_utez(&self) -> GEN0_A_UTEZ_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _GEN0_B>>`[src]

`pub fn gen0_b_dt1(&self) -> GEN0_B_DT1_R`[src]

Bits 22:23

`pub fn gen0_b_dt0(&self) -> GEN0_B_DT0_R`[src]

Bits 20:21

`pub fn gen0_b_dteb(&self) -> GEN0_B_DTEB_R`[src]

Bits 18:19

`pub fn gen0_b_dtea(&self) -> GEN0_B_DTEA_R`[src]

Bits 16:17

`pub fn gen0_b_dtep(&self) -> GEN0_B_DTEP_R`[src]

Bits 14:15

`pub fn gen0_b_dtez(&self) -> GEN0_B_DTEZ_R`[src]

Bits 12:13

`pub fn gen0_b_ut1(&self) -> GEN0_B_UT1_R`[src]

Bits 10:11

`pub fn gen0_b_ut0(&self) -> GEN0_B_UT0_R`[src]

Bits 8:9

`pub fn gen0_b_uteb(&self) -> GEN0_B_UTEB_R`[src]

Bits 6:7

`pub fn gen0_b_utea(&self) -> GEN0_B_UTEA_R`[src]

Bits 4:5

`pub fn gen0_b_utep(&self) -> GEN0_B_UTEP_R`[src]

Bits 2:3

`pub fn gen0_b_utez(&self) -> GEN0_B_UTEZ_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _DT0_CFG>>`[src]

`pub fn dt0_clk_sel(&self) -> DT0_CLK_SEL_R`[src]

Bit 17

`pub fn dt0_b_outbypass(&self) -> DT0_B_OUTBYPASS_R`[src]

Bit 16

`pub fn dt0_a_outbypass(&self) -> DT0_A_OUTBYPASS_R`[src]

Bit 15

`pub fn dt0_fed_outinvert(&self) -> DT0_FED_OUTINVERT_R`[src]

Bit 14

`pub fn dt0_red_outinvert(&self) -> DT0_RED_OUTINVERT_R`[src]

Bit 13

`pub fn dt0_fed_insel(&self) -> DT0_FED_INSEL_R`[src]

Bit 12

`pub fn dt0_red_insel(&self) -> DT0_RED_INSEL_R`[src]

Bit 11

`pub fn dt0_b_outswap(&self) -> DT0_B_OUTSWAP_R`[src]

Bit 10

`pub fn dt0_a_outswap(&self) -> DT0_A_OUTSWAP_R`[src]

Bit 9

`pub fn dt0_deb_mode(&self) -> DT0_DEB_MODE_R`[src]

Bit 8

`pub fn dt0_red_upmethod(&self) -> DT0_RED_UPMETHOD_R`[src]

Bits 4:7

`pub fn dt0_fed_upmethod(&self) -> DT0_FED_UPMETHOD_R`[src]

Bits 0:3

`impl R<u32, Reg<u32, _DT0_FED_CFG>>`[src]

`pub fn dt0_fed(&self) -> DT0_FED_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _DT0_RED_CFG>>`[src]

`pub fn dt0_red(&self) -> DT0_RED_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _CARRIER0_CFG>>`[src]

`pub fn carrier0_in_invert(&self) -> CARRIER0_IN_INVERT_R`[src]

Bit 13

`pub fn carrier0_out_invert(&self) -> CARRIER0_OUT_INVERT_R`[src]

Bit 12

`pub fn carrier0_oshwth(&self) -> CARRIER0_OSHWTH_R`[src]

Bits 8:11

`pub fn carrier0_duty(&self) -> CARRIER0_DUTY_R`[src]

Bits 5:7

`pub fn carrier0_prescale(&self) -> CARRIER0_PRESCALE_R`[src]

Bits 1:4

`pub fn carrier0_en(&self) -> CARRIER0_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _FH0_CFG0>>`[src]

`pub fn fh0_b_ost_u(&self) -> FH0_B_OST_U_R`[src]

Bits 22:23

`pub fn fh0_b_ost_d(&self) -> FH0_B_OST_D_R`[src]

Bits 20:21

`pub fn fh0_b_cbc_u(&self) -> FH0_B_CBC_U_R`[src]

Bits 18:19

`pub fn fh0_b_cbc_d(&self) -> FH0_B_CBC_D_R`[src]

Bits 16:17

`pub fn fh0_a_ost_u(&self) -> FH0_A_OST_U_R`[src]

Bits 14:15

`pub fn fh0_a_ost_d(&self) -> FH0_A_OST_D_R`[src]

Bits 12:13

`pub fn fh0_a_cbc_u(&self) -> FH0_A_CBC_U_R`[src]

Bits 10:11

`pub fn fh0_a_cbc_d(&self) -> FH0_A_CBC_D_R`[src]

Bits 8:9

`pub fn fh0_f0_ost(&self) -> FH0_F0_OST_R`[src]

Bit 7

`pub fn fh0_f1_ost(&self) -> FH0_F1_OST_R`[src]

Bit 6

`pub fn fh0_f2_ost(&self) -> FH0_F2_OST_R`[src]

Bit 5

`pub fn fh0_sw_ost(&self) -> FH0_SW_OST_R`[src]

Bit 4

`pub fn fh0_f0_cbc(&self) -> FH0_F0_CBC_R`[src]

Bit 3

`pub fn fh0_f1_cbc(&self) -> FH0_F1_CBC_R`[src]

Bit 2

`pub fn fh0_f2_cbc(&self) -> FH0_F2_CBC_R`[src]

Bit 1

`pub fn fh0_sw_cbc(&self) -> FH0_SW_CBC_R`[src]

Bit 0

`impl R<u32, Reg<u32, _FH0_CFG1>>`[src]

`pub fn fh0_force_ost(&self) -> FH0_FORCE_OST_R`[src]

Bit 4

`pub fn fh0_force_cbc(&self) -> FH0_FORCE_CBC_R`[src]

Bit 3

`pub fn fh0_cbcpulse(&self) -> FH0_CBCPULSE_R`[src]

Bits 1:2

`pub fn fh0_clr_ost(&self) -> FH0_CLR_OST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _FH0_STATUS>>`[src]

`pub fn fh0_ost_on(&self) -> FH0_OST_ON_R`[src]

Bit 1

`pub fn fh0_cbc_on(&self) -> FH0_CBC_ON_R`[src]

Bit 0

`impl R<u32, Reg<u32, _GEN1_STMP_CFG>>`[src]

`pub fn gen1_b_shdw_full(&self) -> GEN1_B_SHDW_FULL_R`[src]

Bit 9

`pub fn gen1_a_shdw_full(&self) -> GEN1_A_SHDW_FULL_R`[src]

Bit 8

`pub fn gen1_b_upmethod(&self) -> GEN1_B_UPMETHOD_R`[src]

Bits 4:7

`pub fn gen1_a_upmethod(&self) -> GEN1_A_UPMETHOD_R`[src]

Bits 0:3

`impl R<u32, Reg<u32, _GEN1_TSTMP_A>>`[src]

`pub fn gen1_a(&self) -> GEN1_A_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _GEN1_TSTMP_B>>`[src]

`pub fn gen1_b(&self) -> GEN1_B_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _GEN1_CFG0>>`[src]

`pub fn gen1_t1_sel(&self) -> GEN1_T1_SEL_R`[src]

Bits 7:9

`pub fn gen1_t0_sel(&self) -> GEN1_T0_SEL_R`[src]

Bits 4:6

`pub fn gen1_cfg_upmethod(&self) -> GEN1_CFG_UPMETHOD_R`[src]

Bits 0:3

`impl R<u32, Reg<u32, _GEN1_FORCE>>`[src]

`pub fn gen1_b_nciforce_mode(&self) -> GEN1_B_NCIFORCE_MODE_R`[src]

Bits 14:15

`pub fn gen1_b_nciforce(&self) -> GEN1_B_NCIFORCE_R`[src]

Bit 13

`pub fn gen1_a_nciforce_mode(&self) -> GEN1_A_NCIFORCE_MODE_R`[src]

Bits 11:12

`pub fn gen1_a_nciforce(&self) -> GEN1_A_NCIFORCE_R`[src]

Bit 10

`pub fn gen1_b_cntuforce_mode(&self) -> GEN1_B_CNTUFORCE_MODE_R`[src]

Bits 8:9

`pub fn gen1_a_cntuforce_mode(&self) -> GEN1_A_CNTUFORCE_MODE_R`[src]

Bits 6:7

`pub fn gen1_cntuforce_upmethod(&self) -> GEN1_CNTUFORCE_UPMETHOD_R`[src]

Bits 0:5

`impl R<u32, Reg<u32, _GEN1_A>>`[src]

`pub fn gen1_a_dt1(&self) -> GEN1_A_DT1_R`[src]

Bits 22:23

`pub fn gen1_a_dt0(&self) -> GEN1_A_DT0_R`[src]

Bits 20:21

`pub fn gen1_a_dteb(&self) -> GEN1_A_DTEB_R`[src]

Bits 18:19

`pub fn gen1_a_dtea(&self) -> GEN1_A_DTEA_R`[src]

Bits 16:17

`pub fn gen1_a_dtep(&self) -> GEN1_A_DTEP_R`[src]

Bits 14:15

`pub fn gen1_a_dtez(&self) -> GEN1_A_DTEZ_R`[src]

Bits 12:13

`pub fn gen1_a_ut1(&self) -> GEN1_A_UT1_R`[src]

Bits 10:11

`pub fn gen1_a_ut0(&self) -> GEN1_A_UT0_R`[src]

Bits 8:9

`pub fn gen1_a_uteb(&self) -> GEN1_A_UTEB_R`[src]

Bits 6:7

`pub fn gen1_a_utea(&self) -> GEN1_A_UTEA_R`[src]

Bits 4:5

`pub fn gen1_a_utep(&self) -> GEN1_A_UTEP_R`[src]

Bits 2:3

`pub fn gen1_a_utez(&self) -> GEN1_A_UTEZ_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _GEN1_B>>`[src]

`pub fn gen1_b_dt1(&self) -> GEN1_B_DT1_R`[src]

Bits 22:23

`pub fn gen1_b_dt0(&self) -> GEN1_B_DT0_R`[src]

Bits 20:21

`pub fn gen1_b_dteb(&self) -> GEN1_B_DTEB_R`[src]

Bits 18:19

`pub fn gen1_b_dtea(&self) -> GEN1_B_DTEA_R`[src]

Bits 16:17

`pub fn gen1_b_dtep(&self) -> GEN1_B_DTEP_R`[src]

Bits 14:15

`pub fn gen1_b_dtez(&self) -> GEN1_B_DTEZ_R`[src]

Bits 12:13

`pub fn gen1_b_ut1(&self) -> GEN1_B_UT1_R`[src]

Bits 10:11

`pub fn gen1_b_ut0(&self) -> GEN1_B_UT0_R`[src]

Bits 8:9

`pub fn gen1_b_uteb(&self) -> GEN1_B_UTEB_R`[src]

Bits 6:7

`pub fn gen1_b_utea(&self) -> GEN1_B_UTEA_R`[src]

Bits 4:5

`pub fn gen1_b_utep(&self) -> GEN1_B_UTEP_R`[src]

Bits 2:3

`pub fn gen1_b_utez(&self) -> GEN1_B_UTEZ_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _DT1_CFG>>`[src]

`pub fn dt1_clk_sel(&self) -> DT1_CLK_SEL_R`[src]

Bit 17

`pub fn dt1_b_outbypass(&self) -> DT1_B_OUTBYPASS_R`[src]

Bit 16

`pub fn dt1_a_outbypass(&self) -> DT1_A_OUTBYPASS_R`[src]

Bit 15

`pub fn dt1_fed_outinvert(&self) -> DT1_FED_OUTINVERT_R`[src]

Bit 14

`pub fn dt1_red_outinvert(&self) -> DT1_RED_OUTINVERT_R`[src]

Bit 13

`pub fn dt1_fed_insel(&self) -> DT1_FED_INSEL_R`[src]

Bit 12

`pub fn dt1_red_insel(&self) -> DT1_RED_INSEL_R`[src]

Bit 11

`pub fn dt1_b_outswap(&self) -> DT1_B_OUTSWAP_R`[src]

Bit 10

`pub fn dt1_a_outswap(&self) -> DT1_A_OUTSWAP_R`[src]

Bit 9

`pub fn dt1_deb_mode(&self) -> DT1_DEB_MODE_R`[src]

Bit 8

`pub fn dt1_red_upmethod(&self) -> DT1_RED_UPMETHOD_R`[src]

Bits 4:7

`pub fn dt1_fed_upmethod(&self) -> DT1_FED_UPMETHOD_R`[src]

Bits 0:3

`impl R<u32, Reg<u32, _DT1_FED_CFG>>`[src]

`pub fn dt1_fed(&self) -> DT1_FED_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _DT1_RED_CFG>>`[src]

`pub fn dt1_red(&self) -> DT1_RED_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _CARRIER1_CFG>>`[src]

`pub fn carrier1_in_invert(&self) -> CARRIER1_IN_INVERT_R`[src]

Bit 13

`pub fn carrier1_out_invert(&self) -> CARRIER1_OUT_INVERT_R`[src]

Bit 12

`pub fn carrier1_oshwth(&self) -> CARRIER1_OSHWTH_R`[src]

Bits 8:11

`pub fn carrier1_duty(&self) -> CARRIER1_DUTY_R`[src]

Bits 5:7

`pub fn carrier1_prescale(&self) -> CARRIER1_PRESCALE_R`[src]

Bits 1:4

`pub fn carrier1_en(&self) -> CARRIER1_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _FH1_CFG0>>`[src]

`pub fn fh1_b_ost_u(&self) -> FH1_B_OST_U_R`[src]

Bits 22:23

`pub fn fh1_b_ost_d(&self) -> FH1_B_OST_D_R`[src]

Bits 20:21

`pub fn fh1_b_cbc_u(&self) -> FH1_B_CBC_U_R`[src]

Bits 18:19

`pub fn fh1_b_cbc_d(&self) -> FH1_B_CBC_D_R`[src]

Bits 16:17

`pub fn fh1_a_ost_u(&self) -> FH1_A_OST_U_R`[src]

Bits 14:15

`pub fn fh1_a_ost_d(&self) -> FH1_A_OST_D_R`[src]

Bits 12:13

`pub fn fh1_a_cbc_u(&self) -> FH1_A_CBC_U_R`[src]

Bits 10:11

`pub fn fh1_a_cbc_d(&self) -> FH1_A_CBC_D_R`[src]

Bits 8:9

`pub fn fh1_f0_ost(&self) -> FH1_F0_OST_R`[src]

Bit 7

`pub fn fh1_f1_ost(&self) -> FH1_F1_OST_R`[src]

Bit 6

`pub fn fh1_f2_ost(&self) -> FH1_F2_OST_R`[src]

Bit 5

`pub fn fh1_sw_ost(&self) -> FH1_SW_OST_R`[src]

Bit 4

`pub fn fh1_f0_cbc(&self) -> FH1_F0_CBC_R`[src]

Bit 3

`pub fn fh1_f1_cbc(&self) -> FH1_F1_CBC_R`[src]

Bit 2

`pub fn fh1_f2_cbc(&self) -> FH1_F2_CBC_R`[src]

Bit 1

`pub fn fh1_sw_cbc(&self) -> FH1_SW_CBC_R`[src]

Bit 0

`impl R<u32, Reg<u32, _FH1_CFG1>>`[src]

`pub fn fh1_force_ost(&self) -> FH1_FORCE_OST_R`[src]

Bit 4

`pub fn fh1_force_cbc(&self) -> FH1_FORCE_CBC_R`[src]

Bit 3

`pub fn fh1_cbcpulse(&self) -> FH1_CBCPULSE_R`[src]

Bits 1:2

`pub fn fh1_clr_ost(&self) -> FH1_CLR_OST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _FH1_STATUS>>`[src]

`pub fn fh1_ost_on(&self) -> FH1_OST_ON_R`[src]

Bit 1

`pub fn fh1_cbc_on(&self) -> FH1_CBC_ON_R`[src]

Bit 0

`impl R<u32, Reg<u32, _GEN2_STMP_CFG>>`[src]

`pub fn gen2_b_shdw_full(&self) -> GEN2_B_SHDW_FULL_R`[src]

Bit 9

`pub fn gen2_a_shdw_full(&self) -> GEN2_A_SHDW_FULL_R`[src]

Bit 8

`pub fn gen2_b_upmethod(&self) -> GEN2_B_UPMETHOD_R`[src]

Bits 4:7

`pub fn gen2_a_upmethod(&self) -> GEN2_A_UPMETHOD_R`[src]

Bits 0:3

`impl R<u32, Reg<u32, _GEN2_TSTMP_A>>`[src]

`pub fn gen2_a(&self) -> GEN2_A_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _GEN2_TSTMP_B>>`[src]

`pub fn gen2_b(&self) -> GEN2_B_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _GEN2_CFG0>>`[src]

`pub fn gen2_t1_sel(&self) -> GEN2_T1_SEL_R`[src]

Bits 7:9

`pub fn gen2_t0_sel(&self) -> GEN2_T0_SEL_R`[src]

Bits 4:6

`pub fn gen2_cfg_upmethod(&self) -> GEN2_CFG_UPMETHOD_R`[src]

Bits 0:3

`impl R<u32, Reg<u32, _GEN2_FORCE>>`[src]

`pub fn gen2_b_nciforce_mode(&self) -> GEN2_B_NCIFORCE_MODE_R`[src]

Bits 14:15

`pub fn gen2_b_nciforce(&self) -> GEN2_B_NCIFORCE_R`[src]

Bit 13

`pub fn gen2_a_nciforce_mode(&self) -> GEN2_A_NCIFORCE_MODE_R`[src]

Bits 11:12

`pub fn gen2_a_nciforce(&self) -> GEN2_A_NCIFORCE_R`[src]

Bit 10

`pub fn gen2_b_cntuforce_mode(&self) -> GEN2_B_CNTUFORCE_MODE_R`[src]

Bits 8:9

`pub fn gen2_a_cntuforce_mode(&self) -> GEN2_A_CNTUFORCE_MODE_R`[src]

Bits 6:7

`pub fn gen2_cntuforce_upmethod(&self) -> GEN2_CNTUFORCE_UPMETHOD_R`[src]

Bits 0:5

`impl R<u32, Reg<u32, _GEN2_A>>`[src]

`pub fn gen2_a_dt1(&self) -> GEN2_A_DT1_R`[src]

Bits 22:23

`pub fn gen2_a_dt0(&self) -> GEN2_A_DT0_R`[src]

Bits 20:21

`pub fn gen2_a_dteb(&self) -> GEN2_A_DTEB_R`[src]

Bits 18:19

`pub fn gen2_a_dtea(&self) -> GEN2_A_DTEA_R`[src]

Bits 16:17

`pub fn gen2_a_dtep(&self) -> GEN2_A_DTEP_R`[src]

Bits 14:15

`pub fn gen2_a_dtez(&self) -> GEN2_A_DTEZ_R`[src]

Bits 12:13

`pub fn gen2_a_ut1(&self) -> GEN2_A_UT1_R`[src]

Bits 10:11

`pub fn gen2_a_ut0(&self) -> GEN2_A_UT0_R`[src]

Bits 8:9

`pub fn gen2_a_uteb(&self) -> GEN2_A_UTEB_R`[src]

Bits 6:7

`pub fn gen2_a_utea(&self) -> GEN2_A_UTEA_R`[src]

Bits 4:5

`pub fn gen2_a_utep(&self) -> GEN2_A_UTEP_R`[src]

Bits 2:3

`pub fn gen2_a_utez(&self) -> GEN2_A_UTEZ_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _GEN2_B>>`[src]

`pub fn gen2_b_dt1(&self) -> GEN2_B_DT1_R`[src]

Bits 22:23

`pub fn gen2_b_dt0(&self) -> GEN2_B_DT0_R`[src]

Bits 20:21

`pub fn gen2_b_dteb(&self) -> GEN2_B_DTEB_R`[src]

Bits 18:19

`pub fn gen2_b_dtea(&self) -> GEN2_B_DTEA_R`[src]

Bits 16:17

`pub fn gen2_b_dtep(&self) -> GEN2_B_DTEP_R`[src]

Bits 14:15

`pub fn gen2_b_dtez(&self) -> GEN2_B_DTEZ_R`[src]

Bits 12:13

`pub fn gen2_b_ut1(&self) -> GEN2_B_UT1_R`[src]

Bits 10:11

`pub fn gen2_b_ut0(&self) -> GEN2_B_UT0_R`[src]

Bits 8:9

`pub fn gen2_b_uteb(&self) -> GEN2_B_UTEB_R`[src]

Bits 6:7

`pub fn gen2_b_utea(&self) -> GEN2_B_UTEA_R`[src]

Bits 4:5

`pub fn gen2_b_utep(&self) -> GEN2_B_UTEP_R`[src]

Bits 2:3

`pub fn gen2_b_utez(&self) -> GEN2_B_UTEZ_R`[src]

Bits 0:1

`impl R<u32, Reg<u32, _DT2_CFG>>`[src]

`pub fn dt2_clk_sel(&self) -> DT2_CLK_SEL_R`[src]

Bit 17

`pub fn dt2_b_outbypass(&self) -> DT2_B_OUTBYPASS_R`[src]

Bit 16

`pub fn dt2_a_outbypass(&self) -> DT2_A_OUTBYPASS_R`[src]

Bit 15

`pub fn dt2_fed_outinvert(&self) -> DT2_FED_OUTINVERT_R`[src]

Bit 14

`pub fn dt2_red_outinvert(&self) -> DT2_RED_OUTINVERT_R`[src]

Bit 13

`pub fn dt2_fed_insel(&self) -> DT2_FED_INSEL_R`[src]

Bit 12

`pub fn dt2_red_insel(&self) -> DT2_RED_INSEL_R`[src]

Bit 11

`pub fn dt2_b_outswap(&self) -> DT2_B_OUTSWAP_R`[src]

Bit 10

`pub fn dt2_a_outswap(&self) -> DT2_A_OUTSWAP_R`[src]

Bit 9

`pub fn dt2_deb_mode(&self) -> DT2_DEB_MODE_R`[src]

Bit 8

`pub fn dt2_red_upmethod(&self) -> DT2_RED_UPMETHOD_R`[src]

Bits 4:7

`pub fn dt2_fed_upmethod(&self) -> DT2_FED_UPMETHOD_R`[src]

Bits 0:3

`impl R<u32, Reg<u32, _DT2_FED_CFG>>`[src]

`pub fn dt2_fed(&self) -> DT2_FED_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _DT2_RED_CFG>>`[src]

`pub fn dt2_red(&self) -> DT2_RED_R`[src]

Bits 0:15

`impl R<u32, Reg<u32, _CARRIER2_CFG>>`[src]

`pub fn carrier2_in_invert(&self) -> CARRIER2_IN_INVERT_R`[src]

Bit 13

`pub fn carrier2_out_invert(&self) -> CARRIER2_OUT_INVERT_R`[src]

Bit 12

`pub fn carrier2_oshwth(&self) -> CARRIER2_OSHWTH_R`[src]

Bits 8:11

`pub fn carrier2_duty(&self) -> CARRIER2_DUTY_R`[src]

Bits 5:7

`pub fn carrier2_prescale(&self) -> CARRIER2_PRESCALE_R`[src]

Bits 1:4

`pub fn carrier2_en(&self) -> CARRIER2_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _FH2_CFG0>>`[src]

`pub fn fh2_b_ost_u(&self) -> FH2_B_OST_U_R`[src]

Bits 22:23

`pub fn fh2_b_ost_d(&self) -> FH2_B_OST_D_R`[src]

Bits 20:21

`pub fn fh2_b_cbc_u(&self) -> FH2_B_CBC_U_R`[src]

Bits 18:19

`pub fn fh2_b_cbc_d(&self) -> FH2_B_CBC_D_R`[src]

Bits 16:17

`pub fn fh2_a_ost_u(&self) -> FH2_A_OST_U_R`[src]

Bits 14:15

`pub fn fh2_a_ost_d(&self) -> FH2_A_OST_D_R`[src]

Bits 12:13

`pub fn fh2_a_cbc_u(&self) -> FH2_A_CBC_U_R`[src]

Bits 10:11

`pub fn fh2_a_cbc_d(&self) -> FH2_A_CBC_D_R`[src]

Bits 8:9

`pub fn fh2_f0_ost(&self) -> FH2_F0_OST_R`[src]

Bit 7

`pub fn fh2_f1_ost(&self) -> FH2_F1_OST_R`[src]

Bit 6

`pub fn fh2_f2_ost(&self) -> FH2_F2_OST_R`[src]

Bit 5

`pub fn fh2_sw_ost(&self) -> FH2_SW_OST_R`[src]

Bit 4

`pub fn fh2_f0_cbc(&self) -> FH2_F0_CBC_R`[src]

Bit 3

`pub fn fh2_f1_cbc(&self) -> FH2_F1_CBC_R`[src]

Bit 2

`pub fn fh2_f2_cbc(&self) -> FH2_F2_CBC_R`[src]

Bit 1

`pub fn fh2_sw_cbc(&self) -> FH2_SW_CBC_R`[src]

Bit 0

`impl R<u32, Reg<u32, _FH2_CFG1>>`[src]

`pub fn fh2_force_ost(&self) -> FH2_FORCE_OST_R`[src]

Bit 4

`pub fn fh2_force_cbc(&self) -> FH2_FORCE_CBC_R`[src]

Bit 3

`pub fn fh2_cbcpulse(&self) -> FH2_CBCPULSE_R`[src]

Bits 1:2

`pub fn fh2_clr_ost(&self) -> FH2_CLR_OST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _FH2_STATUS>>`[src]

`pub fn fh2_ost_on(&self) -> FH2_OST_ON_R`[src]

Bit 1

`pub fn fh2_cbc_on(&self) -> FH2_CBC_ON_R`[src]

Bit 0

`impl R<u32, Reg<u32, _FAULT_DETECT>>`[src]

`pub fn event_f2(&self) -> EVENT_F2_R`[src]

Bit 8

`pub fn event_f1(&self) -> EVENT_F1_R`[src]

Bit 7

`pub fn event_f0(&self) -> EVENT_F0_R`[src]

Bit 6

`pub fn f2_pole(&self) -> F2_POLE_R`[src]

Bit 5

`pub fn f1_pole(&self) -> F1_POLE_R`[src]

Bit 4

`pub fn f0_pole(&self) -> F0_POLE_R`[src]

Bit 3

`pub fn f2_en(&self) -> F2_EN_R`[src]

Bit 2

`pub fn f1_en(&self) -> F1_EN_R`[src]

Bit 1

`pub fn f0_en(&self) -> F0_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CAP_TIMER_CFG>>`[src]

`pub fn cap_sync_sw(&self) -> CAP_SYNC_SW_R`[src]

Bit 5

`pub fn cap_synci_sel(&self) -> CAP_SYNCI_SEL_R`[src]

Bits 2:4

`pub fn cap_synci_en(&self) -> CAP_SYNCI_EN_R`[src]

Bit 1

`pub fn cap_timer_en(&self) -> CAP_TIMER_EN_R`[src]

Bit 0

Bits 1:2

`pub fn cap2_en(&self) -> CAP2_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CAP_CH0>>`[src]

`pub fn cap0_value(&self) -> CAP0_VALUE_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _CAP_CH1>>`[src]

`pub fn cap1_value(&self) -> CAP1_VALUE_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _CAP_CH2>>`[src]

`pub fn cap2_value(&self) -> CAP2_VALUE_R`[src]

Bits 0:31

`impl R<u32, Reg<u32, _CAP_STATUS>>`[src]

`pub fn cap2_edge(&self) -> CAP2_EDGE_R`[src]

Bit 2

`pub fn cap1_edge(&self) -> CAP1_EDGE_R`[src]

Bit 1

`pub fn cap0_edge(&self) -> CAP0_EDGE_R`[src]

Bit 0

`impl R<u32, Reg<u32, _UPDATE_CFG>>`[src]

`pub fn op2_force_up(&self) -> OP2_FORCE_UP_R`[src]

Bit 7

`pub fn op2_up_en(&self) -> OP2_UP_EN_R`[src]

Bit 6

`pub fn op1_force_up(&self) -> OP1_FORCE_UP_R`[src]

Bit 5

`pub fn op1_up_en(&self) -> OP1_UP_EN_R`[src]

Bit 4

`pub fn op0_force_up(&self) -> OP0_FORCE_UP_R`[src]

Bit 3

`pub fn op0_up_en(&self) -> OP0_UP_EN_R`[src]

Bit 2

`pub fn global_force_up(&self) -> GLOBAL_FORCE_UP_R`[src]

Bit 1

`pub fn global_up_en(&self) -> GLOBAL_UP_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _MCMCPWM_INT_ENA_MCPWM>>`[src]

`pub fn cap2_int_ena(&self) -> CAP2_INT_ENA_R`[src]

Bit 29

`pub fn cap1_int_ena(&self) -> CAP1_INT_ENA_R`[src]

Bit 28

`pub fn cap0_int_ena(&self) -> CAP0_INT_ENA_R`[src]

Bit 27

`pub fn fh2_ost_int_ena(&self) -> FH2_OST_INT_ENA_R`[src]

Bit 26

`pub fn fh1_ost_int_ena(&self) -> FH1_OST_INT_ENA_R`[src]

Bit 25

`pub fn fh0_ost_int_ena(&self) -> FH0_OST_INT_ENA_R`[src]

Bit 24

`pub fn fh2_cbc_int_ena(&self) -> FH2_CBC_INT_ENA_R`[src]

Bit 23

`pub fn fh1_cbc_int_ena(&self) -> FH1_CBC_INT_ENA_R`[src]

Bit 22

`pub fn fh0_cbc_int_ena(&self) -> FH0_CBC_INT_ENA_R`[src]

Bit 21

`pub fn op2_teb_int_ena(&self) -> OP2_TEB_INT_ENA_R`[src]

Bit 20

`pub fn op1_teb_int_ena(&self) -> OP1_TEB_INT_ENA_R`[src]

Bit 19

`pub fn op0_teb_int_ena(&self) -> OP0_TEB_INT_ENA_R`[src]

Bit 18

`pub fn op2_tea_int_ena(&self) -> OP2_TEA_INT_ENA_R`[src]

Bit 17

`pub fn op1_tea_int_ena(&self) -> OP1_TEA_INT_ENA_R`[src]

Bit 16

`pub fn op0_tea_int_ena(&self) -> OP0_TEA_INT_ENA_R`[src]

Bit 15

`pub fn fault2_clr_int_ena(&self) -> FAULT2_CLR_INT_ENA_R`[src]

Bit 14

`pub fn fault1_clr_int_ena(&self) -> FAULT1_CLR_INT_ENA_R`[src]

Bit 13

`pub fn fault0_clr_int_ena(&self) -> FAULT0_CLR_INT_ENA_R`[src]

Bit 12

`pub fn fault2_int_ena(&self) -> FAULT2_INT_ENA_R`[src]

Bit 11

`pub fn fault1_int_ena(&self) -> FAULT1_INT_ENA_R`[src]

Bit 10

`pub fn fault0_int_ena(&self) -> FAULT0_INT_ENA_R`[src]

Bit 9

`pub fn timer2_tep_int_ena(&self) -> TIMER2_TEP_INT_ENA_R`[src]

Bit 8

`pub fn timer1_tep_int_ena(&self) -> TIMER1_TEP_INT_ENA_R`[src]

Bit 7

`pub fn timer0_tep_int_ena(&self) -> TIMER0_TEP_INT_ENA_R`[src]

Bit 6

`pub fn timer2_tez_int_ena(&self) -> TIMER2_TEZ_INT_ENA_R`[src]

Bit 5

`pub fn timer1_tez_int_ena(&self) -> TIMER1_TEZ_INT_ENA_R`[src]

Bit 4

`pub fn timer0_tez_int_ena(&self) -> TIMER0_TEZ_INT_ENA_R`[src]

Bit 3

`pub fn timer2_stop_int_ena(&self) -> TIMER2_STOP_INT_ENA_R`[src]

Bit 2

`pub fn timer1_stop_int_ena(&self) -> TIMER1_STOP_INT_ENA_R`[src]

Bit 1

`pub fn timer0_stop_int_ena(&self) -> TIMER0_STOP_INT_ENA_R`[src]

Bit 0

`impl R<u32, Reg<u32, _MCMCPWM_INT_RAW_MCPWM>>`[src]

`pub fn cap2_int_raw(&self) -> CAP2_INT_RAW_R`[src]

Bit 29

`pub fn cap1_int_raw(&self) -> CAP1_INT_RAW_R`[src]

Bit 28

`pub fn cap0_int_raw(&self) -> CAP0_INT_RAW_R`[src]

Bit 27

`pub fn fh2_ost_int_raw(&self) -> FH2_OST_INT_RAW_R`[src]

Bit 26

`pub fn fh1_ost_int_raw(&self) -> FH1_OST_INT_RAW_R`[src]

Bit 25

`pub fn fh0_ost_int_raw(&self) -> FH0_OST_INT_RAW_R`[src]

Bit 24

`pub fn fh2_cbc_int_raw(&self) -> FH2_CBC_INT_RAW_R`[src]

Bit 23

`pub fn fh1_cbc_int_raw(&self) -> FH1_CBC_INT_RAW_R`[src]

Bit 22

`pub fn fh0_cbc_int_raw(&self) -> FH0_CBC_INT_RAW_R`[src]

Bit 21

`pub fn op2_teb_int_raw(&self) -> OP2_TEB_INT_RAW_R`[src]

Bit 20

`pub fn op1_teb_int_raw(&self) -> OP1_TEB_INT_RAW_R`[src]

Bit 19

`pub fn op0_teb_int_raw(&self) -> OP0_TEB_INT_RAW_R`[src]

Bit 18

`pub fn op2_tea_int_raw(&self) -> OP2_TEA_INT_RAW_R`[src]

Bit 17

`pub fn op1_tea_int_raw(&self) -> OP1_TEA_INT_RAW_R`[src]

Bit 16

`pub fn op0_tea_int_raw(&self) -> OP0_TEA_INT_RAW_R`[src]

Bit 15

`pub fn fault2_clr_int_raw(&self) -> FAULT2_CLR_INT_RAW_R`[src]

Bit 14

`pub fn fault1_clr_int_raw(&self) -> FAULT1_CLR_INT_RAW_R`[src]

Bit 13

`pub fn fault0_clr_int_raw(&self) -> FAULT0_CLR_INT_RAW_R`[src]

Bit 12

`pub fn fault2_int_raw(&self) -> FAULT2_INT_RAW_R`[src]

Bit 11

`pub fn fault1_int_raw(&self) -> FAULT1_INT_RAW_R`[src]

Bit 10

`pub fn fault0_int_raw(&self) -> FAULT0_INT_RAW_R`[src]

Bit 9

`pub fn timer2_tep_int_raw(&self) -> TIMER2_TEP_INT_RAW_R`[src]

Bit 8

`pub fn timer1_tep_int_raw(&self) -> TIMER1_TEP_INT_RAW_R`[src]

Bit 7

`pub fn timer0_tep_int_raw(&self) -> TIMER0_TEP_INT_RAW_R`[src]

Bit 6

`pub fn timer2_tez_int_raw(&self) -> TIMER2_TEZ_INT_RAW_R`[src]

Bit 5

`pub fn timer1_tez_int_raw(&self) -> TIMER1_TEZ_INT_RAW_R`[src]

Bit 4

`pub fn timer0_tez_int_raw(&self) -> TIMER0_TEZ_INT_RAW_R`[src]

Bit 3

`pub fn timer2_stop_int_raw(&self) -> TIMER2_STOP_INT_RAW_R`[src]

Bit 2

`pub fn timer1_stop_int_raw(&self) -> TIMER1_STOP_INT_RAW_R`[src]

Bit 1

`pub fn timer0_stop_int_raw(&self) -> TIMER0_STOP_INT_RAW_R`[src]

Bit 0

`impl R<u32, Reg<u32, _MCMCPWM_INT_ST_MCPWM>>`[src]

`pub fn cap2_int_st(&self) -> CAP2_INT_ST_R`[src]

Bit 29

`pub fn cap1_int_st(&self) -> CAP1_INT_ST_R`[src]

Bit 28

`pub fn cap0_int_st(&self) -> CAP0_INT_ST_R`[src]

Bit 27

`pub fn fh2_ost_int_st(&self) -> FH2_OST_INT_ST_R`[src]

Bit 26

`pub fn fh1_ost_int_st(&self) -> FH1_OST_INT_ST_R`[src]

Bit 25

`pub fn fh0_ost_int_st(&self) -> FH0_OST_INT_ST_R`[src]

Bit 24

`pub fn fh2_cbc_int_st(&self) -> FH2_CBC_INT_ST_R`[src]

Bit 23

`pub fn fh1_cbc_int_st(&self) -> FH1_CBC_INT_ST_R`[src]

Bit 22

`pub fn fh0_cbc_int_st(&self) -> FH0_CBC_INT_ST_R`[src]

Bit 21

`pub fn op2_teb_int_st(&self) -> OP2_TEB_INT_ST_R`[src]

Bit 20

`pub fn op1_teb_int_st(&self) -> OP1_TEB_INT_ST_R`[src]

Bit 19

`pub fn op0_teb_int_st(&self) -> OP0_TEB_INT_ST_R`[src]

Bit 18

`pub fn op2_tea_int_st(&self) -> OP2_TEA_INT_ST_R`[src]

Bit 17

`pub fn op1_tea_int_st(&self) -> OP1_TEA_INT_ST_R`[src]

Bit 16

`pub fn op0_tea_int_st(&self) -> OP0_TEA_INT_ST_R`[src]

Bit 15

`pub fn fault2_clr_int_st(&self) -> FAULT2_CLR_INT_ST_R`[src]

Bit 14

`pub fn fault1_clr_int_st(&self) -> FAULT1_CLR_INT_ST_R`[src]

Bit 13

`pub fn fault0_clr_int_st(&self) -> FAULT0_CLR_INT_ST_R`[src]

Bit 12

`pub fn fault2_int_st(&self) -> FAULT2_INT_ST_R`[src]

Bit 11

`pub fn fault1_int_st(&self) -> FAULT1_INT_ST_R`[src]

Bit 10

`pub fn fault0_int_st(&self) -> FAULT0_INT_ST_R`[src]

Bit 9

`pub fn timer2_tep_int_st(&self) -> TIMER2_TEP_INT_ST_R`[src]

Bit 8

`pub fn timer1_tep_int_st(&self) -> TIMER1_TEP_INT_ST_R`[src]

Bit 7

`pub fn timer0_tep_int_st(&self) -> TIMER0_TEP_INT_ST_R`[src]

Bit 6

`pub fn timer2_tez_int_st(&self) -> TIMER2_TEZ_INT_ST_R`[src]

Bit 5

`pub fn timer1_tez_int_st(&self) -> TIMER1_TEZ_INT_ST_R`[src]

Bit 4

`pub fn timer0_tez_int_st(&self) -> TIMER0_TEZ_INT_ST_R`[src]

Bit 3

`pub fn timer2_stop_int_st(&self) -> TIMER2_STOP_INT_ST_R`[src]

Bit 2

`pub fn timer1_stop_int_st(&self) -> TIMER1_STOP_INT_ST_R`[src]

Bit 1

`pub fn timer0_stop_int_st(&self) -> TIMER0_STOP_INT_ST_R`[src]

Bit 0

`impl R<u32, Reg<u32, _MCMCPWM_INT_CLR_MCPWM>>`[src]

`pub fn cap2_int_clr(&self) -> CAP2_INT_CLR_R`[src]

Bit 29

`pub fn cap1_int_clr(&self) -> CAP1_INT_CLR_R`[src]

Bit 28

`pub fn cap0_int_clr(&self) -> CAP0_INT_CLR_R`[src]

Bit 27

`pub fn fh2_ost_int_clr(&self) -> FH2_OST_INT_CLR_R`[src]

Bit 26

`pub fn fh1_ost_int_clr(&self) -> FH1_OST_INT_CLR_R`[src]

Bit 25

`pub fn fh0_ost_int_clr(&self) -> FH0_OST_INT_CLR_R`[src]

Bit 24

`pub fn fh2_cbc_int_clr(&self) -> FH2_CBC_INT_CLR_R`[src]

Bit 23

`pub fn fh1_cbc_int_clr(&self) -> FH1_CBC_INT_CLR_R`[src]

Bit 22

`pub fn fh0_cbc_int_clr(&self) -> FH0_CBC_INT_CLR_R`[src]

Bit 21

`pub fn op2_teb_int_clr(&self) -> OP2_TEB_INT_CLR_R`[src]

Bit 20

`pub fn op1_teb_int_clr(&self) -> OP1_TEB_INT_CLR_R`[src]

Bit 19

`pub fn op0_teb_int_clr(&self) -> OP0_TEB_INT_CLR_R`[src]

Bit 18

`pub fn op2_tea_int_clr(&self) -> OP2_TEA_INT_CLR_R`[src]

Bit 17

`pub fn op1_tea_int_clr(&self) -> OP1_TEA_INT_CLR_R`[src]

Bit 16

`pub fn op0_tea_int_clr(&self) -> OP0_TEA_INT_CLR_R`[src]

Bit 15

`pub fn fault2_clr_int_clr(&self) -> FAULT2_CLR_INT_CLR_R`[src]

Bit 14

`pub fn fault1_clr_int_clr(&self) -> FAULT1_CLR_INT_CLR_R`[src]

Bit 13

`pub fn fault0_clr_int_clr(&self) -> FAULT0_CLR_INT_CLR_R`[src]

Bit 12

`pub fn fault2_int_clr(&self) -> FAULT2_INT_CLR_R`[src]

Bit 11

`pub fn fault1_int_clr(&self) -> FAULT1_INT_CLR_R`[src]

Bit 10

`pub fn fault0_int_clr(&self) -> FAULT0_INT_CLR_R`[src]

Bit 9

`pub fn timer2_tep_int_clr(&self) -> TIMER2_TEP_INT_CLR_R`[src]

Bit 8

`pub fn timer1_tep_int_clr(&self) -> TIMER1_TEP_INT_CLR_R`[src]

Bit 7

`pub fn timer0_tep_int_clr(&self) -> TIMER0_TEP_INT_CLR_R`[src]

Bit 6

`pub fn timer2_tez_int_clr(&self) -> TIMER2_TEZ_INT_CLR_R`[src]

Bit 5

`pub fn timer1_tez_int_clr(&self) -> TIMER1_TEZ_INT_CLR_R`[src]

Bit 4

`pub fn timer0_tez_int_clr(&self) -> TIMER0_TEZ_INT_CLR_R`[src]

Bit 3

`pub fn timer2_stop_int_clr(&self) -> TIMER2_STOP_INT_CLR_R`[src]

Bit 2

`pub fn timer1_stop_int_clr(&self) -> TIMER1_STOP_INT_CLR_R`[src]

Bit 1

`pub fn timer0_stop_int_clr(&self) -> TIMER0_STOP_INT_CLR_R`[src]

Bit 0

`impl R<u32, Reg<u32, _CLK>>`[src]

`pub fn clk_en(&self) -> CLK_EN_R`[src]

Bit 0

`impl R<u32, Reg<u32, _VERSION>>`[src]

`pub fn date(&self) -> DATE_R`[src]

Bits 0:27

Trait Implementations

`impl<U, T, FI> PartialEq<FI> for R<U, T> where U: PartialEq, FI: Copy + Into,` [src]

`fn eq(&self, other: &FI) -> bool`[src]

`#[must_use]fn ne(&self, other: &Rhs) -> bool`1.0.0[src]

Auto Trait Implementations

`impl<U, T> Send for R<U, T> where T: Send, U: Send,`

`impl<U, T> Sync for R<U, T> where T: Sync, U: Sync,`

`impl<U, T> Unpin for R<U, T> where T: Unpin, U: Unpin,`

Blanket Implementations

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`fn type_id(&self) -> TypeId`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> From<T> for T`[src]

`fn from(t: T) -> T`[src]

`impl<T, U> Into for T where U: From<T>,` [src]

`fn into(self) -> U`[src]

`impl<T, U> TryFrom for T where U: Into<T>,` [src]

`type Error = Infallible`

The type returned in the event of a conversion error.

`fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>`[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,` [src]

`type Error = >::Error`

The type returned in the event of a conversion error.

[−][src]Struct esp32::generic::R

Implementations

impl<U, T> R<U, T> where U: Copy, [src]

pub fn bits(&self) -> U[src]

impl<FI> R<bool, FI>[src]

pub fn bit(&self) -> bool[src]

pub fn bit_is_clear(&self) -> bool[src]

pub fn bit_is_set(&self) -> bool[src]

impl R<u32, Reg<u32, _IDLE>>[src]

pub fn idle(&self) -> IDLE_R[src]

impl R<u8, MODE_A>[src]

pub fn variant(&self) -> Variant<u8, MODE_A>[src]

pub fn is_aes128_encrypt(&self) -> bool[src]

pub fn is_aes192_encrypt(&self) -> bool[src]

pub fn is_aes256_encrypt(&self) -> bool[src]

pub fn is_aes128_decrypt(&self) -> bool[src]

pub fn is_aes192_decrypt(&self) -> bool[src]

pub fn is_aes256_decrypt(&self) -> bool[src]

impl R<u32, Reg<u32, _MODE>>[src]

pub fn mode(&self) -> MODE_R[src]

impl R<u32, Reg<u32, _ENDIAN>>[src]

pub fn mode(&self) -> MODE_R[src]

impl R<u32, Reg<u32, _CFG_DATA0>>[src]

pub fn device_id_fn1(&self) -> DEVICE_ID_FN1_R[src]

pub fn user_id_fn1(&self) -> USER_ID_FN1_R[src]

impl R<u32, Reg<u32, _CFG_DATA1>>[src]

pub fn sdio20_conf1(&self) -> SDIO20_CONF1_R[src]

pub fn func2_eps(&self) -> FUNC2_EPS_R[src]

pub fn sdio_ver(&self) -> SDIO_VER_R[src]

pub fn sdio20_conf0(&self) -> SDIO20_CONF0_R[src]

pub fn ioenable1(&self) -> IOENABLE1_R[src]

pub fn emp(&self) -> EMP_R[src]

pub fn func1_eps(&self) -> FUNC1_EPS_R[src]

pub fn cd_disable(&self) -> CD_DISABLE_R[src]

pub fn ioenable2(&self) -> IOENABLE2_R[src]

pub fn sdio_int_mask(&self) -> SDIO_INT_MASK_R[src]

pub fn sdio_ioready2(&self) -> SDIO_IOREADY2_R[src]

pub fn sdio_cd_enable(&self) -> SDIO_CD_ENABLE_R[src]

pub fn highspeed_mode(&self) -> HIGHSPEED_MODE_R[src]

pub fn highspeed_enable(&self) -> HIGHSPEED_ENABLE_R[src]

pub fn sdio_ioready1(&self) -> SDIO_IOREADY1_R[src]

pub fn sdio_enable(&self) -> SDIO_ENABLE_R[src]

impl R<u32, Reg<u32, _CFG_DATA7>>[src]

pub fn sdio_ioready0(&self) -> SDIO_IOREADY0_R[src]

pub fn sdio_rst(&self) -> SDIO_RST_R[src]

pub fn chip_state(&self) -> CHIP_STATE_R[src]

pub fn pin_state(&self) -> PIN_STATE_R[src]

impl R<u32, Reg<u32, _CIS_CONF0>>[src]

pub fn cis_conf_w0(&self) -> CIS_CONF_W0_R[src]

impl R<u32, Reg<u32, _CIS_CONF1>>[src]

pub fn cis_conf_w1(&self) -> CIS_CONF_W1_R[src]

impl R<u32, Reg<u32, _CIS_CONF2>>[src]

pub fn cis_conf_w2(&self) -> CIS_CONF_W2_R[src]

impl R<u32, Reg<u32, _CIS_CONF3>>[src]

pub fn cis_conf_w3(&self) -> CIS_CONF_W3_R[src]

impl R<u32, Reg<u32, _CIS_CONF4>>[src]

pub fn cis_conf_w4(&self) -> CIS_CONF_W4_R[src]

impl R<u32, Reg<u32, _CIS_CONF5>>[src]

pub fn cis_conf_w5(&self) -> CIS_CONF_W5_R[src]

impl R<u32, Reg<u32, _CIS_CONF6>>[src]

pub fn cis_conf_w6(&self) -> CIS_CONF_W6_R[src]

impl R<u32, Reg<u32, _CIS_CONF7>>[src]

pub fn cis_conf_w7(&self) -> CIS_CONF_W7_R[src]

impl R<u32, Reg<u32, _CFG_DATA16>>[src]

pub fn device_id_fn2(&self) -> DEVICE_ID_FN2_R[src]

pub fn user_id_fn2(&self) -> USER_ID_FN2_R[src]

impl R<u32, Reg<u32, _DATE>>[src]

pub fn sdio_date(&self) -> SDIO_DATE_R[src]

impl R<u32, Reg<u32, _CMD>>[src]

pub fn flash_read(&self) -> FLASH_READ_R[src]

pub fn flash_wren(&self) -> FLASH_WREN_R[src]

pub fn flash_wrdi(&self) -> FLASH_WRDI_R[src]

pub fn flash_rdid(&self) -> FLASH_RDID_R[src]

pub fn flash_rdsr(&self) -> FLASH_RDSR_R[src]

pub fn flash_wrsr(&self) -> FLASH_WRSR_R[src]

pub fn flash_pp(&self) -> FLASH_PP_R[src]

pub fn flash_se(&self) -> FLASH_SE_R[src]

pub fn flash_be(&self) -> FLASH_BE_R[src]

pub fn flash_ce(&self) -> FLASH_CE_R[src]

pub fn flash_dp(&self) -> FLASH_DP_R[src]

`impl<U, T> R<U, T> where U: Copy,` [src]

`pub fn bits(&self) -> U`[src]

`impl<FI> R<bool, FI>`[src]

`pub fn bit(&self) -> bool`[src]

`pub fn bit_is_clear(&self) -> bool`[src]

`pub fn bit_is_set(&self) -> bool`[src]

`impl R<u32, Reg<u32, _IDLE>>`[src]

`pub fn idle(&self) -> IDLE_R`[src]

`impl R<u8, MODE_A>`[src]

`pub fn variant(&self) -> Variant<u8, MODE_A>`[src]

`pub fn is_aes128_encrypt(&self) -> bool`[src]

`pub fn is_aes192_encrypt(&self) -> bool`[src]

`pub fn is_aes256_encrypt(&self) -> bool`[src]

`pub fn is_aes128_decrypt(&self) -> bool`[src]

`pub fn is_aes192_decrypt(&self) -> bool`[src]

`pub fn is_aes256_decrypt(&self) -> bool`[src]

`impl R<u32, Reg<u32, _MODE>>`[src]

`pub fn mode(&self) -> MODE_R`[src]

`impl R<u32, Reg<u32, _ENDIAN>>`[src]

`pub fn mode(&self) -> MODE_R`[src]

`impl R<u32, Reg<u32, _CFG_DATA0>>`[src]

`pub fn device_id_fn1(&self) -> DEVICE_ID_FN1_R`[src]

`pub fn user_id_fn1(&self) -> USER_ID_FN1_R`[src]

`impl R<u32, Reg<u32, _CFG_DATA1>>`[src]

`pub fn sdio20_conf1(&self) -> SDIO20_CONF1_R`[src]

`pub fn func2_eps(&self) -> FUNC2_EPS_R`[src]

`pub fn sdio_ver(&self) -> SDIO_VER_R`[src]

`pub fn sdio20_conf0(&self) -> SDIO20_CONF0_R`[src]

`pub fn ioenable1(&self) -> IOENABLE1_R`[src]

`pub fn emp(&self) -> EMP_R`[src]

`pub fn func1_eps(&self) -> FUNC1_EPS_R`[src]

`pub fn cd_disable(&self) -> CD_DISABLE_R`[src]

`pub fn ioenable2(&self) -> IOENABLE2_R`[src]

`pub fn sdio_int_mask(&self) -> SDIO_INT_MASK_R`[src]

`pub fn sdio_ioready2(&self) -> SDIO_IOREADY2_R`[src]

`pub fn sdio_cd_enable(&self) -> SDIO_CD_ENABLE_R`[src]

`pub fn highspeed_mode(&self) -> HIGHSPEED_MODE_R`[src]

`pub fn highspeed_enable(&self) -> HIGHSPEED_ENABLE_R`[src]

`pub fn sdio_ioready1(&self) -> SDIO_IOREADY1_R`[src]

`pub fn sdio_enable(&self) -> SDIO_ENABLE_R`[src]

`impl R<u32, Reg<u32, _CFG_DATA7>>`[src]

`pub fn sdio_ioready0(&self) -> SDIO_IOREADY0_R`[src]

`pub fn sdio_rst(&self) -> SDIO_RST_R`[src]

`pub fn chip_state(&self) -> CHIP_STATE_R`[src]

`pub fn pin_state(&self) -> PIN_STATE_R`[src]

`impl R<u32, Reg<u32, _CIS_CONF0>>`[src]

`pub fn cis_conf_w0(&self) -> CIS_CONF_W0_R`[src]

`impl R<u32, Reg<u32, _CIS_CONF1>>`[src]

`pub fn cis_conf_w1(&self) -> CIS_CONF_W1_R`[src]

`impl R<u32, Reg<u32, _CIS_CONF2>>`[src]

`pub fn cis_conf_w2(&self) -> CIS_CONF_W2_R`[src]

`impl R<u32, Reg<u32, _CIS_CONF3>>`[src]

`pub fn cis_conf_w3(&self) -> CIS_CONF_W3_R`[src]

`impl R<u32, Reg<u32, _CIS_CONF4>>`[src]

`pub fn cis_conf_w4(&self) -> CIS_CONF_W4_R`[src]

`impl R<u32, Reg<u32, _CIS_CONF5>>`[src]

`pub fn cis_conf_w5(&self) -> CIS_CONF_W5_R`[src]

`impl R<u32, Reg<u32, _CIS_CONF6>>`[src]

`pub fn cis_conf_w6(&self) -> CIS_CONF_W6_R`[src]

`impl R<u32, Reg<u32, _CIS_CONF7>>`[src]

`pub fn cis_conf_w7(&self) -> CIS_CONF_W7_R`[src]

`impl R<u32, Reg<u32, _CFG_DATA16>>`[src]

`pub fn device_id_fn2(&self) -> DEVICE_ID_FN2_R`[src]

`pub fn user_id_fn2(&self) -> USER_ID_FN2_R`[src]

`impl R<u32, Reg<u32, _DATE>>`[src]

`pub fn sdio_date(&self) -> SDIO_DATE_R`[src]

`impl R<u32, Reg<u32, _CMD>>`[src]

`pub fn flash_read(&self) -> FLASH_READ_R`[src]

`pub fn flash_wren(&self) -> FLASH_WREN_R`[src]

`pub fn flash_wrdi(&self) -> FLASH_WRDI_R`[src]

`pub fn flash_rdid(&self) -> FLASH_RDID_R`[src]

`pub fn flash_rdsr(&self) -> FLASH_RDSR_R`[src]

`pub fn flash_wrsr(&self) -> FLASH_WRSR_R`[src]

`pub fn flash_pp(&self) -> FLASH_PP_R`[src]

`pub fn flash_se(&self) -> FLASH_SE_R`[src]

`pub fn flash_be(&self) -> FLASH_BE_R`[src]

`pub fn flash_ce(&self) -> FLASH_CE_R`[src]

`pub fn flash_dp(&self) -> FLASH_DP_R`[src]

`pub fn flash_res(&self) -> FLASH_RES_R`[src]

`pub fn flash_hpm(&self) -> FLASH_HPM_R`[src]