[−][src]Module esp32::slc
SLC
Modules
| _0_done_dscr_addr | SLC_0_DONE_DSCR_ADDR |
| _0_dscr_cnt | SLC_0_DSCR_CNT |
| _0_dscr_rec_conf | SLC_0_DSCR_REC_CONF |
| _0_eof_start_des | SLC_0_EOF_START_DES |
| _0_len_conf | SLC_0_LEN_CONF |
| _0_len_lim_conf | SLC_0_LEN_LIM_CONF |
| _0_length | SLC_0_LENGTH |
| _0_push_dscr_addr | SLC_0_PUSH_DSCR_ADDR |
| _0_rxlink_dscr | SLC_0_RXLINK_DSCR |
| _0_rxlink_dscr_bf0 | SLC_0_RXLINK_DSCR_BF0 |
| _0_rxlink_dscr_bf1 | SLC_0_RXLINK_DSCR_BF1 |
| _0_rxpkt_e_dscr | SLC_0_RXPKT_E_DSCR |
| _0_rxpkt_h_dscr | SLC_0_RXPKT_H_DSCR |
| _0_rxpktu_e_dscr | SLC_0_RXPKTU_E_DSCR |
| _0_rxpktu_h_dscr | SLC_0_RXPKTU_H_DSCR |
| _0_state0 | SLC_0_STATE0 |
| _0_state1 | SLC_0_STATE1 |
| _0_sub_start_des | SLC_0_SUB_START_DES |
| _0_to_eof_bfr_des_addr | SLC_0_TO_EOF_BFR_DES_ADDR |
| _0_to_eof_des_addr | SLC_0_TO_EOF_DES_ADDR |
| _0_tx_eof_des_addr | SLC_0_TX_EOF_DES_ADDR |
| _0_tx_erreof_des_addr | SLC_0_TX_ERREOF_DES_ADDR |
| _0_txlink_dscr | SLC_0_TXLINK_DSCR |
| _0_txlink_dscr_bf0 | SLC_0_TXLINK_DSCR_BF0 |
| _0_txlink_dscr_bf1 | SLC_0_TXLINK_DSCR_BF1 |
| _0_txpkt_e_dscr | SLC_0_TXPKT_E_DSCR |
| _0_txpkt_h_dscr | SLC_0_TXPKT_H_DSCR |
| _0_txpktu_e_dscr | SLC_0_TXPKTU_E_DSCR |
| _0_txpktu_h_dscr | SLC_0_TXPKTU_H_DSCR |
| _0int_clr | SLC_0INT_CLR |
| _0int_ena | SLC_0INT_ENA |
| _0int_ena1 | SLC_0INT_ENA1 |
| _0int_raw | SLC_0INT_RAW |
| _0int_st | SLC_0INT_ST |
| _0int_st1 | SLC_0INT_ST1 |
| _0rx_link | SLC_0RX_LINK |
| _0rxfifo_push | SLC_0RXFIFO_PUSH |
| _0token0 | SLC_0TOKEN0 |
| _0token1 | SLC_0TOKEN1 |
| _0tx_link | SLC_0TX_LINK |
| _0txfifo_pop | SLC_0TXFIFO_POP |
| _1_rxlink_dscr | SLC_1_RXLINK_DSCR |
| _1_rxlink_dscr_bf0 | SLC_1_RXLINK_DSCR_BF0 |
| _1_rxlink_dscr_bf1 | SLC_1_RXLINK_DSCR_BF1 |
| _1_state0 | SLC_1_STATE0 |
| _1_state1 | SLC_1_STATE1 |
| _1_to_eof_bfr_des_addr | SLC_1_TO_EOF_BFR_DES_ADDR |
| _1_to_eof_des_addr | SLC_1_TO_EOF_DES_ADDR |
| _1_tx_eof_des_addr | SLC_1_TX_EOF_DES_ADDR |
| _1_tx_erreof_des_addr | SLC_1_TX_ERREOF_DES_ADDR |
| _1_txlink_dscr | SLC_1_TXLINK_DSCR |
| _1_txlink_dscr_bf0 | SLC_1_TXLINK_DSCR_BF0 |
| _1_txlink_dscr_bf1 | SLC_1_TXLINK_DSCR_BF1 |
| _1int_clr | SLC_1INT_CLR |
| _1int_ena | SLC_1INT_ENA |
| _1int_ena1 | SLC_1INT_ENA1 |
| _1int_raw | SLC_1INT_RAW |
| _1int_st | SLC_1INT_ST |
| _1int_st1 | SLC_1INT_ST1 |
| _1rx_link | SLC_1RX_LINK |
| _1rxfifo_push | SLC_1RXFIFO_PUSH |
| _1token0 | SLC_1TOKEN0 |
| _1token1 | SLC_1TOKEN1 |
| _1tx_link | SLC_1TX_LINK |
| _1txfifo_pop | SLC_1TXFIFO_POP |
| ahb_test | SLC_AHB_TEST |
| bridge_conf | SLC_BRIDGE_CONF |
| cmd_infor0 | SLC_CMD_INFOR0 |
| cmd_infor1 | SLC_CMD_INFOR1 |
| conf0 | SLC_CONF0 |
| conf1 | SLC_CONF1 |
| date | SLC_DATE |
| id | SLC_ID |
| intvec_tohost | SLC_INTVEC_TOHOST |
| rx_dscr_conf | SLC_RX_DSCR_CONF |
| rx_status | SLC_RX_STATUS |
| sdio_crc_st0 | SLC_SDIO_CRC_ST0 |
| sdio_crc_st1 | SLC_SDIO_CRC_ST1 |
| sdio_st | SLC_SDIO_ST |
| seq_position | SLC_SEQ_POSITION |
| token_lat | SLC_TOKEN_LAT |
| tx_dscr_conf | SLC_TX_DSCR_CONF |
| tx_status | SLC_TX_STATUS |
Structs
| RegisterBlock | Register block |
Type Definitions
| AHB_TEST | SLC_AHB_TEST |
| BRIDGE_CONF | SLC_BRIDGE_CONF |
| CMD_INFOR0 | SLC_CMD_INFOR0 |
| CMD_INFOR1 | SLC_CMD_INFOR1 |
| CONF0 | SLC_CONF0 |
| CONF1 | SLC_CONF1 |
| DATE | SLC_DATE |
| ID | SLC_ID |
| INTVEC_TOHOST | SLC_INTVEC_TOHOST |
| RX_DSCR_CONF | SLC_RX_DSCR_CONF |
| RX_STATUS | SLC_RX_STATUS |
| SDIO_CRC_ST0 | SLC_SDIO_CRC_ST0 |
| SDIO_CRC_ST1 | SLC_SDIO_CRC_ST1 |
| SDIO_ST | SLC_SDIO_ST |
| SEQ_POSITION | SLC_SEQ_POSITION |
| TOKEN_LAT | SLC_TOKEN_LAT |
| TX_DSCR_CONF | SLC_TX_DSCR_CONF |
| TX_STATUS | SLC_TX_STATUS |
| _0INT_CLR | SLC_0INT_CLR |
| _0INT_ENA | SLC_0INT_ENA |
| _0INT_ENA1 | SLC_0INT_ENA1 |
| _0INT_RAW | SLC_0INT_RAW |
| _0INT_ST | SLC_0INT_ST |
| _0INT_ST1 | SLC_0INT_ST1 |
| _0RXFIFO_PUSH | SLC_0RXFIFO_PUSH |
| _0RX_LINK | SLC_0RX_LINK |
| _0TOKEN0 | SLC_0TOKEN0 |
| _0TOKEN1 | SLC_0TOKEN1 |
| _0TXFIFO_POP | SLC_0TXFIFO_POP |
| _0TX_LINK | SLC_0TX_LINK |
| _0_DONE_DSCR_ADDR | SLC_0_DONE_DSCR_ADDR |
| _0_DSCR_CNT | SLC_0_DSCR_CNT |
| _0_DSCR_REC_CONF | SLC_0_DSCR_REC_CONF |
| _0_EOF_START_DES | SLC_0_EOF_START_DES |
| _0_LENGTH | SLC_0_LENGTH |
| _0_LEN_CONF | SLC_0_LEN_CONF |
| _0_LEN_LIM_CONF | SLC_0_LEN_LIM_CONF |
| _0_PUSH_DSCR_ADDR | SLC_0_PUSH_DSCR_ADDR |
| _0_RXLINK_DSCR | SLC_0_RXLINK_DSCR |
| _0_RXLINK_DSCR_BF0 | SLC_0_RXLINK_DSCR_BF0 |
| _0_RXLINK_DSCR_BF1 | SLC_0_RXLINK_DSCR_BF1 |
| _0_RXPKTU_E_DSCR | SLC_0_RXPKTU_E_DSCR |
| _0_RXPKTU_H_DSCR | SLC_0_RXPKTU_H_DSCR |
| _0_RXPKT_E_DSCR | SLC_0_RXPKT_E_DSCR |
| _0_RXPKT_H_DSCR | SLC_0_RXPKT_H_DSCR |
| _0_STATE0 | SLC_0_STATE0 |
| _0_STATE1 | SLC_0_STATE1 |
| _0_SUB_START_DES | SLC_0_SUB_START_DES |
| _0_TO_EOF_BFR_DES_ADDR | SLC_0_TO_EOF_BFR_DES_ADDR |
| _0_TO_EOF_DES_ADDR | SLC_0_TO_EOF_DES_ADDR |
| _0_TXLINK_DSCR | SLC_0_TXLINK_DSCR |
| _0_TXLINK_DSCR_BF0 | SLC_0_TXLINK_DSCR_BF0 |
| _0_TXLINK_DSCR_BF1 | SLC_0_TXLINK_DSCR_BF1 |
| _0_TXPKTU_E_DSCR | SLC_0_TXPKTU_E_DSCR |
| _0_TXPKTU_H_DSCR | SLC_0_TXPKTU_H_DSCR |
| _0_TXPKT_E_DSCR | SLC_0_TXPKT_E_DSCR |
| _0_TXPKT_H_DSCR | SLC_0_TXPKT_H_DSCR |
| _0_TX_EOF_DES_ADDR | SLC_0_TX_EOF_DES_ADDR |
| _0_TX_ERREOF_DES_ADDR | SLC_0_TX_ERREOF_DES_ADDR |
| _1INT_CLR | SLC_1INT_CLR |
| _1INT_ENA | SLC_1INT_ENA |
| _1INT_ENA1 | SLC_1INT_ENA1 |
| _1INT_RAW | SLC_1INT_RAW |
| _1INT_ST | SLC_1INT_ST |
| _1INT_ST1 | SLC_1INT_ST1 |
| _1RXFIFO_PUSH | SLC_1RXFIFO_PUSH |
| _1RX_LINK | SLC_1RX_LINK |
| _1TOKEN0 | SLC_1TOKEN0 |
| _1TOKEN1 | SLC_1TOKEN1 |
| _1TXFIFO_POP | SLC_1TXFIFO_POP |
| _1TX_LINK | SLC_1TX_LINK |
| _1_RXLINK_DSCR | SLC_1_RXLINK_DSCR |
| _1_RXLINK_DSCR_BF0 | SLC_1_RXLINK_DSCR_BF0 |
| _1_RXLINK_DSCR_BF1 | SLC_1_RXLINK_DSCR_BF1 |
| _1_STATE0 | SLC_1_STATE0 |
| _1_STATE1 | SLC_1_STATE1 |
| _1_TO_EOF_BFR_DES_ADDR | SLC_1_TO_EOF_BFR_DES_ADDR |
| _1_TO_EOF_DES_ADDR | SLC_1_TO_EOF_DES_ADDR |
| _1_TXLINK_DSCR | SLC_1_TXLINK_DSCR |
| _1_TXLINK_DSCR_BF0 | SLC_1_TXLINK_DSCR_BF0 |
| _1_TXLINK_DSCR_BF1 | SLC_1_TXLINK_DSCR_BF1 |
| _1_TX_EOF_DES_ADDR | SLC_1_TX_EOF_DES_ADDR |
| _1_TX_ERREOF_DES_ADDR | SLC_1_TX_ERREOF_DES_ADDR |