[][src]Struct esp32::spi::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub cmd: Reg<CMD_SPEC>,
    pub ctrl: Reg<CTRL_SPEC>,
    pub ctrl1: Reg<CTRL1_SPEC>,
    pub rd_status: Reg<RD_STATUS_SPEC>,
    pub ctrl2: Reg<CTRL2_SPEC>,
    pub clock: Reg<CLOCK_SPEC>,
    pub user: Reg<USER_SPEC>,
    pub user1: Reg<USER1_SPEC>,
    pub user2: Reg<USER2_SPEC>,
    pub mosi_dlen: Reg<MOSI_DLEN_SPEC>,
    pub miso_dlen: Reg<MISO_DLEN_SPEC>,
    pub slv_wr_status: Reg<SLV_WR_STATUS_SPEC>,
    pub pin: Reg<PIN_SPEC>,
    pub slave: Reg<SLAVE_SPEC>,
    pub slave1: Reg<SLAVE1_SPEC>,
    pub slave2: Reg<SLAVE2_SPEC>,
    pub slave3: Reg<SLAVE3_SPEC>,
    pub slv_wrbuf_dlen: Reg<SLV_WRBUF_DLEN_SPEC>,
    pub slv_rdbuf_dlen: Reg<SLV_RDBUF_DLEN_SPEC>,
    pub cache_fctrl: Reg<CACHE_FCTRL_SPEC>,
    pub cache_sctrl: Reg<CACHE_SCTRL_SPEC>,
    pub sram_cmd: Reg<SRAM_CMD_SPEC>,
    pub sram_drd_cmd: Reg<SRAM_DRD_CMD_SPEC>,
    pub sram_dwr_cmd: Reg<SRAM_DWR_CMD_SPEC>,
    pub slv_rd_bit: Reg<SLV_RD_BIT_SPEC>,
    pub w: [Reg<W_SPEC>; 16],
    pub tx_crc: Reg<TX_CRC_SPEC>,
    pub ext0: Reg<EXT0_SPEC>,
    pub ext1: Reg<EXT1_SPEC>,
    pub ext2: Reg<EXT2_SPEC>,
    pub ext3: Reg<EXT3_SPEC>,
    pub dma_conf: Reg<DMA_CONF_SPEC>,
    pub dma_out_link: Reg<DMA_OUT_LINK_SPEC>,
    pub dma_in_link: Reg<DMA_IN_LINK_SPEC>,
    pub dma_status: Reg<DMA_STATUS_SPEC>,
    pub dma_int_ena: Reg<DMA_INT_ENA_SPEC>,
    pub dma_int_raw: Reg<DMA_INT_RAW_SPEC>,
    pub dma_int_st: Reg<DMA_INT_ST_SPEC>,
    pub dma_int_clr: Reg<DMA_INT_CLR_SPEC>,
    pub in_err_eof_des_addr: Reg<IN_ERR_EOF_DES_ADDR_SPEC>,
    pub in_suc_eof_des_addr: Reg<IN_SUC_EOF_DES_ADDR_SPEC>,
    pub inlink_dscr: Reg<INLINK_DSCR_SPEC>,
    pub inlink_dscr_bf0: Reg<INLINK_DSCR_BF0_SPEC>,
    pub inlink_dscr_bf1: Reg<INLINK_DSCR_BF1_SPEC>,
    pub out_eof_bfr_des_addr: Reg<OUT_EOF_BFR_DES_ADDR_SPEC>,
    pub out_eof_des_addr: Reg<OUT_EOF_DES_ADDR_SPEC>,
    pub outlink_dscr: Reg<OUTLINK_DSCR_SPEC>,
    pub outlink_dscr_bf0: Reg<OUTLINK_DSCR_BF0_SPEC>,
    pub outlink_dscr_bf1: Reg<OUTLINK_DSCR_BF1_SPEC>,
    pub dma_rstatus: Reg<DMA_RSTATUS_SPEC>,
    pub dma_tstatus: Reg<DMA_TSTATUS_SPEC>,
    pub date: Reg<DATE_SPEC>,
    // some fields omitted
}

Register block

Fields

cmd: Reg<CMD_SPEC>

0x00 - SPI_CMD

ctrl: Reg<CTRL_SPEC>

0x08 - SPI_CTRL

ctrl1: Reg<CTRL1_SPEC>

0x0c - SPI_CTRL1

rd_status: Reg<RD_STATUS_SPEC>

0x10 - SPI_RD_STATUS

ctrl2: Reg<CTRL2_SPEC>

0x14 - SPI_CTRL2

clock: Reg<CLOCK_SPEC>

0x18 - SPI_CLOCK

user: Reg<USER_SPEC>

0x1c - SPI_USER

user1: Reg<USER1_SPEC>

0x20 - SPI_USER1

user2: Reg<USER2_SPEC>

0x24 - SPI_USER2

mosi_dlen: Reg<MOSI_DLEN_SPEC>

0x28 - SPI_MOSI_DLEN

miso_dlen: Reg<MISO_DLEN_SPEC>

0x2c - SPI_MISO_DLEN

slv_wr_status: Reg<SLV_WR_STATUS_SPEC>

0x30 - SPI_SLV_WR_STATUS

pin: Reg<PIN_SPEC>

0x34 - SPI_PIN

slave: Reg<SLAVE_SPEC>

0x38 - SPI_SLAVE

slave1: Reg<SLAVE1_SPEC>

0x3c - SPI_SLAVE1

slave2: Reg<SLAVE2_SPEC>

0x40 - SPI_SLAVE2

slave3: Reg<SLAVE3_SPEC>

0x44 - SPI_SLAVE3

slv_wrbuf_dlen: Reg<SLV_WRBUF_DLEN_SPEC>

0x48 - SPI_SLV_WRBUF_DLEN

slv_rdbuf_dlen: Reg<SLV_RDBUF_DLEN_SPEC>

0x4c - SPI_SLV_RDBUF_DLEN

cache_fctrl: Reg<CACHE_FCTRL_SPEC>

0x50 - SPI_CACHE_FCTRL

cache_sctrl: Reg<CACHE_SCTRL_SPEC>

0x54 - SPI_CACHE_SCTRL

sram_cmd: Reg<SRAM_CMD_SPEC>

0x58 - SPI_SRAM_CMD

sram_drd_cmd: Reg<SRAM_DRD_CMD_SPEC>

0x5c - SPI_SRAM_DRD_CMD

sram_dwr_cmd: Reg<SRAM_DWR_CMD_SPEC>

0x60 - SPI_SRAM_DWR_CMD

slv_rd_bit: Reg<SLV_RD_BIT_SPEC>

0x64 - SPI_SLV_RD_BIT

w: [Reg<W_SPEC>; 16]

0x80 - SPI_W0

tx_crc: Reg<TX_CRC_SPEC>

0xc0 - SPI_TX_CRC

ext0: Reg<EXT0_SPEC>

0xf0 - SPI_EXT0

ext1: Reg<EXT1_SPEC>

0xf4 - SPI_EXT1

ext2: Reg<EXT2_SPEC>

0xf8 - SPI_EXT2

ext3: Reg<EXT3_SPEC>

0xfc - SPI_EXT3

dma_conf: Reg<DMA_CONF_SPEC>

0x100 - SPI_DMA_CONF

dma_out_link: Reg<DMA_OUT_LINK_SPEC>

0x104 - SPI_DMA_OUT_LINK

dma_in_link: Reg<DMA_IN_LINK_SPEC>

0x108 - SPI_DMA_IN_LINK

dma_status: Reg<DMA_STATUS_SPEC>

0x10c - SPI_DMA_STATUS

dma_int_ena: Reg<DMA_INT_ENA_SPEC>

0x110 - SPI_DMA_INT_ENA

dma_int_raw: Reg<DMA_INT_RAW_SPEC>

0x114 - SPI_DMA_INT_RAW

dma_int_st: Reg<DMA_INT_ST_SPEC>

0x118 - SPI_DMA_INT_ST

dma_int_clr: Reg<DMA_INT_CLR_SPEC>

0x11c - SPI_DMA_INT_CLR

in_err_eof_des_addr: Reg<IN_ERR_EOF_DES_ADDR_SPEC>

0x120 - SPI_IN_ERR_EOF_DES_ADDR

in_suc_eof_des_addr: Reg<IN_SUC_EOF_DES_ADDR_SPEC>

0x124 - SPI_IN_SUC_EOF_DES_ADDR

inlink_dscr: Reg<INLINK_DSCR_SPEC>

0x128 - SPI_INLINK_DSCR

inlink_dscr_bf0: Reg<INLINK_DSCR_BF0_SPEC>

0x12c - SPI_INLINK_DSCR_BF0

inlink_dscr_bf1: Reg<INLINK_DSCR_BF1_SPEC>

0x130 - SPI_INLINK_DSCR_BF1

out_eof_bfr_des_addr: Reg<OUT_EOF_BFR_DES_ADDR_SPEC>

0x134 - SPI_OUT_EOF_BFR_DES_ADDR

out_eof_des_addr: Reg<OUT_EOF_DES_ADDR_SPEC>

0x138 - SPI_OUT_EOF_DES_ADDR

outlink_dscr: Reg<OUTLINK_DSCR_SPEC>

0x13c - SPI_OUTLINK_DSCR

outlink_dscr_bf0: Reg<OUTLINK_DSCR_BF0_SPEC>

0x140 - SPI_OUTLINK_DSCR_BF0

outlink_dscr_bf1: Reg<OUTLINK_DSCR_BF1_SPEC>

0x144 - SPI_OUTLINK_DSCR_BF1

dma_rstatus: Reg<DMA_RSTATUS_SPEC>

0x148 - SPI_DMA_RSTATUS

dma_tstatus: Reg<DMA_TSTATUS_SPEC>

0x14c - SPI_DMA_TSTATUS

date: Reg<DATE_SPEC>

0x3fc - SPI_DATE

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