#![macro_use]
use core::sync::atomic::{compiler_fence, Ordering};
use embassy_hal_internal::{into_ref, PeripheralRef};
use crate::gpio::sealed::Pin as _;
use crate::gpio::{AnyPin, Pin as GpioPin, PselBits};
use crate::ppi::{Event, Task};
use crate::util::slice_in_ram_or;
use crate::{interrupt, pac, Peripheral};
pub struct SimplePwm<'d, T: Instance> {
_peri: PeripheralRef<'d, T>,
duty: [u16; 4],
ch0: Option<PeripheralRef<'d, AnyPin>>,
ch1: Option<PeripheralRef<'d, AnyPin>>,
ch2: Option<PeripheralRef<'d, AnyPin>>,
ch3: Option<PeripheralRef<'d, AnyPin>>,
}
pub struct SequencePwm<'d, T: Instance> {
_peri: PeripheralRef<'d, T>,
ch0: Option<PeripheralRef<'d, AnyPin>>,
ch1: Option<PeripheralRef<'d, AnyPin>>,
ch2: Option<PeripheralRef<'d, AnyPin>>,
ch3: Option<PeripheralRef<'d, AnyPin>>,
}
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[non_exhaustive]
pub enum Error {
SequenceTooLong,
SequenceTimesAtLeastOne,
BufferNotInRAM,
}
const MAX_SEQUENCE_LEN: usize = 32767;
impl<'d, T: Instance> SequencePwm<'d, T> {
#[allow(unused_unsafe)]
pub fn new_1ch(
pwm: impl Peripheral<P = T> + 'd,
ch0: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
) -> Result<Self, Error> {
into_ref!(ch0);
Self::new_inner(pwm, Some(ch0.map_into()), None, None, None, config)
}
#[allow(unused_unsafe)]
pub fn new_2ch(
pwm: impl Peripheral<P = T> + 'd,
ch0: impl Peripheral<P = impl GpioPin> + 'd,
ch1: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
) -> Result<Self, Error> {
into_ref!(ch0, ch1);
Self::new_inner(pwm, Some(ch0.map_into()), Some(ch1.map_into()), None, None, config)
}
#[allow(unused_unsafe)]
pub fn new_3ch(
pwm: impl Peripheral<P = T> + 'd,
ch0: impl Peripheral<P = impl GpioPin> + 'd,
ch1: impl Peripheral<P = impl GpioPin> + 'd,
ch2: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
) -> Result<Self, Error> {
into_ref!(ch0, ch1, ch2);
Self::new_inner(
pwm,
Some(ch0.map_into()),
Some(ch1.map_into()),
Some(ch2.map_into()),
None,
config,
)
}
#[allow(unused_unsafe)]
pub fn new_4ch(
pwm: impl Peripheral<P = T> + 'd,
ch0: impl Peripheral<P = impl GpioPin> + 'd,
ch1: impl Peripheral<P = impl GpioPin> + 'd,
ch2: impl Peripheral<P = impl GpioPin> + 'd,
ch3: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
) -> Result<Self, Error> {
into_ref!(ch0, ch1, ch2, ch3);
Self::new_inner(
pwm,
Some(ch0.map_into()),
Some(ch1.map_into()),
Some(ch2.map_into()),
Some(ch3.map_into()),
config,
)
}
fn new_inner(
_pwm: impl Peripheral<P = T> + 'd,
ch0: Option<PeripheralRef<'d, AnyPin>>,
ch1: Option<PeripheralRef<'d, AnyPin>>,
ch2: Option<PeripheralRef<'d, AnyPin>>,
ch3: Option<PeripheralRef<'d, AnyPin>>,
config: Config,
) -> Result<Self, Error> {
into_ref!(_pwm);
let r = T::regs();
if let Some(pin) = &ch0 {
pin.set_low();
pin.conf().write(|w| w.dir().output());
}
if let Some(pin) = &ch1 {
pin.set_low();
pin.conf().write(|w| w.dir().output());
}
if let Some(pin) = &ch2 {
pin.set_low();
pin.conf().write(|w| w.dir().output());
}
if let Some(pin) = &ch3 {
pin.set_low();
pin.conf().write(|w| w.dir().output());
}
r.psel.out[0].write(|w| unsafe { w.bits(ch0.psel_bits()) });
r.psel.out[1].write(|w| unsafe { w.bits(ch1.psel_bits()) });
r.psel.out[2].write(|w| unsafe { w.bits(ch2.psel_bits()) });
r.psel.out[3].write(|w| unsafe { w.bits(ch3.psel_bits()) });
r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
r.shorts.reset();
r.events_stopped.reset();
r.events_loopsdone.reset();
r.events_seqend[0].reset();
r.events_seqend[1].reset();
r.events_pwmperiodend.reset();
r.events_seqstarted[0].reset();
r.events_seqstarted[1].reset();
r.decoder.write(|w| {
w.load().bits(config.sequence_load as u8);
w.mode().refresh_count()
});
r.mode.write(|w| match config.counter_mode {
CounterMode::UpAndDown => w.updown().up_and_down(),
CounterMode::Up => w.updown().up(),
});
r.prescaler.write(|w| w.prescaler().bits(config.prescaler as u8));
r.countertop.write(|w| unsafe { w.countertop().bits(config.max_duty) });
Ok(Self {
_peri: _pwm,
ch0,
ch1,
ch2,
ch3,
})
}
#[inline(always)]
pub fn event_stopped(&self) -> Event<'d> {
let r = T::regs();
Event::from_reg(&r.events_stopped)
}
#[inline(always)]
pub fn event_loops_done(&self) -> Event<'d> {
let r = T::regs();
Event::from_reg(&r.events_loopsdone)
}
#[inline(always)]
pub fn event_pwm_period_end(&self) -> Event<'d> {
let r = T::regs();
Event::from_reg(&r.events_pwmperiodend)
}
#[inline(always)]
pub fn event_seq_end(&self) -> Event<'d> {
let r = T::regs();
Event::from_reg(&r.events_seqend[0])
}
#[inline(always)]
pub fn event_seq1_end(&self) -> Event<'d> {
let r = T::regs();
Event::from_reg(&r.events_seqend[1])
}
#[inline(always)]
pub fn event_seq0_started(&self) -> Event<'d> {
let r = T::regs();
Event::from_reg(&r.events_seqstarted[0])
}
#[inline(always)]
pub fn event_seq1_started(&self) -> Event<'d> {
let r = T::regs();
Event::from_reg(&r.events_seqstarted[1])
}
#[inline(always)]
pub unsafe fn task_start_seq0(&self) -> Task<'d> {
let r = T::regs();
Task::from_reg(&r.tasks_seqstart[0])
}
#[inline(always)]
pub unsafe fn task_start_seq1(&self) -> Task<'d> {
let r = T::regs();
Task::from_reg(&r.tasks_seqstart[1])
}
#[inline(always)]
pub unsafe fn task_next_step(&self) -> Task<'d> {
let r = T::regs();
Task::from_reg(&r.tasks_nextstep)
}
#[inline(always)]
pub unsafe fn task_stop(&self) -> Task<'d> {
let r = T::regs();
Task::from_reg(&r.tasks_stop)
}
}
impl<'a, T: Instance> Drop for SequencePwm<'a, T> {
fn drop(&mut self) {
let r = T::regs();
if let Some(pin) = &self.ch0 {
pin.set_low();
pin.conf().reset();
r.psel.out[0].reset();
}
if let Some(pin) = &self.ch1 {
pin.set_low();
pin.conf().reset();
r.psel.out[1].reset();
}
if let Some(pin) = &self.ch2 {
pin.set_low();
pin.conf().reset();
r.psel.out[2].reset();
}
if let Some(pin) = &self.ch3 {
pin.set_low();
pin.conf().reset();
r.psel.out[3].reset();
}
}
}
#[non_exhaustive]
pub struct Config {
pub counter_mode: CounterMode,
pub max_duty: u16,
pub prescaler: Prescaler,
pub sequence_load: SequenceLoad,
}
impl Default for Config {
fn default() -> Config {
Config {
counter_mode: CounterMode::Up,
max_duty: 1000,
prescaler: Prescaler::Div16,
sequence_load: SequenceLoad::Common,
}
}
}
#[non_exhaustive]
#[derive(Clone)]
pub struct SequenceConfig {
pub refresh: u32,
pub end_delay: u32,
}
impl Default for SequenceConfig {
fn default() -> SequenceConfig {
SequenceConfig {
refresh: 0,
end_delay: 0,
}
}
}
#[non_exhaustive]
pub struct Sequence<'s> {
pub words: &'s [u16],
pub config: SequenceConfig,
}
impl<'s> Sequence<'s> {
pub fn new(words: &'s [u16], config: SequenceConfig) -> Self {
Self { words, config }
}
}
#[non_exhaustive]
pub struct SingleSequencer<'d, 's, T: Instance> {
sequencer: Sequencer<'d, 's, T>,
}
impl<'d, 's, T: Instance> SingleSequencer<'d, 's, T> {
pub fn new(pwm: &'s mut SequencePwm<'d, T>, words: &'s [u16], config: SequenceConfig) -> Self {
Self {
sequencer: Sequencer::new(pwm, Sequence::new(words, config), None),
}
}
#[inline(always)]
pub fn start(&self, times: SingleSequenceMode) -> Result<(), Error> {
let (start_seq, times) = match times {
SingleSequenceMode::Times(n) if n == 1 => (StartSequence::One, SequenceMode::Loop(1)),
SingleSequenceMode::Times(n) if n & 1 == 1 => (StartSequence::One, SequenceMode::Loop((n / 2) + 1)),
SingleSequenceMode::Times(n) => (StartSequence::Zero, SequenceMode::Loop(n / 2)),
SingleSequenceMode::Infinite => (StartSequence::Zero, SequenceMode::Infinite),
};
self.sequencer.start(start_seq, times)
}
#[inline(always)]
pub fn stop(&self) {
self.sequencer.stop();
}
}
#[non_exhaustive]
pub struct Sequencer<'d, 's, T: Instance> {
_pwm: &'s mut SequencePwm<'d, T>,
sequence0: Sequence<'s>,
sequence1: Option<Sequence<'s>>,
}
impl<'d, 's, T: Instance> Sequencer<'d, 's, T> {
pub fn new(pwm: &'s mut SequencePwm<'d, T>, sequence0: Sequence<'s>, sequence1: Option<Sequence<'s>>) -> Self {
Sequencer {
_pwm: pwm,
sequence0,
sequence1,
}
}
#[inline(always)]
pub fn start(&self, start_seq: StartSequence, times: SequenceMode) -> Result<(), Error> {
let sequence0 = &self.sequence0;
let alt_sequence = self.sequence1.as_ref().unwrap_or(&self.sequence0);
slice_in_ram_or(sequence0.words, Error::BufferNotInRAM)?;
slice_in_ram_or(alt_sequence.words, Error::BufferNotInRAM)?;
if sequence0.words.len() > MAX_SEQUENCE_LEN || alt_sequence.words.len() > MAX_SEQUENCE_LEN {
return Err(Error::SequenceTooLong);
}
if let SequenceMode::Loop(0) = times {
return Err(Error::SequenceTimesAtLeastOne);
}
let _ = self.stop();
let r = T::regs();
r.seq0.refresh.write(|w| unsafe { w.bits(sequence0.config.refresh) });
r.seq0.enddelay.write(|w| unsafe { w.bits(sequence0.config.end_delay) });
r.seq0.ptr.write(|w| unsafe { w.bits(sequence0.words.as_ptr() as u32) });
r.seq0.cnt.write(|w| unsafe { w.bits(sequence0.words.len() as u32) });
r.seq1.refresh.write(|w| unsafe { w.bits(alt_sequence.config.refresh) });
r.seq1
.enddelay
.write(|w| unsafe { w.bits(alt_sequence.config.end_delay) });
r.seq1
.ptr
.write(|w| unsafe { w.bits(alt_sequence.words.as_ptr() as u32) });
r.seq1.cnt.write(|w| unsafe { w.bits(alt_sequence.words.len() as u32) });
r.enable.write(|w| w.enable().enabled());
compiler_fence(Ordering::SeqCst);
let seqstart_index = if start_seq == StartSequence::One { 1 } else { 0 };
match times {
SequenceMode::Loop(n) => {
r.loop_.write(|w| unsafe { w.cnt().bits(n) });
}
SequenceMode::Infinite => {
r.loop_.write(|w| unsafe { w.cnt().bits(0x1) });
r.shorts.write(|w| w.loopsdone_seqstart0().enabled());
}
}
r.tasks_seqstart[seqstart_index].write(|w| unsafe { w.bits(0x01) });
Ok(())
}
#[inline(always)]
pub fn stop(&self) {
let r = T::regs();
r.shorts.reset();
compiler_fence(Ordering::SeqCst);
r.tasks_stop.write(|w| unsafe { w.bits(0x01) });
r.enable.write(|w| w.enable().disabled());
}
}
impl<'d, 's, T: Instance> Drop for Sequencer<'d, 's, T> {
fn drop(&mut self) {
let _ = self.stop();
}
}
#[derive(Debug, Eq, PartialEq, Clone, Copy)]
pub enum SingleSequenceMode {
Times(u16),
Infinite,
}
#[derive(Debug, Eq, PartialEq, Clone, Copy)]
pub enum StartSequence {
Zero,
One,
}
#[derive(Debug, Eq, PartialEq, Clone, Copy)]
pub enum SequenceMode {
Loop(u16),
Infinite,
}
#[derive(Debug, Eq, PartialEq, Clone, Copy)]
pub enum Prescaler {
Div1,
Div2,
Div4,
Div8,
Div16,
Div32,
Div64,
Div128,
}
#[derive(Debug, Eq, PartialEq, Clone, Copy)]
pub enum SequenceLoad {
Common,
Grouped,
Individual,
Waveform,
}
#[derive(Debug, Eq, PartialEq, Clone, Copy)]
pub enum CounterMode {
Up,
UpAndDown,
}
impl<'d, T: Instance> SimplePwm<'d, T> {
#[allow(unused_unsafe)]
pub fn new_1ch(pwm: impl Peripheral<P = T> + 'd, ch0: impl Peripheral<P = impl GpioPin> + 'd) -> Self {
unsafe {
into_ref!(ch0);
Self::new_inner(pwm, Some(ch0.map_into()), None, None, None)
}
}
#[allow(unused_unsafe)]
pub fn new_2ch(
pwm: impl Peripheral<P = T> + 'd,
ch0: impl Peripheral<P = impl GpioPin> + 'd,
ch1: impl Peripheral<P = impl GpioPin> + 'd,
) -> Self {
into_ref!(ch0, ch1);
Self::new_inner(pwm, Some(ch0.map_into()), Some(ch1.map_into()), None, None)
}
#[allow(unused_unsafe)]
pub fn new_3ch(
pwm: impl Peripheral<P = T> + 'd,
ch0: impl Peripheral<P = impl GpioPin> + 'd,
ch1: impl Peripheral<P = impl GpioPin> + 'd,
ch2: impl Peripheral<P = impl GpioPin> + 'd,
) -> Self {
unsafe {
into_ref!(ch0, ch1, ch2);
Self::new_inner(
pwm,
Some(ch0.map_into()),
Some(ch1.map_into()),
Some(ch2.map_into()),
None,
)
}
}
#[allow(unused_unsafe)]
pub fn new_4ch(
pwm: impl Peripheral<P = T> + 'd,
ch0: impl Peripheral<P = impl GpioPin> + 'd,
ch1: impl Peripheral<P = impl GpioPin> + 'd,
ch2: impl Peripheral<P = impl GpioPin> + 'd,
ch3: impl Peripheral<P = impl GpioPin> + 'd,
) -> Self {
unsafe {
into_ref!(ch0, ch1, ch2, ch3);
Self::new_inner(
pwm,
Some(ch0.map_into()),
Some(ch1.map_into()),
Some(ch2.map_into()),
Some(ch3.map_into()),
)
}
}
fn new_inner(
_pwm: impl Peripheral<P = T> + 'd,
ch0: Option<PeripheralRef<'d, AnyPin>>,
ch1: Option<PeripheralRef<'d, AnyPin>>,
ch2: Option<PeripheralRef<'d, AnyPin>>,
ch3: Option<PeripheralRef<'d, AnyPin>>,
) -> Self {
into_ref!(_pwm);
let r = T::regs();
if let Some(pin) = &ch0 {
pin.set_low();
pin.conf().write(|w| w.dir().output());
}
if let Some(pin) = &ch1 {
pin.set_low();
pin.conf().write(|w| w.dir().output());
}
if let Some(pin) = &ch2 {
pin.set_low();
pin.conf().write(|w| w.dir().output());
}
if let Some(pin) = &ch3 {
pin.set_low();
pin.conf().write(|w| w.dir().output());
}
r.psel.out[0].write(|w| unsafe { w.bits(ch0.psel_bits()) });
r.psel.out[1].write(|w| unsafe { w.bits(ch1.psel_bits()) });
r.psel.out[2].write(|w| unsafe { w.bits(ch2.psel_bits()) });
r.psel.out[3].write(|w| unsafe { w.bits(ch3.psel_bits()) });
let pwm = Self {
_peri: _pwm,
ch0,
ch1,
ch2,
ch3,
duty: [0; 4],
};
r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
r.shorts.reset();
r.enable.write(|w| w.enable().enabled());
r.seq0.ptr.write(|w| unsafe { w.bits((&pwm.duty).as_ptr() as u32) });
r.seq0.cnt.write(|w| unsafe { w.bits(4) });
r.seq0.refresh.write(|w| unsafe { w.bits(0) });
r.seq0.enddelay.write(|w| unsafe { w.bits(0) });
r.decoder.write(|w| {
w.load().individual();
w.mode().refresh_count()
});
r.mode.write(|w| w.updown().up());
r.prescaler.write(|w| w.prescaler().div_16());
r.countertop.write(|w| unsafe { w.countertop().bits(1000) });
r.loop_.write(|w| w.cnt().disabled());
pwm
}
#[inline(always)]
pub fn enable(&self) {
let r = T::regs();
r.enable.write(|w| w.enable().enabled());
}
#[inline(always)]
pub fn disable(&self) {
let r = T::regs();
r.enable.write(|w| w.enable().disabled());
}
pub fn set_duty(&mut self, channel: usize, duty: u16) {
let r = T::regs();
self.duty[channel] = duty & 0x7FFF;
r.seq0.ptr.write(|w| unsafe { w.bits((&self.duty).as_ptr() as u32) });
compiler_fence(Ordering::SeqCst);
r.events_seqend[0].reset();
r.tasks_seqstart[0].write(|w| unsafe { w.bits(1) });
while r.events_seqend[0].read().bits() == 0 {}
}
#[inline(always)]
pub fn set_prescaler(&self, div: Prescaler) {
T::regs().prescaler.write(|w| w.prescaler().bits(div as u8));
}
#[inline(always)]
pub fn prescaler(&self) -> Prescaler {
match T::regs().prescaler.read().prescaler().bits() {
0 => Prescaler::Div1,
1 => Prescaler::Div2,
2 => Prescaler::Div4,
3 => Prescaler::Div8,
4 => Prescaler::Div16,
5 => Prescaler::Div32,
6 => Prescaler::Div64,
7 => Prescaler::Div128,
_ => unreachable!(),
}
}
#[inline(always)]
pub fn set_max_duty(&self, duty: u16) {
T::regs()
.countertop
.write(|w| unsafe { w.countertop().bits(duty.min(32767u16)) });
}
#[inline(always)]
pub fn max_duty(&self) -> u16 {
T::regs().countertop.read().countertop().bits()
}
#[inline(always)]
pub fn set_period(&self, freq: u32) {
let clk = 16_000_000u32 >> (self.prescaler() as u8);
let duty = clk / freq;
self.set_max_duty(duty.min(32767) as u16);
}
#[inline(always)]
pub fn period(&self) -> u32 {
let clk = 16_000_000u32 >> (self.prescaler() as u8);
let max_duty = self.max_duty() as u32;
clk / max_duty
}
}
impl<'a, T: Instance> Drop for SimplePwm<'a, T> {
fn drop(&mut self) {
let r = T::regs();
self.disable();
if let Some(pin) = &self.ch0 {
pin.set_low();
pin.conf().reset();
r.psel.out[0].reset();
}
if let Some(pin) = &self.ch1 {
pin.set_low();
pin.conf().reset();
r.psel.out[1].reset();
}
if let Some(pin) = &self.ch2 {
pin.set_low();
pin.conf().reset();
r.psel.out[2].reset();
}
if let Some(pin) = &self.ch3 {
pin.set_low();
pin.conf().reset();
r.psel.out[3].reset();
}
}
}
pub(crate) mod sealed {
use super::*;
pub trait Instance {
fn regs() -> &'static pac::pwm0::RegisterBlock;
}
}
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static {
type Interrupt: interrupt::typelevel::Interrupt;
}
macro_rules! impl_pwm {
($type:ident, $pac_type:ident, $irq:ident) => {
impl crate::pwm::sealed::Instance for peripherals::$type {
fn regs() -> &'static pac::pwm0::RegisterBlock {
unsafe { &*pac::$pac_type::ptr() }
}
}
impl crate::pwm::Instance for peripherals::$type {
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
}